sbc.c revision 1.38.4.1
1 /* $NetBSD: sbc.c,v 1.38.4.1 1999/05/16 22:38:09 scottr Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 #include "opt_ddb.h" 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsipi_debug.h> 61 #include <dev/scsipi/scsiconf.h> 62 63 #include <dev/ic/ncr5380reg.h> 64 #include <dev/ic/ncr5380var.h> 65 66 #include <machine/cpu.h> 67 #include <machine/viareg.h> 68 69 #include <mac68k/dev/sbcreg.h> 70 #include <mac68k/dev/sbcvar.h> 71 72 /* SBC_DEBUG -- relies on DDB */ 73 #ifdef SBC_DEBUG 74 # define SBC_DB_INTR 0x01 75 # define SBC_DB_DMA 0x02 76 # define SBC_DB_REG 0x04 77 # define SBC_DB_BREAK 0x08 78 # ifndef DDB 79 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 80 # endif 81 # define SBC_BREAK \ 82 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 83 #else 84 # define SBC_BREAK 85 #endif 86 87 88 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 89 int sbc_link_flags = 0 /* | SDEV_DB2 */; 90 int sbc_options = 0 /* | SBC_PDMA */; 91 92 /* This is copied from julian's bt driver */ 93 /* "so we have a default dev struct for our link struct." */ 94 struct scsipi_device sbc_dev = { 95 NULL, /* Use default error handler. */ 96 NULL, /* Use default start handler. */ 97 NULL, /* Use default async handler. */ 98 NULL, /* Use default "done" routine. */ 99 }; 100 101 extern label_t *nofault; 102 extern caddr_t m68k_fault_addr; 103 104 static int sbc_wait_busy __P((struct ncr5380_softc *)); 105 static int sbc_ready __P((struct ncr5380_softc *)); 106 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 107 108 109 /*** 110 * General support for Mac-specific SCSI logic. 111 ***/ 112 113 /* These are used in the following inline functions. */ 114 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 115 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 116 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 117 118 /* Return zero on success. */ 119 static __inline__ int 120 sbc_wait_busy(sc) 121 struct ncr5380_softc *sc; 122 { 123 int timo = sbc_wait_busy_timo; 124 for (;;) { 125 if (SCI_BUSY(sc)) { 126 timo = 0; /* return 0 */ 127 break; 128 } 129 if (--timo < 0) 130 break; /* return -1 */ 131 delay(2); 132 } 133 return (timo); 134 } 135 136 static __inline__ int 137 sbc_ready(sc) 138 struct ncr5380_softc *sc; 139 { 140 int timo = sbc_ready_timo; 141 142 for (;;) { 143 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 144 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 145 timo = 0; 146 break; 147 } 148 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 149 || (SCI_BUSY(sc) == 0)) { 150 timo = -1; 151 break; 152 } 153 if (--timo < 0) 154 break; /* return -1 */ 155 delay(2); 156 } 157 return (timo); 158 } 159 160 static __inline__ int 161 sbc_wait_dreq(sc) 162 struct ncr5380_softc *sc; 163 { 164 int timo = sbc_wait_dreq_timo; 165 166 for (;;) { 167 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 168 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 169 timo = 0; 170 break; 171 } 172 if (--timo < 0) 173 break; /* return -1 */ 174 delay(2); 175 } 176 return (timo); 177 } 178 179 void 180 sbc_irq_intr(p) 181 void *p; 182 { 183 struct ncr5380_softc *ncr_sc = p; 184 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 185 int claimed = 0; 186 extern int cold; 187 188 /* How we ever arrive here without IRQ set is a mystery... */ 189 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 190 #ifdef SBC_DEBUG 191 if (sbc_debug & SBC_DB_INTR) 192 decode_5380_intr(ncr_sc); 193 #endif 194 if (!cold) 195 claimed = ncr5380_intr(ncr_sc); 196 if (!claimed) { 197 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 198 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 199 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 200 if (sc->sc_clrintr) 201 (*sc->sc_clrintr)(ncr_sc); 202 } 203 #ifdef SBC_DEBUG 204 else { 205 printf("%s: spurious intr\n", 206 ncr_sc->sc_dev.dv_xname); 207 SBC_BREAK; 208 } 209 #endif 210 } 211 } 212 } 213 214 #ifdef SBC_DEBUG 215 void 216 decode_5380_intr(ncr_sc) 217 struct ncr5380_softc *ncr_sc; 218 { 219 u_int8_t csr = *ncr_sc->sci_csr; 220 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 221 222 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 223 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 224 if (csr & SCI_BUS_IO) 225 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 226 else 227 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 228 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 229 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 230 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 231 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 232 ((bus_csr & ~SCI_BUS_RST) == 0)) 233 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 234 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 235 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 236 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 237 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 238 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 239 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 240 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 241 (bus_csr == 0)) 242 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 243 else 244 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 245 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 246 } 247 #endif 248 249 250 /*** 251 * The following code implements polled PDMA. 252 ***/ 253 254 int 255 sbc_pdma_in(ncr_sc, phase, datalen, data) 256 struct ncr5380_softc *ncr_sc; 257 int phase; 258 int datalen; 259 u_char *data; 260 { 261 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 262 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 263 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 264 int resid, s; 265 266 if (datalen < ncr_sc->sc_min_dma_len || 267 (sc->sc_options & SBC_PDMA) == 0) 268 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 269 270 s = splbio(); 271 if (sbc_wait_busy(ncr_sc)) { 272 splx(s); 273 return 0; 274 } 275 276 *ncr_sc->sci_mode |= SCI_MODE_DMA; 277 *ncr_sc->sci_irecv = 0; 278 279 #define R4 *((u_int32_t *)data)++ = *long_data 280 #define R1 *((u_int8_t *)data)++ = *byte_data 281 for (resid = datalen; resid >= 128; resid -= 128) { 282 if (sbc_ready(ncr_sc)) 283 goto interrupt; 284 R4; R4; R4; R4; R4; R4; R4; R4; 285 R4; R4; R4; R4; R4; R4; R4; R4; 286 R4; R4; R4; R4; R4; R4; R4; R4; 287 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 288 } 289 while (resid) { 290 if (sbc_ready(ncr_sc)) 291 goto interrupt; 292 R1; 293 resid--; 294 } 295 #undef R4 296 #undef R1 297 298 interrupt: 299 SCI_CLR_INTR(ncr_sc); 300 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 301 *ncr_sc->sci_icmd = 0; 302 splx(s); 303 return (datalen - resid); 304 } 305 306 int 307 sbc_pdma_out(ncr_sc, phase, datalen, data) 308 struct ncr5380_softc *ncr_sc; 309 int phase; 310 int datalen; 311 u_char *data; 312 { 313 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 314 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 315 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 316 label_t faultbuf; 317 #if 0 318 int resid, s; 319 #else 320 int s; 321 #endif 322 u_int8_t icmd; 323 324 #if 1 325 /* Work around lame gcc initialization bug */ 326 (void)&data; 327 #endif 328 329 if (datalen < ncr_sc->sc_min_dma_len || 330 (sc->sc_options & SBC_PDMA) == 0) 331 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 332 333 s = splbio(); 334 if (sbc_wait_busy(ncr_sc)) { 335 splx(s); 336 return 0; 337 } 338 339 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 340 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 341 *ncr_sc->sci_mode |= SCI_MODE_DMA; 342 *ncr_sc->sci_dma_send = 0; 343 344 #if 1 345 sc->sc_resid = datalen; 346 #endif 347 348 /* 349 * Setup for a possible bus error caused by SCSI controller 350 * switching out of DATA OUT before we're done with the 351 * current transfer. (See comment before sbc_drq_intr().) 352 */ 353 nofault = &faultbuf; 354 355 if (setjmp(nofault)) { 356 printf("buf = 0x%lx, fault = 0x%lx\n", 357 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 358 #if 0 359 panic("Unexpected bus error in sbc_pdma_out()"); 360 #else 361 sc->sc_resid -= 362 (u_long)m68k_fault_addr - (u_long)sc->sc_drq_addr; 363 goto interrupt; 364 #endif 365 } 366 367 #if 1 368 #define resid sc->sc_resid 369 #define W1 do { \ 370 *byte_data = *((u_int8_t *)data)++; \ 371 resid--; \ 372 } while (0) 373 #define W4 do { \ 374 *long_data = *((u_int32_t *)data)++; \ 375 resid -= 4; \ 376 } while (0) 377 while (resid >= 64) { 378 if (sbc_ready(ncr_sc)) 379 goto interrupt; 380 W4; W4; W4; W4; 381 W4; W4; W4; W4; 382 W4; W4; W4; W4; 383 W4; W4; W4; W4; 384 } 385 #else 386 #define W1 *byte_data = *((u_int8_t *)data)++ 387 #define W4 *long_data = *((u_int32_t *)data)++ 388 for (resid = datalen; resid >= 64; resid -= 64) { 389 if (sbc_ready(ncr_sc)) 390 goto interrupt; 391 W1; 392 if (sbc_ready(ncr_sc)) 393 goto interrupt; 394 W1; 395 if (sbc_ready(ncr_sc)) 396 goto interrupt; 397 W1; 398 if (sbc_ready(ncr_sc)) 399 goto interrupt; 400 W1; 401 if (sbc_ready(ncr_sc)) 402 goto interrupt; 403 W4; W4; W4; W4; 404 W4; W4; W4; W4; 405 W4; W4; W4; W4; 406 W4; W4; W4; 407 } 408 #endif 409 while (resid) { 410 if (sbc_ready(ncr_sc)) 411 goto interrupt; 412 W1; 413 resid--; 414 } 415 #undef W1 416 #undef W4 417 if (sbc_wait_dreq(ncr_sc)) 418 printf("%s: timeout waiting for DREQ.\n", 419 ncr_sc->sc_dev.dv_xname); 420 421 *byte_data = 0; 422 goto done; 423 424 interrupt: 425 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 426 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 427 --resid; 428 } 429 430 done: 431 SCI_CLR_INTR(ncr_sc); 432 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 433 *ncr_sc->sci_icmd = icmd; 434 splx(s); 435 return (datalen - resid); 436 } 437 438 439 /*** 440 * The following code implements interrupt-driven PDMA. 441 ***/ 442 443 /* 444 * This is the meat of the PDMA transfer. 445 * When we get here, we shove data as fast as the mac can take it. 446 * We depend on several things: 447 * * All macs after the Mac Plus that have a 5380 chip should have a general 448 * logic IC that handshakes data for blind transfers. 449 * * If the SCSI controller finishes sending/receiving data before we do, 450 * the same general logic IC will generate a /BERR for us in short order. 451 * * The fault address for said /BERR minus the base address for the 452 * transfer will be the amount of data that was actually written. 453 * 454 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 455 * detect and handle the bus error for early termination of a command. 456 * This is usually caused by a disconnecting target. 457 */ 458 void 459 sbc_drq_intr(p) 460 void *p; 461 { 462 struct sbc_softc *sc = (struct sbc_softc *)p; 463 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 464 struct sci_req *sr = ncr_sc->sc_current; 465 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 466 label_t faultbuf; 467 volatile u_int32_t *long_drq; 468 u_int32_t *long_data; 469 volatile u_int8_t *drq; 470 u_int8_t *data; 471 int count, dcount, resid; 472 u_int8_t tmp; 473 474 /* Work around lame gcc initialization bug */ 475 (void)&drq; 476 477 /* 478 * If we're not ready to xfer data, or have no more, just return. 479 */ 480 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 481 return; 482 483 #ifdef SBC_DEBUG 484 if (sbc_debug & SBC_DB_INTR) 485 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 486 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 487 #endif 488 489 /* 490 * Setup for a possible bus error caused by SCSI controller 491 * switching out of DATA-IN/OUT before we're done with the 492 * current transfer. 493 */ 494 nofault = &faultbuf; 495 496 if (setjmp(nofault)) { 497 nofault = (label_t *)0; 498 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 499 count = (( (u_long)m68k_fault_addr 500 - (u_long)sc->sc_drq_addr)); 501 502 if ((count < 0) || (count > dh->dh_len)) { 503 printf("%s: complete=0x%x (pending 0x%x)\n", 504 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 505 panic("something is wrong"); 506 } 507 508 dh->dh_addr += count; 509 dh->dh_len -= count; 510 } else 511 count = 0; 512 513 #ifdef SBC_DEBUG 514 if (sbc_debug & SBC_DB_INTR) 515 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 516 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 517 #endif 518 m68k_fault_addr = 0; 519 520 return; 521 } 522 523 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 524 dcount = 0; 525 526 /* 527 * Get the source address aligned. 528 */ 529 resid = 530 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 531 if (count && count < 4) { 532 drq = (volatile u_int8_t *)sc->sc_drq_addr; 533 data = (u_int8_t *)dh->dh_addr; 534 535 #define W1 *drq++ = *data++ 536 while (count) { 537 W1; count--; 538 } 539 #undef W1 540 dh->dh_addr += resid; 541 dh->dh_len -= resid; 542 } 543 544 /* 545 * Start the transfer. 546 */ 547 while (dh->dh_len) { 548 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 549 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 550 long_data = (u_int32_t *)dh->dh_addr; 551 552 #define W4 *long_drq++ = *long_data++ 553 while (count >= 64) { 554 W4; W4; W4; W4; W4; W4; W4; W4; 555 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 556 count -= 64; 557 } 558 while (count >= 4) { 559 W4; count -= 4; 560 } 561 #undef W4 562 data = (u_int8_t *)long_data; 563 drq = (u_int8_t *)long_drq; 564 565 #define W1 *drq++ = *data++ 566 while (count) { 567 W1; count--; 568 } 569 #undef W1 570 dh->dh_len -= dcount; 571 dh->dh_addr += dcount; 572 } 573 dh->dh_flags |= SBC_DH_DONE; 574 575 /* 576 * XXX -- Read a byte from the SBC to trigger a /BERR. 577 * This seems to be necessary for us to notice that 578 * the target has disconnected. Ick. 06 jun 1996 (sr) 579 */ 580 if (dcount >= MAX_DMA_LEN) 581 drq = (volatile u_int8_t *)sc->sc_drq_addr; 582 tmp = *drq; 583 } else { /* Data In */ 584 /* 585 * Get the dest address aligned. 586 */ 587 resid = 588 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 589 if (count && count < 4) { 590 data = (u_int8_t *)dh->dh_addr; 591 drq = (volatile u_int8_t *)sc->sc_drq_addr; 592 593 #define R1 *data++ = *drq++ 594 while (count) { 595 R1; count--; 596 } 597 #undef R1 598 dh->dh_addr += resid; 599 dh->dh_len -= resid; 600 } 601 602 /* 603 * Start the transfer. 604 */ 605 while (dh->dh_len) { 606 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 607 long_data = (u_int32_t *)dh->dh_addr; 608 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 609 610 #define R4 *long_data++ = *long_drq++ 611 while (count >= 64) { 612 R4; R4; R4; R4; R4; R4; R4; R4; 613 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 614 count -= 64; 615 } 616 while (count >= 4) { 617 R4; count -= 4; 618 } 619 #undef R4 620 data = (u_int8_t *)long_data; 621 drq = (volatile u_int8_t *)long_drq; 622 623 #define R1 *data++ = *drq++ 624 while (count) { 625 R1; count--; 626 } 627 #undef R1 628 dh->dh_len -= dcount; 629 dh->dh_addr += dcount; 630 } 631 dh->dh_flags |= SBC_DH_DONE; 632 } 633 634 /* 635 * OK. No bus error occurred above. Clear the nofault flag 636 * so we no longer short-circuit bus errors. 637 */ 638 nofault = (label_t *)0; 639 640 #ifdef SBC_DEBUG 641 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 642 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 643 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 644 *ncr_sc->sci_bus_csr); 645 #endif 646 } 647 648 void 649 sbc_dma_alloc(ncr_sc) 650 struct ncr5380_softc *ncr_sc; 651 { 652 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 653 struct sci_req *sr = ncr_sc->sc_current; 654 struct scsipi_xfer *xs = sr->sr_xs; 655 struct sbc_pdma_handle *dh; 656 int i, xlen; 657 658 #ifdef DIAGNOSTIC 659 if (sr->sr_dma_hand != NULL) 660 panic("sbc_dma_alloc: already have PDMA handle"); 661 #endif 662 663 /* Polled transfers shouldn't allocate a PDMA handle. */ 664 if (sr->sr_flags & SR_IMMED) 665 return; 666 667 xlen = ncr_sc->sc_datalen; 668 669 /* Make sure our caller checked sc_min_dma_len. */ 670 if (xlen < MIN_DMA_LEN) 671 panic("sbc_dma_alloc: len=0x%x\n", xlen); 672 673 /* 674 * Find free PDMA handle. Guaranteed to find one since we 675 * have as many PDMA handles as the driver has processes. 676 * (instances?) 677 */ 678 for (i = 0; i < SCI_OPENINGS; i++) { 679 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 680 goto found; 681 } 682 panic("sbc: no free PDMA handles"); 683 found: 684 dh = &sc->sc_pdma[i]; 685 dh->dh_flags = SBC_DH_BUSY; 686 dh->dh_addr = ncr_sc->sc_dataptr; 687 dh->dh_len = xlen; 688 689 /* Copy the 'write' flag for convenience. */ 690 if (xs->flags & SCSI_DATA_OUT) 691 dh->dh_flags |= SBC_DH_OUT; 692 693 sr->sr_dma_hand = dh; 694 } 695 696 void 697 sbc_dma_free(ncr_sc) 698 struct ncr5380_softc *ncr_sc; 699 { 700 struct sci_req *sr = ncr_sc->sc_current; 701 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 702 703 #ifdef DIAGNOSTIC 704 if (sr->sr_dma_hand == NULL) 705 panic("sbc_dma_free: no DMA handle"); 706 #endif 707 708 if (ncr_sc->sc_state & NCR_DOINGDMA) 709 panic("sbc_dma_free: free while in progress"); 710 711 if (dh->dh_flags & SBC_DH_BUSY) { 712 dh->dh_flags = 0; 713 dh->dh_addr = NULL; 714 dh->dh_len = 0; 715 } 716 sr->sr_dma_hand = NULL; 717 } 718 719 void 720 sbc_dma_poll(ncr_sc) 721 struct ncr5380_softc *ncr_sc; 722 { 723 struct sci_req *sr = ncr_sc->sc_current; 724 725 /* 726 * We shouldn't arrive here; if SR_IMMED is set, then 727 * dma_alloc() should have refused to allocate a handle 728 * for the transfer. This forces the polled PDMA code 729 * to handle the request... 730 */ 731 #ifdef SBC_DEBUG 732 if (sbc_debug & SBC_DB_DMA) 733 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 734 #endif 735 sr->sr_flags |= SR_OVERDUE; 736 } 737 738 void 739 sbc_dma_setup(ncr_sc) 740 struct ncr5380_softc *ncr_sc; 741 { 742 /* Not needed; we don't have real DMA */ 743 } 744 745 void 746 sbc_dma_start(ncr_sc) 747 struct ncr5380_softc *ncr_sc; 748 { 749 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 750 struct sci_req *sr = ncr_sc->sc_current; 751 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 752 753 /* 754 * Match bus phase, clear pending interrupts, set DMA mode, and 755 * assert data bus (for writing only), then start the transfer. 756 */ 757 if (dh->dh_flags & SBC_DH_OUT) { 758 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 759 SCI_CLR_INTR(ncr_sc); 760 if (sc->sc_clrintr) 761 (*sc->sc_clrintr)(ncr_sc); 762 *ncr_sc->sci_mode |= SCI_MODE_DMA; 763 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 764 *ncr_sc->sci_dma_send = 0; 765 } else { 766 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 767 SCI_CLR_INTR(ncr_sc); 768 if (sc->sc_clrintr) 769 (*sc->sc_clrintr)(ncr_sc); 770 *ncr_sc->sci_mode |= SCI_MODE_DMA; 771 *ncr_sc->sci_icmd = 0; 772 *ncr_sc->sci_irecv = 0; 773 } 774 ncr_sc->sc_state |= NCR_DOINGDMA; 775 776 #ifdef SBC_DEBUG 777 if (sbc_debug & SBC_DB_DMA) 778 printf("%s: PDMA started, va=%p, len=0x%x\n", 779 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 780 #endif 781 } 782 783 void 784 sbc_dma_eop(ncr_sc) 785 struct ncr5380_softc *ncr_sc; 786 { 787 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 788 } 789 790 void 791 sbc_dma_stop(ncr_sc) 792 struct ncr5380_softc *ncr_sc; 793 { 794 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 795 struct sci_req *sr = ncr_sc->sc_current; 796 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 797 int ntrans; 798 799 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 800 #ifdef SBC_DEBUG 801 if (sbc_debug & SBC_DB_DMA) 802 printf("%s: dma_stop: DMA not running\n", 803 ncr_sc->sc_dev.dv_xname); 804 #endif 805 return; 806 } 807 ncr_sc->sc_state &= ~NCR_DOINGDMA; 808 809 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 810 ntrans = ncr_sc->sc_datalen - dh->dh_len; 811 812 #ifdef SBC_DEBUG 813 if (sbc_debug & SBC_DB_DMA) 814 printf("%s: dma_stop: ntrans=0x%x\n", 815 ncr_sc->sc_dev.dv_xname, ntrans); 816 #endif 817 818 if (ntrans > ncr_sc->sc_datalen) 819 panic("sbc_dma_stop: excess transfer\n"); 820 821 /* Adjust data pointer */ 822 ncr_sc->sc_dataptr += ntrans; 823 ncr_sc->sc_datalen -= ntrans; 824 825 /* Clear any pending interrupts. */ 826 SCI_CLR_INTR(ncr_sc); 827 if (sc->sc_clrintr) 828 (*sc->sc_clrintr)(ncr_sc); 829 } 830 831 /* Put SBIC back into PIO mode. */ 832 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 833 *ncr_sc->sci_icmd = 0; 834 835 #ifdef SBC_DEBUG 836 if (sbc_debug & SBC_DB_REG) 837 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 838 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 839 *ncr_sc->sci_bus_csr); 840 #endif 841 } 842
Indexes created Thu Oct 02 14:10:14 GMT 2025