sbc.c revision 1.4
1 /* $NetBSD: sbc.c,v 1.4 1996/04/30 18:11:38 scottr Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott Reynolds 5 * Copyright (c) 1995 David Jones 6 * Copyright (c) 1995 Allen Briggs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the authors may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 4. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by David Jones, Allen 22 * Briggs and Scott Reynolds. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * This file contains only the machine-dependent parts of the mac68k 38 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 39 * The machine-independent parts are in ncr5380sbc.c 40 * 41 * Supported hardware includes: 42 * Macintosh II family 5380-based controller 43 * 44 * Credits, history: 45 * 46 * Scott Reynolds wrote this module, based on work by Allen Briggs 47 * (mac68k), David Jones (sun3), and Leo Weppelman (atari). Allen 48 * supplied some crucial interpretation of the NetBSD 1.1 'ncrscsi' 49 * driver. Allen, Gordon W. Ross, and Jason Thorpe all helped to 50 * refine this code, and were considerable sources of moral support. 51 * 52 * The sbc_options code is based on similar code in Jason's modified 53 * NetBSD/sparc 'si' driver. 54 */ 55 56 #include <sys/types.h> 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/kernel.h> 60 #include <sys/errno.h> 61 #include <sys/device.h> 62 #include <sys/buf.h> 63 #include <sys/proc.h> 64 #include <sys/user.h> 65 66 #include <scsi/scsi_all.h> 67 #include <scsi/scsi_debug.h> 68 #include <scsi/scsiconf.h> 69 70 #include <dev/ic/ncr5380reg.h> 71 #include <dev/ic/ncr5380var.h> 72 73 #include <machine/viareg.h> 74 75 #include "sbcreg.h" 76 77 /* 78 * Transfers smaller than this are done using PIO 79 * (on assumption they're not worth PDMA overhead) 80 */ 81 #define MIN_DMA_LEN 128 82 83 /* 84 * Transfers larger than 8192 bytes need to be split up 85 * due to the size of the PDMA space. 86 */ 87 #define MAX_DMA_LEN 0x2000 88 89 /* 90 * From Guide to the Macintosh Family Hardware, p. 137 91 * These are offsets from SCSIBase (see pmap_bootstrap.c) 92 */ 93 #define SBC_REGISTER_OFFSET 0x10000 94 #define SBC_DMA_DRQ_OFFSET 0x06000 95 #define SBC_DMA_NODRQ_OFFSET 0x12000 96 97 #ifdef SBC_DEBUG 98 # define SBC_DB_INTR 0x01 99 # define SBC_DB_DMA 0x02 100 # define SBC_DB_REG 0x04 101 # define SBC_DB_BREAK 0x08 102 103 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 104 int sbc_link_flags = 0 /* | SDEV_DB2 */; 105 106 # ifndef DDB 107 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 108 # endif 109 # define SBC_BREAK \ 110 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 111 #else 112 # define SBC_BREAK 113 #endif 114 115 /* 116 * This structure is used to keep track of PDMA requests. 117 */ 118 struct sbc_pdma_handle { 119 int dh_flags; /* flags */ 120 #define SBC_DH_BUSY 0x01 /* This handle is in use */ 121 #define SBC_DH_OUT 0x02 /* PDMA data out (write) */ 122 u_char *dh_addr; /* data buffer */ 123 int dh_len; /* length of data buffer */ 124 }; 125 126 /* 127 * The first structure member has to be the ncr5380_softc 128 * so we can just cast to go back and forth between them. 129 */ 130 struct sbc_softc { 131 struct ncr5380_softc ncr_sc; 132 volatile struct sbc_regs *sc_regs; 133 volatile long *sc_drq_addr; 134 volatile u_char *sc_nodrq_addr; 135 volatile u_char *sc_ienable; 136 volatile u_char *sc_iflag; 137 int sc_options; /* options for this instance. */ 138 struct sbc_pdma_handle sc_pdma[SCI_OPENINGS]; 139 }; 140 141 /* 142 * Options. By default, SCSI interrupts and reselect are disabled. 143 * You may enable either of these features with the `flags' directive 144 * in your kernel's configuration file. 145 * 146 * Alternatively, you can patch your kernel with DDB or some other 147 * mechanism. The sc_options member of the softc is OR'd with 148 * the value in sbc_options. 149 */ 150 #define SBC_INTR 0x01 /* Allow SCSI IRQ/DRQ interrupts */ 151 #define SBC_RESELECT 0x02 /* Allow disconnect/reselect */ 152 #define SBC_OPTIONS_MASK (SBC_INTR|SBC_RESELECT) 153 #define SBC_OPTIONS_BITS "\10\2RESELECT\1INTR" 154 int sbc_options = 0; 155 156 static int sbc_print __P((void *, char *)); 157 static int sbc_match __P((struct device *, void *, void *)); 158 static void sbc_attach __P((struct device *, struct device *, void *)); 159 static void sbc_minphys __P((struct buf *bp)); 160 161 static int sbc_wait_busy __P((struct ncr5380_softc *)); 162 static int sbc_ready __P((struct ncr5380_softc *)); 163 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 164 static int sbc_pdma_in __P((struct ncr5380_softc *, int, int, u_char *)); 165 static int sbc_pdma_out __P((struct ncr5380_softc *, int, int, u_char *)); 166 #ifdef SBC_DEBUG 167 static void decode_5380_intr __P((struct ncr5380_softc *)); 168 #endif 169 170 void sbc_intr_enable __P((struct ncr5380_softc *)); 171 void sbc_intr_disable __P((struct ncr5380_softc *)); 172 void sbc_irq_intr __P((void *)); 173 void sbc_drq_intr __P((void *)); 174 void sbc_dma_alloc __P((struct ncr5380_softc *)); 175 void sbc_dma_free __P((struct ncr5380_softc *)); 176 void sbc_dma_poll __P((struct ncr5380_softc *)); 177 void sbc_dma_setup __P((struct ncr5380_softc *)); 178 void sbc_dma_start __P((struct ncr5380_softc *)); 179 void sbc_dma_eop __P((struct ncr5380_softc *)); 180 void sbc_dma_stop __P((struct ncr5380_softc *)); 181 182 static struct scsi_adapter sbc_ops = { 183 ncr5380_scsi_cmd, /* scsi_cmd() */ 184 sbc_minphys, /* scsi_minphys() */ 185 NULL, /* open_target_lu() */ 186 NULL, /* close_target_lu() */ 187 }; 188 189 /* This is copied from julian's bt driver */ 190 /* "so we have a default dev struct for our link struct." */ 191 static struct scsi_device sbc_dev = { 192 NULL, /* Use default error handler. */ 193 NULL, /* Use default start handler. */ 194 NULL, /* Use default async handler. */ 195 NULL, /* Use default "done" routine. */ 196 }; 197 198 struct cfattach sbc_ca = { 199 sizeof(struct sbc_softc), sbc_match, sbc_attach 200 }; 201 202 struct cfdriver sbc_cd = { 203 NULL, "sbc", DV_DULL 204 }; 205 206 207 static int 208 sbc_print(aux, name) 209 void *aux; 210 char *name; 211 { 212 if (name != NULL) 213 printf("%s: scsibus ", name); 214 return UNCONF; 215 } 216 217 static int 218 sbc_match(parent, match, args) 219 struct device *parent; 220 void *match, *args; 221 { 222 struct device *self = match; /* XXX mainbus is "indirect" */ 223 struct confargs *ca = args; 224 225 if (matchbyname(parent, match, ca) == 0) 226 return 0; 227 if (!mac68k_machine.scsi80) 228 return 0; 229 if (self->dv_cfdata->cf_unit != 0) 230 return 0; 231 return 1; 232 } 233 234 static void 235 sbc_attach(parent, self, args) 236 struct device *parent, *self; 237 void *args; 238 { 239 struct sbc_softc *sc = (struct sbc_softc *) self; 240 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) sc; 241 extern vm_offset_t SCSIBase; 242 243 /* Pull in the options flags. */ 244 sc->sc_options = 245 ((ncr_sc->sc_dev.dv_cfdata->cf_flags | sbc_options) & SBC_OPTIONS_MASK); 246 247 /* 248 * Set up base address of 5380 249 */ 250 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REGISTER_OFFSET); 251 252 /* 253 * Fill in the prototype scsi_link. 254 */ 255 ncr_sc->sc_link.adapter_softc = sc; 256 ncr_sc->sc_link.adapter_target = 7; 257 ncr_sc->sc_link.adapter = &sbc_ops; 258 ncr_sc->sc_link.device = &sbc_dev; 259 260 /* 261 * Initialize fields used by the MI code 262 */ 263 ncr_sc->sci_r0 = &sc->sc_regs->sci_pr0.sci_reg; 264 ncr_sc->sci_r1 = &sc->sc_regs->sci_pr1.sci_reg; 265 ncr_sc->sci_r2 = &sc->sc_regs->sci_pr2.sci_reg; 266 ncr_sc->sci_r3 = &sc->sc_regs->sci_pr3.sci_reg; 267 ncr_sc->sci_r4 = &sc->sc_regs->sci_pr4.sci_reg; 268 ncr_sc->sci_r5 = &sc->sc_regs->sci_pr5.sci_reg; 269 ncr_sc->sci_r6 = &sc->sc_regs->sci_pr6.sci_reg; 270 ncr_sc->sci_r7 = &sc->sc_regs->sci_pr7.sci_reg; 271 272 /* 273 * MD function pointers used by the MI code. 274 */ 275 ncr_sc->sc_pio_out = sbc_pdma_out; 276 ncr_sc->sc_pio_in = sbc_pdma_in; 277 ncr_sc->sc_dma_alloc = NULL; 278 ncr_sc->sc_dma_free = NULL; 279 ncr_sc->sc_dma_poll = NULL; 280 ncr_sc->sc_intr_on = NULL; 281 ncr_sc->sc_intr_off = NULL; 282 ncr_sc->sc_dma_setup = NULL; 283 ncr_sc->sc_dma_start = NULL; 284 ncr_sc->sc_dma_eop = NULL; 285 ncr_sc->sc_dma_stop = NULL; 286 ncr_sc->sc_flags = 0; 287 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 288 289 /* 290 * MD function pointers used by the MI code. 291 */ 292 if ((sc->sc_options & SBC_INTR) == 0) { 293 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 294 } else { 295 if (sc->sc_options & SBC_RESELECT) 296 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 297 ncr_sc->sc_dma_alloc = sbc_dma_alloc; 298 ncr_sc->sc_dma_free = sbc_dma_free; 299 ncr_sc->sc_dma_poll = sbc_dma_poll; 300 ncr_sc->sc_dma_setup = sbc_dma_setup; 301 ncr_sc->sc_dma_start = sbc_dma_start; 302 ncr_sc->sc_dma_eop = sbc_dma_eop; 303 ncr_sc->sc_dma_stop = sbc_dma_stop; 304 mac68k_register_scsi_drq(sbc_drq_intr, ncr_sc); 305 mac68k_register_scsi_irq(sbc_irq_intr, ncr_sc); 306 } 307 308 /* 309 * Initialize fields used only here in the MD code. 310 */ 311 sc->sc_drq_addr = (long *) (SCSIBase + SBC_DMA_DRQ_OFFSET); 312 sc->sc_nodrq_addr = (u_char *) (SCSIBase + SBC_DMA_NODRQ_OFFSET); 313 if (VIA2 == VIA2OFF) { 314 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + vIER; 315 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + vIFR; 316 } else { 317 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + rIER; 318 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + rIFR; 319 } 320 321 if (sc->sc_options) 322 printf(": options=%b", sc->sc_options, SBC_OPTIONS_BITS); 323 printf("\n"); 324 325 /* Now enable SCSI interrupts through VIA2, if appropriate */ 326 if (sc->sc_options & SBC_INTR) 327 sbc_intr_enable(ncr_sc); 328 329 #ifdef SBC_DEBUG 330 if (sbc_debug) 331 printf("%s: softc=%p regs=%p\n", ncr_sc->sc_dev.dv_xname, 332 sc, sc->sc_regs); 333 ncr_sc->sc_link.flags |= sbc_link_flags; 334 #endif 335 336 /* 337 * Initialize the SCSI controller itself. 338 */ 339 ncr5380_init(ncr_sc); 340 ncr5380_reset_scsibus(ncr_sc); 341 config_found(self, &(ncr_sc->sc_link), sbc_print); 342 } 343 344 345 static void 346 sbc_minphys(struct buf *bp) 347 { 348 if (bp->b_bcount > MAX_DMA_LEN) 349 bp->b_bcount = MAX_DMA_LEN; 350 return (minphys(bp)); 351 } 352 353 354 /*** 355 * General support for Mac-specific SCSI logic. 356 ***/ 357 358 /* These are used in the following inline functions. */ 359 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 360 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 361 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 362 363 /* Return zero on success. */ 364 static __inline__ int 365 sbc_wait_busy(sc) 366 struct ncr5380_softc *sc; 367 { 368 register int timo = sbc_wait_busy_timo; 369 for (;;) { 370 if (SCI_BUSY(sc)) { 371 timo = 0; /* return 0 */ 372 break; 373 } 374 if (--timo < 0) 375 break; /* return -1 */ 376 delay(2); 377 } 378 return (timo); 379 } 380 381 static __inline__ int 382 sbc_ready(sc) 383 struct ncr5380_softc *sc; 384 { 385 register int timo = sbc_ready_timo; 386 387 for (;;) { 388 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 389 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 390 timo = 0; 391 break; 392 } 393 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 394 || (SCI_BUSY(sc) == 0)) { 395 timo = -1; 396 break; 397 } 398 if (--timo < 0) 399 break; /* return -1 */ 400 delay(2); 401 } 402 return (timo); 403 } 404 405 static __inline__ int 406 sbc_wait_dreq(sc) 407 struct ncr5380_softc *sc; 408 { 409 register int timo = sbc_wait_dreq_timo; 410 411 for (;;) { 412 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 413 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 414 timo = 0; 415 break; 416 } 417 if (--timo < 0) 418 break; /* return -1 */ 419 delay(2); 420 } 421 return (timo); 422 } 423 424 425 /*** 426 * Macintosh SCSI interrupt support routines. 427 ***/ 428 429 void 430 sbc_intr_enable(ncr_sc) 431 struct ncr5380_softc *ncr_sc; 432 { 433 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 434 int s; 435 436 s = splhigh(); 437 *sc->sc_iflag = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 438 *sc->sc_ienable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 439 splx(s); 440 } 441 442 void 443 sbc_intr_disable(ncr_sc) 444 struct ncr5380_softc *ncr_sc; 445 { 446 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 447 int s; 448 449 s = splhigh(); 450 *sc->sc_ienable = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 451 splx(s); 452 } 453 454 void 455 sbc_irq_intr(p) 456 void *p; 457 { 458 static int handling_sbc_intr = 0; 459 register struct ncr5380_softc *ncr_sc = p; 460 register int claimed = 0; 461 462 /* How we ever arrive here without IRQ set is a mystery... */ 463 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 464 /* 465 * For some reason, the hardware sometimes generates a 466 * spurious selection interrupt. I don't know why this 467 * happens, but the following hack works around it. --sar 468 */ 469 if (handling_sbc_intr) 470 return; 471 handling_sbc_intr++; 472 473 #ifdef SBC_DEBUG 474 if (sbc_debug & SBC_DB_INTR) 475 decode_5380_intr(ncr_sc); 476 #endif 477 claimed = ncr5380_intr(ncr_sc); 478 if (!claimed) { 479 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 480 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 481 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 482 #ifdef SBC_DEBUG 483 else { 484 printf("%s: spurious intr\n", 485 ncr_sc->sc_dev.dv_xname); 486 SBC_BREAK; 487 } 488 #endif 489 } 490 491 /* We can handle another interrupt from the SBC now. */ 492 handling_sbc_intr = 0; 493 } 494 } 495 496 #ifdef SBC_DEBUG 497 void 498 decode_5380_intr(ncr_sc) 499 struct ncr5380_softc *ncr_sc; 500 { 501 register u_char csr = *ncr_sc->sci_csr; 502 register u_char bus_csr = *ncr_sc->sci_bus_csr; 503 504 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 505 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 506 if (csr & SCI_BUS_IO) 507 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 508 else 509 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 510 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 511 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 512 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 513 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 514 ((bus_csr & ~SCI_BUS_RST) == 0)) 515 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 516 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 517 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 518 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 519 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 520 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 521 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 522 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 523 (bus_csr == 0)) 524 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 525 else 526 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 527 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 528 } 529 #endif 530 531 /*** 532 * The following code implements polled PDMA. 533 ***/ 534 535 static int 536 sbc_pdma_out(ncr_sc, phase, count, data) 537 struct ncr5380_softc *ncr_sc; 538 int phase; 539 int count; 540 u_char *data; 541 { 542 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 543 register volatile long *long_data = sc->sc_drq_addr; 544 register volatile u_char *byte_data = sc->sc_nodrq_addr; 545 register int len = count; 546 547 if (count < ncr_sc->sc_min_dma_len) 548 return ncr5380_pio_out(ncr_sc, phase, count, data); 549 550 if (sbc_wait_busy(ncr_sc) == 0) { 551 *ncr_sc->sci_mode &= ~SCI_MODE_MONBSY; /* XXX */ 552 *ncr_sc->sci_mode |= SCI_MODE_DMA; 553 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 554 *ncr_sc->sci_dma_send = 0; 555 556 #define W1 *byte_data = *data++ 557 #define W4 *long_data = *((long*)data)++ 558 while (len >= 64) { 559 if (sbc_ready(ncr_sc)) 560 goto timeout; 561 W1; 562 if (sbc_ready(ncr_sc)) 563 goto timeout; 564 W1; 565 if (sbc_ready(ncr_sc)) 566 goto timeout; 567 W1; 568 if (sbc_ready(ncr_sc)) 569 goto timeout; 570 W1; 571 if (sbc_ready(ncr_sc)) 572 goto timeout; 573 W4; W4; W4; W4; 574 W4; W4; W4; W4; 575 W4; W4; W4; W4; 576 W4; W4; W4; 577 len -= 64; 578 } 579 while (len) { 580 if (sbc_ready(ncr_sc)) 581 goto timeout; 582 W1; 583 len--; 584 } 585 #undef W1 586 #undef W4 587 if (sbc_wait_dreq(ncr_sc)) 588 printf("%s: timeout waiting for DREQ.\n", 589 ncr_sc->sc_dev.dv_xname); 590 591 *byte_data = 0; 592 593 SCI_CLR_INTR(ncr_sc); 594 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 595 *ncr_sc->sci_icmd = 0; 596 } 597 return count - len; 598 599 timeout: 600 printf("%s: pdma_out: timeout len=%d count=%d\n", 601 ncr_sc->sc_dev.dv_xname, len, count); 602 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 603 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 604 --len; 605 } 606 607 SCI_CLR_INTR(ncr_sc); 608 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 609 *ncr_sc->sci_icmd = 0; 610 return count - len; 611 } 612 613 static int 614 sbc_pdma_in(ncr_sc, phase, count, data) 615 struct ncr5380_softc *ncr_sc; 616 int phase; 617 int count; 618 u_char *data; 619 { 620 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 621 register volatile long *long_data = sc->sc_drq_addr; 622 register volatile u_char *byte_data = sc->sc_nodrq_addr; 623 register int len = count; 624 625 if (count < ncr_sc->sc_min_dma_len) 626 return ncr5380_pio_in(ncr_sc, phase, count, data); 627 628 if (sbc_wait_busy(ncr_sc) == 0) { 629 *ncr_sc->sci_mode &= ~SCI_MODE_MONBSY; /* XXX */ 630 *ncr_sc->sci_mode |= SCI_MODE_DMA; 631 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 632 *ncr_sc->sci_irecv = 0; 633 634 #define R4 *((long *)data)++ = *long_data 635 #define R1 *data++ = *byte_data 636 while (len >= 1024) { 637 if (sbc_ready(ncr_sc)) 638 goto timeout; 639 R4; R4; R4; R4; R4; R4; R4; R4; 640 R4; R4; R4; R4; R4; R4; R4; R4; 641 R4; R4; R4; R4; R4; R4; R4; R4; 642 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 643 if (sbc_ready(ncr_sc)) 644 goto timeout; 645 R4; R4; R4; R4; R4; R4; R4; R4; 646 R4; R4; R4; R4; R4; R4; R4; R4; 647 R4; R4; R4; R4; R4; R4; R4; R4; 648 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 649 if (sbc_ready(ncr_sc)) 650 goto timeout; 651 R4; R4; R4; R4; R4; R4; R4; R4; 652 R4; R4; R4; R4; R4; R4; R4; R4; 653 R4; R4; R4; R4; R4; R4; R4; R4; 654 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 655 if (sbc_ready(ncr_sc)) 656 goto timeout; 657 R4; R4; R4; R4; R4; R4; R4; R4; 658 R4; R4; R4; R4; R4; R4; R4; R4; 659 R4; R4; R4; R4; R4; R4; R4; R4; 660 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 661 if (sbc_ready(ncr_sc)) 662 goto timeout; 663 R4; R4; R4; R4; R4; R4; R4; R4; 664 R4; R4; R4; R4; R4; R4; R4; R4; 665 R4; R4; R4; R4; R4; R4; R4; R4; 666 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 667 if (sbc_ready(ncr_sc)) 668 goto timeout; 669 R4; R4; R4; R4; R4; R4; R4; R4; 670 R4; R4; R4; R4; R4; R4; R4; R4; 671 R4; R4; R4; R4; R4; R4; R4; R4; 672 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 673 if (sbc_ready(ncr_sc)) 674 goto timeout; 675 R4; R4; R4; R4; R4; R4; R4; R4; 676 R4; R4; R4; R4; R4; R4; R4; R4; 677 R4; R4; R4; R4; R4; R4; R4; R4; 678 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 679 if (sbc_ready(ncr_sc)) 680 goto timeout; 681 R4; R4; R4; R4; R4; R4; R4; R4; 682 R4; R4; R4; R4; R4; R4; R4; R4; 683 R4; R4; R4; R4; R4; R4; R4; R4; 684 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 685 len -= 1024; 686 } 687 while (len >= 128) { 688 if (sbc_ready(ncr_sc)) 689 goto timeout; 690 R4; R4; R4; R4; R4; R4; R4; R4; 691 R4; R4; R4; R4; R4; R4; R4; R4; 692 R4; R4; R4; R4; R4; R4; R4; R4; 693 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 694 len -= 128; 695 } 696 while (len) { 697 if (sbc_ready(ncr_sc)) 698 goto timeout; 699 R1; 700 len--; 701 } 702 #undef R4 703 #undef R1 704 SCI_CLR_INTR(ncr_sc); 705 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 706 *ncr_sc->sci_icmd = 0; 707 } 708 return count - len; 709 710 timeout: 711 printf("%s: pdma_in: timeout len=%d count=%d\n", 712 ncr_sc->sc_dev.dv_xname, len, count); 713 714 SCI_CLR_INTR(ncr_sc); 715 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 716 *ncr_sc->sci_icmd = 0; 717 return count - len; 718 } 719 720 721 /*** 722 * The following code implements interrupt-driven PDMA. 723 ***/ 724 725 /* 726 * This is the meat of the PDMA transfer. 727 * When we get here, we shove data as fast as the mac can take it. 728 * We depend on several things: 729 * * All macs after the Mac Plus that have a 5380 chip should have a general 730 * logic IC that handshakes data for blind transfers. 731 * * If the SCSI controller finishes sending/receiving data before we do, 732 * the same general logic IC will generate a /BERR for us in short order. 733 * * The fault address for said /BERR minus the base address for the 734 * transfer will be the amount of data that was actually written. 735 * 736 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 737 * detect and handle the bus error for early termination of a command. 738 * This is usually caused by a disconnecting target. 739 */ 740 void 741 sbc_drq_intr(p) 742 void *p; 743 { 744 extern int *nofault, mac68k_buserr_addr; 745 register struct sbc_softc *sc = (struct sbc_softc *) p; 746 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 747 register struct sci_req *sr = ncr_sc->sc_current; 748 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 749 label_t faultbuf; 750 volatile u_int32_t *long_drq; 751 u_int32_t *long_data; 752 volatile u_int8_t *drq; 753 u_int8_t *data; 754 register int count; 755 int dcount, resid; 756 757 /* 758 * If we're not ready to xfer data, or have no more, just return. 759 */ 760 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 761 return; 762 763 #ifdef SBC_DEBUG 764 if (sbc_debug & SBC_DB_INTR) 765 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 766 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 767 #endif 768 769 /* 770 * Setup for a possible bus error caused by SCSI controller 771 * switching out of DATA-IN/OUT before we're done with the 772 * current transfer. 773 */ 774 nofault = (int *) &faultbuf; 775 776 if (setjmp((label_t *) nofault)) { 777 nofault = (int *) 0; 778 count = ( (u_long) mac68k_buserr_addr 779 - (u_long) sc->sc_drq_addr); 780 781 if ((count < 0) || (count > dh->dh_len)) { 782 printf("%s: complete=0x%x (pending 0x%x)\n", 783 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 784 panic("something is wrong"); 785 } 786 #ifdef SBC_DEBUG 787 if (sbc_debug & SBC_DB_INTR) 788 printf("%s: drq /berr, pending=0x%x, complete=0x%x\n", 789 ncr_sc->sc_dev.dv_xname, dh->dh_len, count); 790 #endif 791 792 dh->dh_addr += count; 793 dh->dh_len -= count; 794 mac68k_buserr_addr = 0; 795 796 return; 797 } 798 799 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 800 /* 801 * Get the source address aligned. 802 */ 803 resid = count = min(dh->dh_len, 804 4 - (((int) dh->dh_addr) & 0x3)); 805 if (count && count < 4) { 806 data = (u_int8_t *) dh->dh_addr; 807 drq = (u_int8_t *) sc->sc_drq_addr; 808 #define W1 *drq++ = *data++ 809 while (count) { 810 W1; count--; 811 } 812 #undef W1 813 dh->dh_addr += resid; 814 dh->dh_len -= resid; 815 } 816 817 /* 818 * Get ready to start the transfer. 819 */ 820 while (dh->dh_len) { 821 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 822 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 823 long_data = (u_int32_t *) dh->dh_addr; 824 825 #define W4 *long_drq++ = *long_data++ 826 while (count >= 64) { 827 W4; W4; W4; W4; W4; W4; W4; W4; 828 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 829 count -= 64; 830 } 831 while (count >= 4) { 832 W4; count -= 4; 833 } 834 #undef W4 835 data = (u_int8_t *) long_data; 836 drq = (u_int8_t *) long_drq; 837 #define W1 *drq++ = *data++ 838 while (count) { 839 W1; count--; 840 } 841 #undef W1 842 dh->dh_len -= dcount; 843 dh->dh_addr += dcount; 844 } 845 } else { /* Data In */ 846 /* 847 * Get the dest address aligned. 848 */ 849 resid = count = min(dh->dh_len, 850 4 - (((int) dh->dh_addr) & 0x3)); 851 if (count && count < 4) { 852 data = (u_int8_t *) dh->dh_addr; 853 drq = (u_int8_t *) sc->sc_drq_addr; 854 #define R1 *data++ = *drq++ 855 while (count) { 856 R1; count--; 857 } 858 #undef R1 859 dh->dh_addr += resid; 860 dh->dh_len -= resid; 861 } 862 863 /* 864 * Get ready to start the transfer. 865 */ 866 while (dh->dh_len) { 867 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 868 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 869 long_data = (u_int32_t *) dh->dh_addr; 870 871 #define R4 *long_data++ = *long_drq++ 872 while (count >= 512) { 873 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0) { 874 nofault = (int *) 0; 875 876 dh->dh_addr += (dcount - count); 877 dh->dh_len -= (dcount - count); 878 return; 879 } 880 R4; R4; R4; R4; R4; R4; R4; R4; 881 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 882 R4; R4; R4; R4; R4; R4; R4; R4; 883 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 884 R4; R4; R4; R4; R4; R4; R4; R4; 885 R4; R4; R4; R4; R4; R4; R4; R4; 886 R4; R4; R4; R4; R4; R4; R4; R4; 887 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 888 R4; R4; R4; R4; R4; R4; R4; R4; 889 R4; R4; R4; R4; R4; R4; R4; R4; 890 R4; R4; R4; R4; R4; R4; R4; R4; 891 R4; R4; R4; R4; R4; R4; R4; R4; 892 R4; R4; R4; R4; R4; R4; R4; R4; 893 R4; R4; R4; R4; R4; R4; R4; R4; 894 R4; R4; R4; R4; R4; R4; R4; R4; 895 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 896 count -= 512; 897 } 898 while (count >= 4) { 899 R4; count -= 4; 900 } 901 #undef R4 902 data = (u_int8_t *) long_data; 903 drq = (u_int8_t *) long_drq; 904 #define R1 *data++ = *drq++ 905 while (count) { 906 R1; count--; 907 } 908 #undef R1 909 dh->dh_len -= dcount; 910 dh->dh_addr += dcount; 911 } 912 } 913 914 /* 915 * OK. No bus error occurred above. Clear the nofault flag 916 * so we no longer short-circuit bus errors. 917 */ 918 nofault = (int *) 0; 919 } 920 921 void 922 sbc_dma_alloc(ncr_sc) 923 struct ncr5380_softc *ncr_sc; 924 { 925 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 926 struct sci_req *sr = ncr_sc->sc_current; 927 struct scsi_xfer *xs = sr->sr_xs; 928 struct sbc_pdma_handle *dh; 929 int i, xlen; 930 931 #ifdef DIAGNOSTIC 932 if (sr->sr_dma_hand != NULL) 933 panic("sbc_dma_alloc: already have PDMA handle"); 934 #endif 935 936 /* Polled transfers shouldn't allocate a PDMA handle. */ 937 if (sr->sr_flags & SR_IMMED) 938 return; 939 940 /* XXX - we don't trust PDMA writes yet! */ 941 if (xs->flags & SCSI_DATA_OUT) 942 return; 943 944 xlen = ncr_sc->sc_datalen; 945 946 /* Make sure our caller checked sc_min_dma_len. */ 947 if (xlen < MIN_DMA_LEN) 948 panic("sbc_dma_alloc: len=0x%x\n", xlen); 949 950 /* 951 * Find free PDMA handle. Guaranteed to find one since we 952 * have as many PDMA handles as the driver has processes. 953 * (instances?) 954 */ 955 for (i = 0; i < SCI_OPENINGS; i++) { 956 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 957 goto found; 958 } 959 panic("sbc: no free PDMA handles"); 960 found: 961 dh = &sc->sc_pdma[i]; 962 dh->dh_flags = SBC_DH_BUSY; 963 dh->dh_addr = ncr_sc->sc_dataptr; 964 dh->dh_len = xlen; 965 966 /* Copy the 'write' flag for convenience. */ 967 if (xs->flags & SCSI_DATA_OUT) 968 dh->dh_flags |= SBC_DH_OUT; 969 970 sr->sr_dma_hand = dh; 971 } 972 973 void 974 sbc_dma_free(ncr_sc) 975 struct ncr5380_softc *ncr_sc; 976 { 977 struct sci_req *sr = ncr_sc->sc_current; 978 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 979 980 #ifdef DIAGNOSTIC 981 if (sr->sr_dma_hand == NULL) 982 panic("sbc_dma_free: no DMA handle"); 983 #endif 984 985 if (ncr_sc->sc_state & NCR_DOINGDMA) 986 panic("sbc_dma_free: free while in progress"); 987 988 if (dh->dh_flags & SBC_DH_BUSY) { 989 dh->dh_flags = 0; 990 dh->dh_addr = NULL; 991 dh->dh_len = 0; 992 } 993 sr->sr_dma_hand = NULL; 994 } 995 996 void 997 sbc_dma_poll(ncr_sc) 998 struct ncr5380_softc *ncr_sc; 999 { 1000 struct sci_req *sr = ncr_sc->sc_current; 1001 1002 /* 1003 * We shouldn't arrive here; if SR_IMMED is set, then 1004 * dma_alloc() should have refused to allocate a handle 1005 * for the transfer. This forces the polled PDMA code 1006 * to handle the request... 1007 */ 1008 #ifdef SBC_DEBUG 1009 if (sbc_debug & SBC_DB_DMA) 1010 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 1011 #endif 1012 sr->sr_flags |= SR_OVERDUE; 1013 } 1014 1015 void 1016 sbc_dma_setup(ncr_sc) 1017 struct ncr5380_softc *ncr_sc; 1018 { 1019 /* Not needed; we don't have real DMA */ 1020 } 1021 1022 void 1023 sbc_dma_start(ncr_sc) 1024 struct ncr5380_softc *ncr_sc; 1025 { 1026 struct sci_req *sr = ncr_sc->sc_current; 1027 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1028 1029 /* 1030 * Match bus phase, set DMA mode, and assert data bus (for 1031 * writing only), then start the transfer. 1032 */ 1033 if (dh->dh_flags & SBC_DH_OUT) { 1034 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 1035 SCI_CLR_INTR(ncr_sc); 1036 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1037 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 1038 *ncr_sc->sci_dma_send = 0; 1039 } else { 1040 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 1041 SCI_CLR_INTR(ncr_sc); 1042 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1043 *ncr_sc->sci_icmd = 0; 1044 *ncr_sc->sci_irecv = 0; 1045 } 1046 ncr_sc->sc_state |= NCR_DOINGDMA; 1047 1048 #ifdef SBC_DEBUG 1049 if (sbc_debug & SBC_DB_DMA) 1050 printf("%s: PDMA started, va=%p, len=0x%x\n", 1051 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 1052 #endif 1053 } 1054 1055 void 1056 sbc_dma_eop(ncr_sc) 1057 struct ncr5380_softc *ncr_sc; 1058 { 1059 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 1060 } 1061 1062 void 1063 sbc_dma_stop(ncr_sc) 1064 struct ncr5380_softc *ncr_sc; 1065 { 1066 struct sci_req *sr = ncr_sc->sc_current; 1067 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1068 register int ntrans; 1069 1070 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 1071 #ifdef SBC_DEBUG 1072 if (sbc_debug & SBC_DB_DMA) 1073 printf("%s: dma_stop: DMA not running\n", 1074 ncr_sc->sc_dev.dv_xname); 1075 #endif 1076 return; 1077 } 1078 ncr_sc->sc_state &= ~NCR_DOINGDMA; 1079 1080 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 1081 ntrans = ncr_sc->sc_datalen - dh->dh_len; 1082 1083 #ifdef SBC_DEBUG 1084 if (sbc_debug & SBC_DB_DMA) 1085 printf("%s: dma_stop: ntrans=0x%x\n", 1086 ncr_sc->sc_dev.dv_xname, ntrans); 1087 #endif 1088 1089 if (ntrans > ncr_sc->sc_datalen) 1090 panic("sbc_dma_stop: excess transfer\n"); 1091 1092 /* Adjust data pointer */ 1093 ncr_sc->sc_dataptr += ntrans; 1094 ncr_sc->sc_datalen -= ntrans; 1095 1096 /* Clear any pending interrupts. */ 1097 SCI_CLR_INTR(ncr_sc); 1098 } 1099 1100 /* Put SBIC back into PIO mode. */ 1101 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 1102 *ncr_sc->sci_icmd = 0; 1103 1104 #ifdef SBC_DEBUG 1105 if (sbc_debug & SBC_DB_REG) 1106 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 1107 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 1108 *ncr_sc->sci_bus_csr); 1109 #endif 1110 } 1111
Indexes created Wed Sep 24 22:09:59 GMT 2025