sbc.c revision 1.44
1 /* $NetBSD: sbc.c,v 1.44 2003/07/15 02:43:18 lukem Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.44 2003/07/15 02:43:18 lukem Exp $"); 49 50 #include "opt_ddb.h" 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/buf.h> 59 #include <sys/proc.h> 60 #include <sys/user.h> 61 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsipi_all.h> 64 #include <dev/scsipi/scsipi_debug.h> 65 #include <dev/scsipi/scsiconf.h> 66 67 #include <dev/ic/ncr5380reg.h> 68 #include <dev/ic/ncr5380var.h> 69 70 #include <machine/cpu.h> 71 #include <machine/viareg.h> 72 73 #include <mac68k/dev/sbcreg.h> 74 #include <mac68k/dev/sbcvar.h> 75 76 /* SBC_DEBUG -- relies on DDB */ 77 #ifdef SBC_DEBUG 78 # define SBC_DB_INTR 0x01 79 # define SBC_DB_DMA 0x02 80 # define SBC_DB_REG 0x04 81 # define SBC_DB_BREAK 0x08 82 # ifndef DDB 83 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 84 # endif 85 # define SBC_BREAK \ 86 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 87 #else 88 # define SBC_BREAK 89 #endif 90 91 92 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 93 int sbc_link_flags = 0 /* | SDEV_DB2 */; 94 int sbc_options = 0 /* | SBC_PDMA */; 95 96 extern label_t *nofault; 97 extern caddr_t m68k_fault_addr; 98 99 static int sbc_wait_busy __P((struct ncr5380_softc *)); 100 static int sbc_ready __P((struct ncr5380_softc *)); 101 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 102 103 104 /*** 105 * General support for Mac-specific SCSI logic. 106 ***/ 107 108 /* These are used in the following inline functions. */ 109 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 110 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 111 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 112 113 /* Return zero on success. */ 114 static __inline__ int 115 sbc_wait_busy(sc) 116 struct ncr5380_softc *sc; 117 { 118 int timo = sbc_wait_busy_timo; 119 for (;;) { 120 if (SCI_BUSY(sc)) { 121 timo = 0; /* return 0 */ 122 break; 123 } 124 if (--timo < 0) 125 break; /* return -1 */ 126 delay(2); 127 } 128 return (timo); 129 } 130 131 static __inline__ int 132 sbc_ready(sc) 133 struct ncr5380_softc *sc; 134 { 135 int timo = sbc_ready_timo; 136 137 for (;;) { 138 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 139 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 140 timo = 0; 141 break; 142 } 143 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 144 || (SCI_BUSY(sc) == 0)) { 145 timo = -1; 146 break; 147 } 148 if (--timo < 0) 149 break; /* return -1 */ 150 delay(2); 151 } 152 return (timo); 153 } 154 155 static __inline__ int 156 sbc_wait_dreq(sc) 157 struct ncr5380_softc *sc; 158 { 159 int timo = sbc_wait_dreq_timo; 160 161 for (;;) { 162 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 163 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 164 timo = 0; 165 break; 166 } 167 if (--timo < 0) 168 break; /* return -1 */ 169 delay(2); 170 } 171 return (timo); 172 } 173 174 void 175 sbc_irq_intr(p) 176 void *p; 177 { 178 struct ncr5380_softc *ncr_sc = p; 179 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 180 int claimed = 0; 181 182 /* How we ever arrive here without IRQ set is a mystery... */ 183 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 184 #ifdef SBC_DEBUG 185 if (sbc_debug & SBC_DB_INTR) 186 decode_5380_intr(ncr_sc); 187 #endif 188 if (!cold) 189 claimed = ncr5380_intr(ncr_sc); 190 if (!claimed) { 191 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 192 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 193 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 194 if (sc->sc_clrintr) 195 (*sc->sc_clrintr)(ncr_sc); 196 } 197 #ifdef SBC_DEBUG 198 else { 199 printf("%s: spurious intr\n", 200 ncr_sc->sc_dev.dv_xname); 201 SBC_BREAK; 202 } 203 #endif 204 } 205 } 206 } 207 208 #ifdef SBC_DEBUG 209 void 210 decode_5380_intr(ncr_sc) 211 struct ncr5380_softc *ncr_sc; 212 { 213 u_int8_t csr = *ncr_sc->sci_csr; 214 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 215 216 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 217 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 218 if (csr & SCI_BUS_IO) 219 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 220 else 221 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 222 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 223 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 224 printf("%s: DMA eop\n", ncr_sc->sc_dev.dv_xname); 225 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 226 ((bus_csr & ~SCI_BUS_RST) == 0)) 227 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 228 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 229 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 230 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 231 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 232 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 233 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 234 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 235 (bus_csr == 0)) 236 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 237 else 238 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 239 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 240 } 241 #endif 242 243 244 /*** 245 * The following code implements polled PDMA. 246 ***/ 247 248 int 249 sbc_pdma_in(ncr_sc, phase, datalen, data) 250 struct ncr5380_softc *ncr_sc; 251 int phase; 252 int datalen; 253 u_char *data; 254 { 255 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 256 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 257 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 258 int resid, s; 259 260 if (datalen < ncr_sc->sc_min_dma_len || 261 (sc->sc_options & SBC_PDMA) == 0) 262 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 263 264 s = splbio(); 265 if (sbc_wait_busy(ncr_sc)) { 266 splx(s); 267 return 0; 268 } 269 270 *ncr_sc->sci_mode |= SCI_MODE_DMA; 271 *ncr_sc->sci_irecv = 0; 272 273 #define R4 *((u_int32_t *)data)++ = *long_data 274 #define R1 *((u_int8_t *)data)++ = *byte_data 275 for (resid = datalen; resid >= 128; resid -= 128) { 276 if (sbc_ready(ncr_sc)) 277 goto interrupt; 278 R4; R4; R4; R4; R4; R4; R4; R4; 279 R4; R4; R4; R4; R4; R4; R4; R4; 280 R4; R4; R4; R4; R4; R4; R4; R4; 281 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 282 } 283 while (resid) { 284 if (sbc_ready(ncr_sc)) 285 goto interrupt; 286 R1; 287 resid--; 288 } 289 #undef R4 290 #undef R1 291 292 interrupt: 293 SCI_CLR_INTR(ncr_sc); 294 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 295 *ncr_sc->sci_icmd = 0; 296 splx(s); 297 return (datalen - resid); 298 } 299 300 int 301 sbc_pdma_out(ncr_sc, phase, datalen, data) 302 struct ncr5380_softc *ncr_sc; 303 int phase; 304 int datalen; 305 u_char *data; 306 { 307 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 308 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 309 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 310 label_t faultbuf; 311 int resid, s; 312 u_int8_t icmd; 313 314 #if 1 315 /* Work around lame gcc initialization bug */ 316 (void)&data; 317 #endif 318 319 if (datalen < ncr_sc->sc_min_dma_len || 320 (sc->sc_options & SBC_PDMA) == 0) 321 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 322 323 s = splbio(); 324 if (sbc_wait_busy(ncr_sc)) { 325 splx(s); 326 return 0; 327 } 328 329 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 330 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 331 *ncr_sc->sci_mode |= SCI_MODE_DMA; 332 *ncr_sc->sci_dma_send = 0; 333 334 /* 335 * Setup for a possible bus error caused by SCSI controller 336 * switching out of DATA OUT before we're done with the 337 * current transfer. (See comment before sbc_drq_intr().) 338 */ 339 nofault = &faultbuf; 340 341 if (setjmp(nofault)) { 342 printf("buf = 0x%lx, fault = 0x%lx\n", 343 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 344 panic("Unexpected bus error in sbc_pdma_out()"); 345 } 346 347 #define W1 *byte_data = *((u_int8_t *)data)++ 348 #define W4 *long_data = *((u_int32_t *)data)++ 349 for (resid = datalen; resid >= 64; resid -= 64) { 350 if (sbc_ready(ncr_sc)) 351 goto interrupt; 352 W1; 353 if (sbc_ready(ncr_sc)) 354 goto interrupt; 355 W1; 356 if (sbc_ready(ncr_sc)) 357 goto interrupt; 358 W1; 359 if (sbc_ready(ncr_sc)) 360 goto interrupt; 361 W1; 362 if (sbc_ready(ncr_sc)) 363 goto interrupt; 364 W4; W4; W4; W4; 365 W4; W4; W4; W4; 366 W4; W4; W4; W4; 367 W4; W4; W4; 368 } 369 while (resid) { 370 if (sbc_ready(ncr_sc)) 371 goto interrupt; 372 W1; 373 resid--; 374 } 375 #undef W1 376 #undef W4 377 if (sbc_wait_dreq(ncr_sc)) 378 printf("%s: timeout waiting for DREQ.\n", 379 ncr_sc->sc_dev.dv_xname); 380 381 *byte_data = 0; 382 goto done; 383 384 interrupt: 385 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 386 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 387 --resid; 388 } 389 390 done: 391 SCI_CLR_INTR(ncr_sc); 392 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 393 *ncr_sc->sci_icmd = icmd; 394 splx(s); 395 return (datalen - resid); 396 } 397 398 399 /*** 400 * The following code implements interrupt-driven PDMA. 401 ***/ 402 403 /* 404 * This is the meat of the PDMA transfer. 405 * When we get here, we shove data as fast as the mac can take it. 406 * We depend on several things: 407 * * All macs after the Mac Plus that have a 5380 chip should have a general 408 * logic IC that handshakes data for blind transfers. 409 * * If the SCSI controller finishes sending/receiving data before we do, 410 * the same general logic IC will generate a /BERR for us in short order. 411 * * The fault address for said /BERR minus the base address for the 412 * transfer will be the amount of data that was actually written. 413 * 414 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 415 * detect and handle the bus error for early termination of a command. 416 * This is usually caused by a disconnecting target. 417 */ 418 void 419 sbc_drq_intr(p) 420 void *p; 421 { 422 struct sbc_softc *sc = (struct sbc_softc *)p; 423 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 424 struct sci_req *sr = ncr_sc->sc_current; 425 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 426 label_t faultbuf; 427 volatile u_int32_t *long_drq; 428 u_int32_t *long_data; 429 volatile u_int8_t *drq; 430 u_int8_t *data; 431 int count, dcount, resid; 432 u_int8_t tmp; 433 434 /* Work around lame gcc initialization bug */ 435 (void)&drq; 436 437 /* 438 * If we're not ready to xfer data, or have no more, just return. 439 */ 440 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 441 return; 442 443 #ifdef SBC_DEBUG 444 if (sbc_debug & SBC_DB_INTR) 445 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 446 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 447 #endif 448 449 /* 450 * Setup for a possible bus error caused by SCSI controller 451 * switching out of DATA-IN/OUT before we're done with the 452 * current transfer. 453 */ 454 nofault = &faultbuf; 455 456 if (setjmp(nofault)) { 457 nofault = (label_t *)0; 458 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 459 count = (( (u_long)m68k_fault_addr 460 - (u_long)sc->sc_drq_addr)); 461 462 if ((count < 0) || (count > dh->dh_len)) { 463 printf("%s: complete=0x%x (pending 0x%x)\n", 464 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 465 panic("something is wrong"); 466 } 467 468 dh->dh_addr += count; 469 dh->dh_len -= count; 470 } else 471 count = 0; 472 473 #ifdef SBC_DEBUG 474 if (sbc_debug & SBC_DB_INTR) 475 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 476 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 477 #endif 478 m68k_fault_addr = 0; 479 480 return; 481 } 482 483 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 484 dcount = 0; 485 486 /* 487 * Get the source address aligned. 488 */ 489 resid = 490 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 491 if (count && count < 4) { 492 drq = (volatile u_int8_t *)sc->sc_drq_addr; 493 data = (u_int8_t *)dh->dh_addr; 494 495 #define W1 *drq++ = *data++ 496 while (count) { 497 W1; count--; 498 } 499 #undef W1 500 dh->dh_addr += resid; 501 dh->dh_len -= resid; 502 } 503 504 /* 505 * Start the transfer. 506 */ 507 while (dh->dh_len) { 508 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 509 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 510 long_data = (u_int32_t *)dh->dh_addr; 511 512 #define W4 *long_drq++ = *long_data++ 513 while (count >= 64) { 514 W4; W4; W4; W4; W4; W4; W4; W4; 515 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 516 count -= 64; 517 } 518 while (count >= 4) { 519 W4; count -= 4; 520 } 521 #undef W4 522 data = (u_int8_t *)long_data; 523 drq = (u_int8_t *)long_drq; 524 525 #define W1 *drq++ = *data++ 526 while (count) { 527 W1; count--; 528 } 529 #undef W1 530 dh->dh_len -= dcount; 531 dh->dh_addr += dcount; 532 } 533 dh->dh_flags |= SBC_DH_DONE; 534 535 /* 536 * XXX -- Read a byte from the SBC to trigger a /BERR. 537 * This seems to be necessary for us to notice that 538 * the target has disconnected. Ick. 06 jun 1996 (sr) 539 */ 540 if (dcount >= MAX_DMA_LEN) 541 drq = (volatile u_int8_t *)sc->sc_drq_addr; 542 tmp = *drq; 543 } else { /* Data In */ 544 /* 545 * Get the dest address aligned. 546 */ 547 resid = 548 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 549 if (count && count < 4) { 550 data = (u_int8_t *)dh->dh_addr; 551 drq = (volatile u_int8_t *)sc->sc_drq_addr; 552 553 #define R1 *data++ = *drq++ 554 while (count) { 555 R1; count--; 556 } 557 #undef R1 558 dh->dh_addr += resid; 559 dh->dh_len -= resid; 560 } 561 562 /* 563 * Start the transfer. 564 */ 565 while (dh->dh_len) { 566 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 567 long_data = (u_int32_t *)dh->dh_addr; 568 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 569 570 #define R4 *long_data++ = *long_drq++ 571 while (count >= 64) { 572 R4; R4; R4; R4; R4; R4; R4; R4; 573 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 574 count -= 64; 575 } 576 while (count >= 4) { 577 R4; count -= 4; 578 } 579 #undef R4 580 data = (u_int8_t *)long_data; 581 drq = (volatile u_int8_t *)long_drq; 582 583 #define R1 *data++ = *drq++ 584 while (count) { 585 R1; count--; 586 } 587 #undef R1 588 dh->dh_len -= dcount; 589 dh->dh_addr += dcount; 590 } 591 dh->dh_flags |= SBC_DH_DONE; 592 } 593 594 /* 595 * OK. No bus error occurred above. Clear the nofault flag 596 * so we no longer short-circuit bus errors. 597 */ 598 nofault = (label_t *)0; 599 600 #ifdef SBC_DEBUG 601 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 602 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 603 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 604 *ncr_sc->sci_bus_csr); 605 #endif 606 } 607 608 void 609 sbc_dma_alloc(ncr_sc) 610 struct ncr5380_softc *ncr_sc; 611 { 612 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 613 struct sci_req *sr = ncr_sc->sc_current; 614 struct scsipi_xfer *xs = sr->sr_xs; 615 struct sbc_pdma_handle *dh; 616 int i, xlen; 617 618 #ifdef DIAGNOSTIC 619 if (sr->sr_dma_hand != NULL) 620 panic("sbc_dma_alloc: already have PDMA handle"); 621 #endif 622 623 /* Polled transfers shouldn't allocate a PDMA handle. */ 624 if (sr->sr_flags & SR_IMMED) 625 return; 626 627 xlen = ncr_sc->sc_datalen; 628 629 /* Make sure our caller checked sc_min_dma_len. */ 630 if (xlen < MIN_DMA_LEN) 631 panic("sbc_dma_alloc: len=0x%x", xlen); 632 633 /* 634 * Find free PDMA handle. Guaranteed to find one since we 635 * have as many PDMA handles as the driver has processes. 636 * (instances?) 637 */ 638 for (i = 0; i < SCI_OPENINGS; i++) { 639 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 640 goto found; 641 } 642 panic("sbc: no free PDMA handles"); 643 found: 644 dh = &sc->sc_pdma[i]; 645 dh->dh_flags = SBC_DH_BUSY; 646 dh->dh_addr = ncr_sc->sc_dataptr; 647 dh->dh_len = xlen; 648 649 /* Copy the 'write' flag for convenience. */ 650 if (xs->xs_control & XS_CTL_DATA_OUT) 651 dh->dh_flags |= SBC_DH_OUT; 652 653 sr->sr_dma_hand = dh; 654 } 655 656 void 657 sbc_dma_free(ncr_sc) 658 struct ncr5380_softc *ncr_sc; 659 { 660 struct sci_req *sr = ncr_sc->sc_current; 661 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 662 663 #ifdef DIAGNOSTIC 664 if (sr->sr_dma_hand == NULL) 665 panic("sbc_dma_free: no DMA handle"); 666 #endif 667 668 if (ncr_sc->sc_state & NCR_DOINGDMA) 669 panic("sbc_dma_free: free while in progress"); 670 671 if (dh->dh_flags & SBC_DH_BUSY) { 672 dh->dh_flags = 0; 673 dh->dh_addr = NULL; 674 dh->dh_len = 0; 675 } 676 sr->sr_dma_hand = NULL; 677 } 678 679 void 680 sbc_dma_poll(ncr_sc) 681 struct ncr5380_softc *ncr_sc; 682 { 683 struct sci_req *sr = ncr_sc->sc_current; 684 685 /* 686 * We shouldn't arrive here; if SR_IMMED is set, then 687 * dma_alloc() should have refused to allocate a handle 688 * for the transfer. This forces the polled PDMA code 689 * to handle the request... 690 */ 691 #ifdef SBC_DEBUG 692 if (sbc_debug & SBC_DB_DMA) 693 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 694 #endif 695 sr->sr_flags |= SR_OVERDUE; 696 } 697 698 void 699 sbc_dma_setup(ncr_sc) 700 struct ncr5380_softc *ncr_sc; 701 { 702 /* Not needed; we don't have real DMA */ 703 } 704 705 void 706 sbc_dma_start(ncr_sc) 707 struct ncr5380_softc *ncr_sc; 708 { 709 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 710 struct sci_req *sr = ncr_sc->sc_current; 711 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 712 713 /* 714 * Match bus phase, clear pending interrupts, set DMA mode, and 715 * assert data bus (for writing only), then start the transfer. 716 */ 717 if (dh->dh_flags & SBC_DH_OUT) { 718 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 719 SCI_CLR_INTR(ncr_sc); 720 if (sc->sc_clrintr) 721 (*sc->sc_clrintr)(ncr_sc); 722 *ncr_sc->sci_mode |= SCI_MODE_DMA; 723 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 724 *ncr_sc->sci_dma_send = 0; 725 } else { 726 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 727 SCI_CLR_INTR(ncr_sc); 728 if (sc->sc_clrintr) 729 (*sc->sc_clrintr)(ncr_sc); 730 *ncr_sc->sci_mode |= SCI_MODE_DMA; 731 *ncr_sc->sci_icmd = 0; 732 *ncr_sc->sci_irecv = 0; 733 } 734 ncr_sc->sc_state |= NCR_DOINGDMA; 735 736 #ifdef SBC_DEBUG 737 if (sbc_debug & SBC_DB_DMA) 738 printf("%s: PDMA started, va=%p, len=0x%x\n", 739 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 740 #endif 741 } 742 743 void 744 sbc_dma_eop(ncr_sc) 745 struct ncr5380_softc *ncr_sc; 746 { 747 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 748 } 749 750 void 751 sbc_dma_stop(ncr_sc) 752 struct ncr5380_softc *ncr_sc; 753 { 754 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 755 struct sci_req *sr = ncr_sc->sc_current; 756 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 757 int ntrans; 758 759 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 760 #ifdef SBC_DEBUG 761 if (sbc_debug & SBC_DB_DMA) 762 printf("%s: dma_stop: DMA not running\n", 763 ncr_sc->sc_dev.dv_xname); 764 #endif 765 return; 766 } 767 ncr_sc->sc_state &= ~NCR_DOINGDMA; 768 769 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 770 ntrans = ncr_sc->sc_datalen - dh->dh_len; 771 772 #ifdef SBC_DEBUG 773 if (sbc_debug & SBC_DB_DMA) 774 printf("%s: dma_stop: ntrans=0x%x\n", 775 ncr_sc->sc_dev.dv_xname, ntrans); 776 #endif 777 778 if (ntrans > ncr_sc->sc_datalen) 779 panic("sbc_dma_stop: excess transfer"); 780 781 /* Adjust data pointer */ 782 ncr_sc->sc_dataptr += ntrans; 783 ncr_sc->sc_datalen -= ntrans; 784 785 /* Clear any pending interrupts. */ 786 SCI_CLR_INTR(ncr_sc); 787 if (sc->sc_clrintr) 788 (*sc->sc_clrintr)(ncr_sc); 789 } 790 791 /* Put SBIC back into PIO mode. */ 792 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 793 *ncr_sc->sci_icmd = 0; 794 795 #ifdef SBC_DEBUG 796 if (sbc_debug & SBC_DB_REG) 797 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 798 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 799 *ncr_sc->sci_bus_csr); 800 #endif 801 } 802
Indexes created Mon Sep 22 05:09:51 GMT 2025