sbc.c revision 1.46
1 /* $NetBSD: sbc.c,v 1.46 2005/06/16 22:43:36 jmc Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.46 2005/06/16 22:43:36 jmc Exp $"); 49 50 #include "opt_ddb.h" 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/buf.h> 59 #include <sys/proc.h> 60 #include <sys/user.h> 61 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsipi_all.h> 64 #include <dev/scsipi/scsipi_debug.h> 65 #include <dev/scsipi/scsiconf.h> 66 67 #include <dev/ic/ncr5380reg.h> 68 #include <dev/ic/ncr5380var.h> 69 70 #include <machine/cpu.h> 71 #include <machine/viareg.h> 72 73 #include <mac68k/dev/sbcreg.h> 74 #include <mac68k/dev/sbcvar.h> 75 76 /* SBC_DEBUG -- relies on DDB */ 77 #ifdef SBC_DEBUG 78 # define SBC_DB_INTR 0x01 79 # define SBC_DB_DMA 0x02 80 # define SBC_DB_REG 0x04 81 # define SBC_DB_BREAK 0x08 82 # ifndef DDB 83 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 84 # endif 85 # define SBC_BREAK \ 86 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 87 #else 88 # define SBC_BREAK 89 #endif 90 91 92 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 93 int sbc_link_flags = 0 /* | SDEV_DB2 */; 94 int sbc_options = 0 /* | SBC_PDMA */; 95 96 extern label_t *nofault; 97 extern caddr_t m68k_fault_addr; 98 99 static int sbc_wait_busy(struct ncr5380_softc *); 100 static int sbc_ready(struct ncr5380_softc *); 101 static int sbc_wait_dreq(struct ncr5380_softc *); 102 103 104 /*** 105 * General support for Mac-specific SCSI logic. 106 ***/ 107 108 /* These are used in the following inline functions. */ 109 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 110 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 111 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 112 113 /* Return zero on success. */ 114 static __inline__ int 115 sbc_wait_busy(struct ncr5380_softc *sc) 116 { 117 int timo = sbc_wait_busy_timo; 118 for (;;) { 119 if (SCI_BUSY(sc)) { 120 timo = 0; /* return 0 */ 121 break; 122 } 123 if (--timo < 0) 124 break; /* return -1 */ 125 delay(2); 126 } 127 return (timo); 128 } 129 130 static __inline__ int 131 sbc_ready(struct ncr5380_softc *sc) 132 { 133 int timo = sbc_ready_timo; 134 135 for (;;) { 136 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 137 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 138 timo = 0; 139 break; 140 } 141 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 142 || (SCI_BUSY(sc) == 0)) { 143 timo = -1; 144 break; 145 } 146 if (--timo < 0) 147 break; /* return -1 */ 148 delay(2); 149 } 150 return (timo); 151 } 152 153 static __inline__ int 154 sbc_wait_dreq(struct ncr5380_softc *sc) 155 { 156 int timo = sbc_wait_dreq_timo; 157 158 for (;;) { 159 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 160 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 161 timo = 0; 162 break; 163 } 164 if (--timo < 0) 165 break; /* return -1 */ 166 delay(2); 167 } 168 return (timo); 169 } 170 171 void 172 sbc_irq_intr(void *p) 173 { 174 struct ncr5380_softc *ncr_sc = p; 175 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 176 int claimed = 0; 177 178 /* How we ever arrive here without IRQ set is a mystery... */ 179 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 180 #ifdef SBC_DEBUG 181 if (sbc_debug & SBC_DB_INTR) 182 decode_5380_intr(ncr_sc); 183 #endif 184 if (!cold) 185 claimed = ncr5380_intr(ncr_sc); 186 if (!claimed) { 187 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 188 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 189 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 190 if (sc->sc_clrintr) 191 (*sc->sc_clrintr)(ncr_sc); 192 } 193 #ifdef SBC_DEBUG 194 else { 195 printf("%s: spurious intr\n", 196 ncr_sc->sc_dev.dv_xname); 197 SBC_BREAK; 198 } 199 #endif 200 } 201 } 202 } 203 204 #ifdef SBC_DEBUG 205 void 206 decode_5380_intr(struct ncr5380_softc *ncr_sc) 207 { 208 u_int8_t csr = *ncr_sc->sci_csr; 209 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 210 211 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 212 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 213 if (csr & SCI_BUS_IO) 214 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 215 else 216 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 217 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 218 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 219 printf("%s: DMA eop\n", ncr_sc->sc_dev.dv_xname); 220 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 221 ((bus_csr & ~SCI_BUS_RST) == 0)) 222 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 223 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 224 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 225 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 226 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 227 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 228 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 229 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 230 (bus_csr == 0)) 231 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 232 else 233 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 234 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 235 } 236 #endif 237 238 239 /*** 240 * The following code implements polled PDMA. 241 ***/ 242 243 int 244 sbc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 245 { 246 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 247 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 248 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 249 int resid, s; 250 251 if (datalen < ncr_sc->sc_min_dma_len || 252 (sc->sc_options & SBC_PDMA) == 0) 253 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 254 255 s = splbio(); 256 if (sbc_wait_busy(ncr_sc)) { 257 splx(s); 258 return 0; 259 } 260 261 *ncr_sc->sci_mode |= SCI_MODE_DMA; 262 *ncr_sc->sci_irecv = 0; 263 264 #define R4 *((u_int32_t *)data)++ = *long_data 265 #define R1 *((u_int8_t *)data)++ = *byte_data 266 for (resid = datalen; resid >= 128; resid -= 128) { 267 if (sbc_ready(ncr_sc)) 268 goto interrupt; 269 R4; R4; R4; R4; R4; R4; R4; R4; 270 R4; R4; R4; R4; R4; R4; R4; R4; 271 R4; R4; R4; R4; R4; R4; R4; R4; 272 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 273 } 274 while (resid) { 275 if (sbc_ready(ncr_sc)) 276 goto interrupt; 277 R1; 278 resid--; 279 } 280 #undef R4 281 #undef R1 282 283 interrupt: 284 SCI_CLR_INTR(ncr_sc); 285 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 286 *ncr_sc->sci_icmd = 0; 287 splx(s); 288 return (datalen - resid); 289 } 290 291 int 292 sbc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 293 { 294 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 295 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 296 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 297 label_t faultbuf; 298 int resid, s; 299 u_int8_t icmd; 300 301 #if 1 302 /* Work around lame gcc initialization bug */ 303 (void)&data; 304 #endif 305 306 if (datalen < ncr_sc->sc_min_dma_len || 307 (sc->sc_options & SBC_PDMA) == 0) 308 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 309 310 s = splbio(); 311 if (sbc_wait_busy(ncr_sc)) { 312 splx(s); 313 return 0; 314 } 315 316 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 317 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 318 *ncr_sc->sci_mode |= SCI_MODE_DMA; 319 *ncr_sc->sci_dma_send = 0; 320 321 /* 322 * Setup for a possible bus error caused by SCSI controller 323 * switching out of DATA OUT before we're done with the 324 * current transfer. (See comment before sbc_drq_intr().) 325 */ 326 nofault = &faultbuf; 327 328 if (setjmp(nofault)) { 329 printf("buf = 0x%lx, fault = 0x%lx\n", 330 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 331 panic("Unexpected bus error in sbc_pdma_out()"); 332 } 333 334 #define W1 *byte_data = *((u_int8_t *)data)++ 335 #define W4 *long_data = *((u_int32_t *)data)++ 336 for (resid = datalen; resid >= 64; resid -= 64) { 337 if (sbc_ready(ncr_sc)) 338 goto interrupt; 339 W1; 340 if (sbc_ready(ncr_sc)) 341 goto interrupt; 342 W1; 343 if (sbc_ready(ncr_sc)) 344 goto interrupt; 345 W1; 346 if (sbc_ready(ncr_sc)) 347 goto interrupt; 348 W1; 349 if (sbc_ready(ncr_sc)) 350 goto interrupt; 351 W4; W4; W4; W4; 352 W4; W4; W4; W4; 353 W4; W4; W4; W4; 354 W4; W4; W4; 355 } 356 while (resid) { 357 if (sbc_ready(ncr_sc)) 358 goto interrupt; 359 W1; 360 resid--; 361 } 362 #undef W1 363 #undef W4 364 if (sbc_wait_dreq(ncr_sc)) 365 printf("%s: timeout waiting for DREQ.\n", 366 ncr_sc->sc_dev.dv_xname); 367 368 *byte_data = 0; 369 goto done; 370 371 interrupt: 372 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 373 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 374 --resid; 375 } 376 377 done: 378 SCI_CLR_INTR(ncr_sc); 379 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 380 *ncr_sc->sci_icmd = icmd; 381 splx(s); 382 return (datalen - resid); 383 } 384 385 386 /*** 387 * The following code implements interrupt-driven PDMA. 388 ***/ 389 390 /* 391 * This is the meat of the PDMA transfer. 392 * When we get here, we shove data as fast as the mac can take it. 393 * We depend on several things: 394 * * All macs after the Mac Plus that have a 5380 chip should have a general 395 * logic IC that handshakes data for blind transfers. 396 * * If the SCSI controller finishes sending/receiving data before we do, 397 * the same general logic IC will generate a /BERR for us in short order. 398 * * The fault address for said /BERR minus the base address for the 399 * transfer will be the amount of data that was actually written. 400 * 401 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 402 * detect and handle the bus error for early termination of a command. 403 * This is usually caused by a disconnecting target. 404 */ 405 void 406 sbc_drq_intr(void *p) 407 { 408 struct sbc_softc *sc = (struct sbc_softc *)p; 409 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 410 struct sci_req *sr = ncr_sc->sc_current; 411 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 412 label_t faultbuf; 413 volatile u_int32_t *long_drq; 414 u_int32_t *long_data; 415 volatile u_int8_t *drq; 416 u_int8_t *data; 417 int count, dcount, resid; 418 u_int8_t tmp; 419 420 /* Work around lame gcc initialization bug */ 421 (void)&drq; 422 423 /* 424 * If we're not ready to xfer data, or have no more, just return. 425 */ 426 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 427 return; 428 429 #ifdef SBC_DEBUG 430 if (sbc_debug & SBC_DB_INTR) 431 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 432 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 433 #endif 434 435 /* 436 * Setup for a possible bus error caused by SCSI controller 437 * switching out of DATA-IN/OUT before we're done with the 438 * current transfer. 439 */ 440 nofault = &faultbuf; 441 442 if (setjmp(nofault)) { 443 nofault = (label_t *)0; 444 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 445 count = (( (u_long)m68k_fault_addr 446 - (u_long)sc->sc_drq_addr)); 447 448 if ((count < 0) || (count > dh->dh_len)) { 449 printf("%s: complete=0x%x (pending 0x%x)\n", 450 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 451 panic("something is wrong"); 452 } 453 454 dh->dh_addr += count; 455 dh->dh_len -= count; 456 } else 457 count = 0; 458 459 #ifdef SBC_DEBUG 460 if (sbc_debug & SBC_DB_INTR) 461 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 462 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 463 #endif 464 m68k_fault_addr = 0; 465 466 return; 467 } 468 469 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 470 dcount = 0; 471 472 /* 473 * Get the source address aligned. 474 */ 475 resid = 476 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 477 if (count && count < 4) { 478 drq = (volatile u_int8_t *)sc->sc_drq_addr; 479 data = (u_int8_t *)dh->dh_addr; 480 481 #define W1 *drq++ = *data++ 482 while (count) { 483 W1; count--; 484 } 485 #undef W1 486 dh->dh_addr += resid; 487 dh->dh_len -= resid; 488 } 489 490 /* 491 * Start the transfer. 492 */ 493 while (dh->dh_len) { 494 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 495 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 496 long_data = (u_int32_t *)dh->dh_addr; 497 498 #define W4 *long_drq++ = *long_data++ 499 while (count >= 64) { 500 W4; W4; W4; W4; W4; W4; W4; W4; 501 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 502 count -= 64; 503 } 504 while (count >= 4) { 505 W4; count -= 4; 506 } 507 #undef W4 508 data = (u_int8_t *)long_data; 509 drq = (volatile u_int8_t *)long_drq; 510 511 #define W1 *drq++ = *data++ 512 while (count) { 513 W1; count--; 514 } 515 #undef W1 516 dh->dh_len -= dcount; 517 dh->dh_addr += dcount; 518 } 519 dh->dh_flags |= SBC_DH_DONE; 520 521 /* 522 * XXX -- Read a byte from the SBC to trigger a /BERR. 523 * This seems to be necessary for us to notice that 524 * the target has disconnected. Ick. 06 jun 1996 (sr) 525 */ 526 if (dcount >= MAX_DMA_LEN) 527 drq = (volatile u_int8_t *)sc->sc_drq_addr; 528 tmp = *drq; 529 } else { /* Data In */ 530 /* 531 * Get the dest address aligned. 532 */ 533 resid = 534 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 535 if (count && count < 4) { 536 data = (u_int8_t *)dh->dh_addr; 537 drq = (volatile u_int8_t *)sc->sc_drq_addr; 538 539 #define R1 *data++ = *drq++ 540 while (count) { 541 R1; count--; 542 } 543 #undef R1 544 dh->dh_addr += resid; 545 dh->dh_len -= resid; 546 } 547 548 /* 549 * Start the transfer. 550 */ 551 while (dh->dh_len) { 552 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 553 long_data = (u_int32_t *)dh->dh_addr; 554 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 555 556 #define R4 *long_data++ = *long_drq++ 557 while (count >= 64) { 558 R4; R4; R4; R4; R4; R4; R4; R4; 559 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 560 count -= 64; 561 } 562 while (count >= 4) { 563 R4; count -= 4; 564 } 565 #undef R4 566 data = (u_int8_t *)long_data; 567 drq = (volatile u_int8_t *)long_drq; 568 569 #define R1 *data++ = *drq++ 570 while (count) { 571 R1; count--; 572 } 573 #undef R1 574 dh->dh_len -= dcount; 575 dh->dh_addr += dcount; 576 } 577 dh->dh_flags |= SBC_DH_DONE; 578 } 579 580 /* 581 * OK. No bus error occurred above. Clear the nofault flag 582 * so we no longer short-circuit bus errors. 583 */ 584 nofault = (label_t *)0; 585 586 #ifdef SBC_DEBUG 587 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 588 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 589 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 590 *ncr_sc->sci_bus_csr); 591 #endif 592 } 593 594 void 595 sbc_dma_alloc(struct ncr5380_softc *ncr_sc) 596 { 597 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 598 struct sci_req *sr = ncr_sc->sc_current; 599 struct scsipi_xfer *xs = sr->sr_xs; 600 struct sbc_pdma_handle *dh; 601 int i, xlen; 602 603 #ifdef DIAGNOSTIC 604 if (sr->sr_dma_hand != NULL) 605 panic("sbc_dma_alloc: already have PDMA handle"); 606 #endif 607 608 /* Polled transfers shouldn't allocate a PDMA handle. */ 609 if (sr->sr_flags & SR_IMMED) 610 return; 611 612 xlen = ncr_sc->sc_datalen; 613 614 /* Make sure our caller checked sc_min_dma_len. */ 615 if (xlen < MIN_DMA_LEN) 616 panic("sbc_dma_alloc: len=0x%x", xlen); 617 618 /* 619 * Find free PDMA handle. Guaranteed to find one since we 620 * have as many PDMA handles as the driver has processes. 621 * (instances?) 622 */ 623 for (i = 0; i < SCI_OPENINGS; i++) { 624 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 625 goto found; 626 } 627 panic("sbc: no free PDMA handles"); 628 found: 629 dh = &sc->sc_pdma[i]; 630 dh->dh_flags = SBC_DH_BUSY; 631 dh->dh_addr = ncr_sc->sc_dataptr; 632 dh->dh_len = xlen; 633 634 /* Copy the 'write' flag for convenience. */ 635 if (xs->xs_control & XS_CTL_DATA_OUT) 636 dh->dh_flags |= SBC_DH_OUT; 637 638 sr->sr_dma_hand = dh; 639 } 640 641 void 642 sbc_dma_free(struct ncr5380_softc *ncr_sc) 643 { 644 struct sci_req *sr = ncr_sc->sc_current; 645 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 646 647 #ifdef DIAGNOSTIC 648 if (sr->sr_dma_hand == NULL) 649 panic("sbc_dma_free: no DMA handle"); 650 #endif 651 652 if (ncr_sc->sc_state & NCR_DOINGDMA) 653 panic("sbc_dma_free: free while in progress"); 654 655 if (dh->dh_flags & SBC_DH_BUSY) { 656 dh->dh_flags = 0; 657 dh->dh_addr = NULL; 658 dh->dh_len = 0; 659 } 660 sr->sr_dma_hand = NULL; 661 } 662 663 void 664 sbc_dma_poll(struct ncr5380_softc *ncr_sc) 665 { 666 struct sci_req *sr = ncr_sc->sc_current; 667 668 /* 669 * We shouldn't arrive here; if SR_IMMED is set, then 670 * dma_alloc() should have refused to allocate a handle 671 * for the transfer. This forces the polled PDMA code 672 * to handle the request... 673 */ 674 #ifdef SBC_DEBUG 675 if (sbc_debug & SBC_DB_DMA) 676 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 677 #endif 678 sr->sr_flags |= SR_OVERDUE; 679 } 680 681 void 682 sbc_dma_setup(struct ncr5380_softc *ncr_sc) 683 { 684 /* Not needed; we don't have real DMA */ 685 } 686 687 void 688 sbc_dma_start(struct ncr5380_softc *ncr_sc) 689 { 690 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 691 struct sci_req *sr = ncr_sc->sc_current; 692 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 693 694 /* 695 * Match bus phase, clear pending interrupts, set DMA mode, and 696 * assert data bus (for writing only), then start the transfer. 697 */ 698 if (dh->dh_flags & SBC_DH_OUT) { 699 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 700 SCI_CLR_INTR(ncr_sc); 701 if (sc->sc_clrintr) 702 (*sc->sc_clrintr)(ncr_sc); 703 *ncr_sc->sci_mode |= SCI_MODE_DMA; 704 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 705 *ncr_sc->sci_dma_send = 0; 706 } else { 707 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 708 SCI_CLR_INTR(ncr_sc); 709 if (sc->sc_clrintr) 710 (*sc->sc_clrintr)(ncr_sc); 711 *ncr_sc->sci_mode |= SCI_MODE_DMA; 712 *ncr_sc->sci_icmd = 0; 713 *ncr_sc->sci_irecv = 0; 714 } 715 ncr_sc->sc_state |= NCR_DOINGDMA; 716 717 #ifdef SBC_DEBUG 718 if (sbc_debug & SBC_DB_DMA) 719 printf("%s: PDMA started, va=%p, len=0x%x\n", 720 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 721 #endif 722 } 723 724 void 725 sbc_dma_eop(struct ncr5380_softc *ncr_sc) 726 { 727 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 728 } 729 730 void 731 sbc_dma_stop(struct ncr5380_softc *ncr_sc) 732 { 733 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 734 struct sci_req *sr = ncr_sc->sc_current; 735 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 736 int ntrans; 737 738 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 739 #ifdef SBC_DEBUG 740 if (sbc_debug & SBC_DB_DMA) 741 printf("%s: dma_stop: DMA not running\n", 742 ncr_sc->sc_dev.dv_xname); 743 #endif 744 return; 745 } 746 ncr_sc->sc_state &= ~NCR_DOINGDMA; 747 748 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 749 ntrans = ncr_sc->sc_datalen - dh->dh_len; 750 751 #ifdef SBC_DEBUG 752 if (sbc_debug & SBC_DB_DMA) 753 printf("%s: dma_stop: ntrans=0x%x\n", 754 ncr_sc->sc_dev.dv_xname, ntrans); 755 #endif 756 757 if (ntrans > ncr_sc->sc_datalen) 758 panic("sbc_dma_stop: excess transfer"); 759 760 /* Adjust data pointer */ 761 ncr_sc->sc_dataptr += ntrans; 762 ncr_sc->sc_datalen -= ntrans; 763 764 /* Clear any pending interrupts. */ 765 SCI_CLR_INTR(ncr_sc); 766 if (sc->sc_clrintr) 767 (*sc->sc_clrintr)(ncr_sc); 768 } 769 770 /* Put SBIC back into PIO mode. */ 771 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 772 *ncr_sc->sci_icmd = 0; 773 774 #ifdef SBC_DEBUG 775 if (sbc_debug & SBC_DB_REG) 776 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 777 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 778 *ncr_sc->sci_bus_csr); 779 #endif 780 } 781
Indexes created Wed Sep 24 14:09:57 GMT 2025