sbc.c revision 1.5
1 /* $NetBSD: sbc.c,v 1.5 1996/05/05 06:17:13 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott Reynolds 5 * Copyright (c) 1995 David Jones 6 * Copyright (c) 1995 Allen Briggs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the authors may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 4. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by David Jones, Allen 22 * Briggs and Scott Reynolds. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * This file contains only the machine-dependent parts of the mac68k 38 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 39 * The machine-independent parts are in ncr5380sbc.c 40 * 41 * Supported hardware includes: 42 * Macintosh II family 5380-based controller 43 * 44 * Credits, history: 45 * 46 * Scott Reynolds wrote this module, based on work by Allen Briggs 47 * (mac68k), David Jones (sun3), and Leo Weppelman (atari). Allen 48 * supplied some crucial interpretation of the NetBSD 1.1 'ncrscsi' 49 * driver. Allen, Gordon W. Ross, and Jason Thorpe all helped to 50 * refine this code, and were considerable sources of moral support. 51 * 52 * The sbc_options code is based on similar code in Jason's modified 53 * NetBSD/sparc 'si' driver. 54 */ 55 56 #include <sys/types.h> 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/kernel.h> 60 #include <sys/errno.h> 61 #include <sys/device.h> 62 #include <sys/buf.h> 63 #include <sys/proc.h> 64 #include <sys/user.h> 65 66 #include <scsi/scsi_all.h> 67 #include <scsi/scsi_debug.h> 68 #include <scsi/scsiconf.h> 69 70 #include <dev/ic/ncr5380reg.h> 71 #include <dev/ic/ncr5380var.h> 72 73 #include <machine/viareg.h> 74 75 #include "sbcreg.h" 76 77 /* 78 * Transfers smaller than this are done using PIO 79 * (on assumption they're not worth PDMA overhead) 80 */ 81 #define MIN_DMA_LEN 128 82 83 /* 84 * Transfers larger than 8192 bytes need to be split up 85 * due to the size of the PDMA space. 86 */ 87 #define MAX_DMA_LEN 0x2000 88 89 /* 90 * From Guide to the Macintosh Family Hardware, p. 137 91 * These are offsets from SCSIBase (see pmap_bootstrap.c) 92 */ 93 #define SBC_REGISTER_OFFSET 0x10000 94 #define SBC_DMA_DRQ_OFFSET 0x06000 95 #define SBC_DMA_NODRQ_OFFSET 0x12000 96 97 #ifdef SBC_DEBUG 98 # define SBC_DB_INTR 0x01 99 # define SBC_DB_DMA 0x02 100 # define SBC_DB_REG 0x04 101 # define SBC_DB_BREAK 0x08 102 103 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 104 int sbc_link_flags = 0 /* | SDEV_DB2 */; 105 106 # ifndef DDB 107 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 108 # endif 109 # define SBC_BREAK \ 110 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 111 #else 112 # define SBC_BREAK 113 #endif 114 115 /* 116 * This structure is used to keep track of PDMA requests. 117 */ 118 struct sbc_pdma_handle { 119 int dh_flags; /* flags */ 120 #define SBC_DH_BUSY 0x01 /* This handle is in use */ 121 #define SBC_DH_OUT 0x02 /* PDMA data out (write) */ 122 u_char *dh_addr; /* data buffer */ 123 int dh_len; /* length of data buffer */ 124 }; 125 126 /* 127 * The first structure member has to be the ncr5380_softc 128 * so we can just cast to go back and forth between them. 129 */ 130 struct sbc_softc { 131 struct ncr5380_softc ncr_sc; 132 volatile struct sbc_regs *sc_regs; 133 volatile long *sc_drq_addr; 134 volatile u_char *sc_nodrq_addr; 135 volatile u_char *sc_ienable; 136 volatile u_char *sc_iflag; 137 int sc_options; /* options for this instance. */ 138 struct sbc_pdma_handle sc_pdma[SCI_OPENINGS]; 139 }; 140 141 /* 142 * Options. By default, SCSI interrupts and reselect are disabled. 143 * You may enable either of these features with the `flags' directive 144 * in your kernel's configuration file. 145 * 146 * Alternatively, you can patch your kernel with DDB or some other 147 * mechanism. The sc_options member of the softc is OR'd with 148 * the value in sbc_options. 149 */ 150 #define SBC_INTR 0x01 /* Allow SCSI IRQ/DRQ interrupts */ 151 #define SBC_RESELECT 0x02 /* Allow disconnect/reselect */ 152 #define SBC_OPTIONS_MASK (SBC_INTR|SBC_RESELECT) 153 #define SBC_OPTIONS_BITS "\10\2RESELECT\1INTR" 154 int sbc_options = 0; 155 156 static int sbc_print __P((void *, char *)); 157 static int sbc_match __P((struct device *, void *, void *)); 158 static void sbc_attach __P((struct device *, struct device *, void *)); 159 static void sbc_minphys __P((struct buf *bp)); 160 161 static int sbc_wait_busy __P((struct ncr5380_softc *)); 162 static int sbc_ready __P((struct ncr5380_softc *)); 163 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 164 static int sbc_pdma_in __P((struct ncr5380_softc *, int, int, u_char *)); 165 static int sbc_pdma_out __P((struct ncr5380_softc *, int, int, u_char *)); 166 #ifdef SBC_DEBUG 167 static void decode_5380_intr __P((struct ncr5380_softc *)); 168 #endif 169 170 void sbc_intr_enable __P((struct ncr5380_softc *)); 171 void sbc_intr_disable __P((struct ncr5380_softc *)); 172 void sbc_irq_intr __P((void *)); 173 void sbc_drq_intr __P((void *)); 174 void sbc_dma_alloc __P((struct ncr5380_softc *)); 175 void sbc_dma_free __P((struct ncr5380_softc *)); 176 void sbc_dma_poll __P((struct ncr5380_softc *)); 177 void sbc_dma_setup __P((struct ncr5380_softc *)); 178 void sbc_dma_start __P((struct ncr5380_softc *)); 179 void sbc_dma_eop __P((struct ncr5380_softc *)); 180 void sbc_dma_stop __P((struct ncr5380_softc *)); 181 182 static struct scsi_adapter sbc_ops = { 183 ncr5380_scsi_cmd, /* scsi_cmd() */ 184 sbc_minphys, /* scsi_minphys() */ 185 NULL, /* open_target_lu() */ 186 NULL, /* close_target_lu() */ 187 }; 188 189 /* This is copied from julian's bt driver */ 190 /* "so we have a default dev struct for our link struct." */ 191 static struct scsi_device sbc_dev = { 192 NULL, /* Use default error handler. */ 193 NULL, /* Use default start handler. */ 194 NULL, /* Use default async handler. */ 195 NULL, /* Use default "done" routine. */ 196 }; 197 198 struct cfattach sbc_ca = { 199 sizeof(struct sbc_softc), sbc_match, sbc_attach 200 }; 201 202 struct cfdriver sbc_cd = { 203 NULL, "sbc", DV_DULL 204 }; 205 206 207 static int 208 sbc_print(aux, name) 209 void *aux; 210 char *name; 211 { 212 if (name != NULL) 213 printf("%s: scsibus ", name); 214 return UNCONF; 215 } 216 217 static int 218 sbc_match(parent, match, args) 219 struct device *parent; 220 void *match, *args; 221 { 222 struct device *self = match; /* XXX mainbus is "indirect" */ 223 struct confargs *ca = args; 224 225 if (!mac68k_machine.scsi80) 226 return 0; 227 if (self->dv_cfdata->cf_unit != 0) 228 return 0; 229 return 1; 230 } 231 232 static void 233 sbc_attach(parent, self, args) 234 struct device *parent, *self; 235 void *args; 236 { 237 struct sbc_softc *sc = (struct sbc_softc *) self; 238 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) sc; 239 extern vm_offset_t SCSIBase; 240 241 /* Pull in the options flags. */ 242 sc->sc_options = 243 ((ncr_sc->sc_dev.dv_cfdata->cf_flags | sbc_options) & SBC_OPTIONS_MASK); 244 245 /* 246 * Set up base address of 5380 247 */ 248 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REGISTER_OFFSET); 249 250 /* 251 * Fill in the prototype scsi_link. 252 */ 253 ncr_sc->sc_link.adapter_softc = sc; 254 ncr_sc->sc_link.adapter_target = 7; 255 ncr_sc->sc_link.adapter = &sbc_ops; 256 ncr_sc->sc_link.device = &sbc_dev; 257 258 /* 259 * Initialize fields used by the MI code 260 */ 261 ncr_sc->sci_r0 = &sc->sc_regs->sci_pr0.sci_reg; 262 ncr_sc->sci_r1 = &sc->sc_regs->sci_pr1.sci_reg; 263 ncr_sc->sci_r2 = &sc->sc_regs->sci_pr2.sci_reg; 264 ncr_sc->sci_r3 = &sc->sc_regs->sci_pr3.sci_reg; 265 ncr_sc->sci_r4 = &sc->sc_regs->sci_pr4.sci_reg; 266 ncr_sc->sci_r5 = &sc->sc_regs->sci_pr5.sci_reg; 267 ncr_sc->sci_r6 = &sc->sc_regs->sci_pr6.sci_reg; 268 ncr_sc->sci_r7 = &sc->sc_regs->sci_pr7.sci_reg; 269 270 /* 271 * MD function pointers used by the MI code. 272 */ 273 ncr_sc->sc_pio_out = sbc_pdma_out; 274 ncr_sc->sc_pio_in = sbc_pdma_in; 275 ncr_sc->sc_dma_alloc = NULL; 276 ncr_sc->sc_dma_free = NULL; 277 ncr_sc->sc_dma_poll = NULL; 278 ncr_sc->sc_intr_on = NULL; 279 ncr_sc->sc_intr_off = NULL; 280 ncr_sc->sc_dma_setup = NULL; 281 ncr_sc->sc_dma_start = NULL; 282 ncr_sc->sc_dma_eop = NULL; 283 ncr_sc->sc_dma_stop = NULL; 284 ncr_sc->sc_flags = 0; 285 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 286 287 /* 288 * MD function pointers used by the MI code. 289 */ 290 if ((sc->sc_options & SBC_INTR) == 0) { 291 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 292 } else { 293 if (sc->sc_options & SBC_RESELECT) 294 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 295 ncr_sc->sc_dma_alloc = sbc_dma_alloc; 296 ncr_sc->sc_dma_free = sbc_dma_free; 297 ncr_sc->sc_dma_poll = sbc_dma_poll; 298 ncr_sc->sc_dma_setup = sbc_dma_setup; 299 ncr_sc->sc_dma_start = sbc_dma_start; 300 ncr_sc->sc_dma_eop = sbc_dma_eop; 301 ncr_sc->sc_dma_stop = sbc_dma_stop; 302 mac68k_register_scsi_drq(sbc_drq_intr, ncr_sc); 303 mac68k_register_scsi_irq(sbc_irq_intr, ncr_sc); 304 } 305 306 /* 307 * Initialize fields used only here in the MD code. 308 */ 309 sc->sc_drq_addr = (long *) (SCSIBase + SBC_DMA_DRQ_OFFSET); 310 sc->sc_nodrq_addr = (u_char *) (SCSIBase + SBC_DMA_NODRQ_OFFSET); 311 if (VIA2 == VIA2OFF) { 312 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + vIER; 313 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + vIFR; 314 } else { 315 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + rIER; 316 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + rIFR; 317 } 318 319 if (sc->sc_options) 320 printf(": options=%b", sc->sc_options, SBC_OPTIONS_BITS); 321 printf("\n"); 322 323 /* Now enable SCSI interrupts through VIA2, if appropriate */ 324 if (sc->sc_options & SBC_INTR) 325 sbc_intr_enable(ncr_sc); 326 327 #ifdef SBC_DEBUG 328 if (sbc_debug) 329 printf("%s: softc=%p regs=%p\n", ncr_sc->sc_dev.dv_xname, 330 sc, sc->sc_regs); 331 ncr_sc->sc_link.flags |= sbc_link_flags; 332 #endif 333 334 /* 335 * Initialize the SCSI controller itself. 336 */ 337 ncr5380_init(ncr_sc); 338 ncr5380_reset_scsibus(ncr_sc); 339 config_found(self, &(ncr_sc->sc_link), sbc_print); 340 } 341 342 343 static void 344 sbc_minphys(struct buf *bp) 345 { 346 if (bp->b_bcount > MAX_DMA_LEN) 347 bp->b_bcount = MAX_DMA_LEN; 348 return (minphys(bp)); 349 } 350 351 352 /*** 353 * General support for Mac-specific SCSI logic. 354 ***/ 355 356 /* These are used in the following inline functions. */ 357 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 358 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 359 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 360 361 /* Return zero on success. */ 362 static __inline__ int 363 sbc_wait_busy(sc) 364 struct ncr5380_softc *sc; 365 { 366 register int timo = sbc_wait_busy_timo; 367 for (;;) { 368 if (SCI_BUSY(sc)) { 369 timo = 0; /* return 0 */ 370 break; 371 } 372 if (--timo < 0) 373 break; /* return -1 */ 374 delay(2); 375 } 376 return (timo); 377 } 378 379 static __inline__ int 380 sbc_ready(sc) 381 struct ncr5380_softc *sc; 382 { 383 register int timo = sbc_ready_timo; 384 385 for (;;) { 386 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 387 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 388 timo = 0; 389 break; 390 } 391 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 392 || (SCI_BUSY(sc) == 0)) { 393 timo = -1; 394 break; 395 } 396 if (--timo < 0) 397 break; /* return -1 */ 398 delay(2); 399 } 400 return (timo); 401 } 402 403 static __inline__ int 404 sbc_wait_dreq(sc) 405 struct ncr5380_softc *sc; 406 { 407 register int timo = sbc_wait_dreq_timo; 408 409 for (;;) { 410 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 411 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 412 timo = 0; 413 break; 414 } 415 if (--timo < 0) 416 break; /* return -1 */ 417 delay(2); 418 } 419 return (timo); 420 } 421 422 423 /*** 424 * Macintosh SCSI interrupt support routines. 425 ***/ 426 427 void 428 sbc_intr_enable(ncr_sc) 429 struct ncr5380_softc *ncr_sc; 430 { 431 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 432 int s; 433 434 s = splhigh(); 435 *sc->sc_iflag = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 436 *sc->sc_ienable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 437 splx(s); 438 } 439 440 void 441 sbc_intr_disable(ncr_sc) 442 struct ncr5380_softc *ncr_sc; 443 { 444 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 445 int s; 446 447 s = splhigh(); 448 *sc->sc_ienable = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 449 splx(s); 450 } 451 452 void 453 sbc_irq_intr(p) 454 void *p; 455 { 456 static int handling_sbc_intr = 0; 457 register struct ncr5380_softc *ncr_sc = p; 458 register int claimed = 0; 459 460 /* How we ever arrive here without IRQ set is a mystery... */ 461 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 462 /* 463 * For some reason, the hardware sometimes generates a 464 * spurious selection interrupt. I don't know why this 465 * happens, but the following hack works around it. --sar 466 */ 467 if (handling_sbc_intr) 468 return; 469 handling_sbc_intr++; 470 471 #ifdef SBC_DEBUG 472 if (sbc_debug & SBC_DB_INTR) 473 decode_5380_intr(ncr_sc); 474 #endif 475 claimed = ncr5380_intr(ncr_sc); 476 if (!claimed) { 477 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 478 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 479 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 480 #ifdef SBC_DEBUG 481 else { 482 printf("%s: spurious intr\n", 483 ncr_sc->sc_dev.dv_xname); 484 SBC_BREAK; 485 } 486 #endif 487 } 488 489 /* We can handle another interrupt from the SBC now. */ 490 handling_sbc_intr = 0; 491 } 492 } 493 494 #ifdef SBC_DEBUG 495 void 496 decode_5380_intr(ncr_sc) 497 struct ncr5380_softc *ncr_sc; 498 { 499 register u_char csr = *ncr_sc->sci_csr; 500 register u_char bus_csr = *ncr_sc->sci_bus_csr; 501 502 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 503 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 504 if (csr & SCI_BUS_IO) 505 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 506 else 507 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 508 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 509 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 510 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 511 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 512 ((bus_csr & ~SCI_BUS_RST) == 0)) 513 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 514 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 515 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 516 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 517 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 518 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 519 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 520 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 521 (bus_csr == 0)) 522 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 523 else 524 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 525 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 526 } 527 #endif 528 529 /*** 530 * The following code implements polled PDMA. 531 ***/ 532 533 static int 534 sbc_pdma_out(ncr_sc, phase, count, data) 535 struct ncr5380_softc *ncr_sc; 536 int phase; 537 int count; 538 u_char *data; 539 { 540 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 541 register volatile long *long_data = sc->sc_drq_addr; 542 register volatile u_char *byte_data = sc->sc_nodrq_addr; 543 register int len = count; 544 545 if (count < ncr_sc->sc_min_dma_len) 546 return ncr5380_pio_out(ncr_sc, phase, count, data); 547 548 if (sbc_wait_busy(ncr_sc) == 0) { 549 *ncr_sc->sci_mode &= ~SCI_MODE_MONBSY; /* XXX */ 550 *ncr_sc->sci_mode |= SCI_MODE_DMA; 551 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 552 *ncr_sc->sci_dma_send = 0; 553 554 #define W1 *byte_data = *data++ 555 #define W4 *long_data = *((long*)data)++ 556 while (len >= 64) { 557 if (sbc_ready(ncr_sc)) 558 goto timeout; 559 W1; 560 if (sbc_ready(ncr_sc)) 561 goto timeout; 562 W1; 563 if (sbc_ready(ncr_sc)) 564 goto timeout; 565 W1; 566 if (sbc_ready(ncr_sc)) 567 goto timeout; 568 W1; 569 if (sbc_ready(ncr_sc)) 570 goto timeout; 571 W4; W4; W4; W4; 572 W4; W4; W4; W4; 573 W4; W4; W4; W4; 574 W4; W4; W4; 575 len -= 64; 576 } 577 while (len) { 578 if (sbc_ready(ncr_sc)) 579 goto timeout; 580 W1; 581 len--; 582 } 583 #undef W1 584 #undef W4 585 if (sbc_wait_dreq(ncr_sc)) 586 printf("%s: timeout waiting for DREQ.\n", 587 ncr_sc->sc_dev.dv_xname); 588 589 *byte_data = 0; 590 591 SCI_CLR_INTR(ncr_sc); 592 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 593 *ncr_sc->sci_icmd = 0; 594 } 595 return count - len; 596 597 timeout: 598 printf("%s: pdma_out: timeout len=%d count=%d\n", 599 ncr_sc->sc_dev.dv_xname, len, count); 600 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 601 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 602 --len; 603 } 604 605 SCI_CLR_INTR(ncr_sc); 606 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 607 *ncr_sc->sci_icmd = 0; 608 return count - len; 609 } 610 611 static int 612 sbc_pdma_in(ncr_sc, phase, count, data) 613 struct ncr5380_softc *ncr_sc; 614 int phase; 615 int count; 616 u_char *data; 617 { 618 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 619 register volatile long *long_data = sc->sc_drq_addr; 620 register volatile u_char *byte_data = sc->sc_nodrq_addr; 621 register int len = count; 622 623 if (count < ncr_sc->sc_min_dma_len) 624 return ncr5380_pio_in(ncr_sc, phase, count, data); 625 626 if (sbc_wait_busy(ncr_sc) == 0) { 627 *ncr_sc->sci_mode &= ~SCI_MODE_MONBSY; /* XXX */ 628 *ncr_sc->sci_mode |= SCI_MODE_DMA; 629 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 630 *ncr_sc->sci_irecv = 0; 631 632 #define R4 *((long *)data)++ = *long_data 633 #define R1 *data++ = *byte_data 634 while (len >= 1024) { 635 if (sbc_ready(ncr_sc)) 636 goto timeout; 637 R4; R4; R4; R4; R4; R4; R4; R4; 638 R4; R4; R4; R4; R4; R4; R4; R4; 639 R4; R4; R4; R4; R4; R4; R4; R4; 640 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 641 if (sbc_ready(ncr_sc)) 642 goto timeout; 643 R4; R4; R4; R4; R4; R4; R4; R4; 644 R4; R4; R4; R4; R4; R4; R4; R4; 645 R4; R4; R4; R4; R4; R4; R4; R4; 646 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 647 if (sbc_ready(ncr_sc)) 648 goto timeout; 649 R4; R4; R4; R4; R4; R4; R4; R4; 650 R4; R4; R4; R4; R4; R4; R4; R4; 651 R4; R4; R4; R4; R4; R4; R4; R4; 652 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 653 if (sbc_ready(ncr_sc)) 654 goto timeout; 655 R4; R4; R4; R4; R4; R4; R4; R4; 656 R4; R4; R4; R4; R4; R4; R4; R4; 657 R4; R4; R4; R4; R4; R4; R4; R4; 658 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 659 if (sbc_ready(ncr_sc)) 660 goto timeout; 661 R4; R4; R4; R4; R4; R4; R4; R4; 662 R4; R4; R4; R4; R4; R4; R4; R4; 663 R4; R4; R4; R4; R4; R4; R4; R4; 664 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 665 if (sbc_ready(ncr_sc)) 666 goto timeout; 667 R4; R4; R4; R4; R4; R4; R4; R4; 668 R4; R4; R4; R4; R4; R4; R4; R4; 669 R4; R4; R4; R4; R4; R4; R4; R4; 670 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 671 if (sbc_ready(ncr_sc)) 672 goto timeout; 673 R4; R4; R4; R4; R4; R4; R4; R4; 674 R4; R4; R4; R4; R4; R4; R4; R4; 675 R4; R4; R4; R4; R4; R4; R4; R4; 676 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 677 if (sbc_ready(ncr_sc)) 678 goto timeout; 679 R4; R4; R4; R4; R4; R4; R4; R4; 680 R4; R4; R4; R4; R4; R4; R4; R4; 681 R4; R4; R4; R4; R4; R4; R4; R4; 682 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 683 len -= 1024; 684 } 685 while (len >= 128) { 686 if (sbc_ready(ncr_sc)) 687 goto timeout; 688 R4; R4; R4; R4; R4; R4; R4; R4; 689 R4; R4; R4; R4; R4; R4; R4; R4; 690 R4; R4; R4; R4; R4; R4; R4; R4; 691 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 692 len -= 128; 693 } 694 while (len) { 695 if (sbc_ready(ncr_sc)) 696 goto timeout; 697 R1; 698 len--; 699 } 700 #undef R4 701 #undef R1 702 SCI_CLR_INTR(ncr_sc); 703 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 704 *ncr_sc->sci_icmd = 0; 705 } 706 return count - len; 707 708 timeout: 709 printf("%s: pdma_in: timeout len=%d count=%d\n", 710 ncr_sc->sc_dev.dv_xname, len, count); 711 712 SCI_CLR_INTR(ncr_sc); 713 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 714 *ncr_sc->sci_icmd = 0; 715 return count - len; 716 } 717 718 719 /*** 720 * The following code implements interrupt-driven PDMA. 721 ***/ 722 723 /* 724 * This is the meat of the PDMA transfer. 725 * When we get here, we shove data as fast as the mac can take it. 726 * We depend on several things: 727 * * All macs after the Mac Plus that have a 5380 chip should have a general 728 * logic IC that handshakes data for blind transfers. 729 * * If the SCSI controller finishes sending/receiving data before we do, 730 * the same general logic IC will generate a /BERR for us in short order. 731 * * The fault address for said /BERR minus the base address for the 732 * transfer will be the amount of data that was actually written. 733 * 734 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 735 * detect and handle the bus error for early termination of a command. 736 * This is usually caused by a disconnecting target. 737 */ 738 void 739 sbc_drq_intr(p) 740 void *p; 741 { 742 extern int *nofault, mac68k_buserr_addr; 743 register struct sbc_softc *sc = (struct sbc_softc *) p; 744 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 745 register struct sci_req *sr = ncr_sc->sc_current; 746 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 747 label_t faultbuf; 748 volatile u_int32_t *long_drq; 749 u_int32_t *long_data; 750 volatile u_int8_t *drq; 751 u_int8_t *data; 752 register int count; 753 int dcount, resid; 754 755 /* 756 * If we're not ready to xfer data, or have no more, just return. 757 */ 758 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 759 return; 760 761 #ifdef SBC_DEBUG 762 if (sbc_debug & SBC_DB_INTR) 763 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 764 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 765 #endif 766 767 /* 768 * Setup for a possible bus error caused by SCSI controller 769 * switching out of DATA-IN/OUT before we're done with the 770 * current transfer. 771 */ 772 nofault = (int *) &faultbuf; 773 774 if (setjmp((label_t *) nofault)) { 775 nofault = (int *) 0; 776 count = ( (u_long) mac68k_buserr_addr 777 - (u_long) sc->sc_drq_addr); 778 779 if ((count < 0) || (count > dh->dh_len)) { 780 printf("%s: complete=0x%x (pending 0x%x)\n", 781 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 782 panic("something is wrong"); 783 } 784 #ifdef SBC_DEBUG 785 if (sbc_debug & SBC_DB_INTR) 786 printf("%s: drq /berr, pending=0x%x, complete=0x%x\n", 787 ncr_sc->sc_dev.dv_xname, dh->dh_len, count); 788 #endif 789 790 dh->dh_addr += count; 791 dh->dh_len -= count; 792 mac68k_buserr_addr = 0; 793 794 return; 795 } 796 797 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 798 /* 799 * Get the source address aligned. 800 */ 801 resid = count = min(dh->dh_len, 802 4 - (((int) dh->dh_addr) & 0x3)); 803 if (count && count < 4) { 804 data = (u_int8_t *) dh->dh_addr; 805 drq = (u_int8_t *) sc->sc_drq_addr; 806 #define W1 *drq++ = *data++ 807 while (count) { 808 W1; count--; 809 } 810 #undef W1 811 dh->dh_addr += resid; 812 dh->dh_len -= resid; 813 } 814 815 /* 816 * Get ready to start the transfer. 817 */ 818 while (dh->dh_len) { 819 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 820 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 821 long_data = (u_int32_t *) dh->dh_addr; 822 823 #define W4 *long_drq++ = *long_data++ 824 while (count >= 64) { 825 W4; W4; W4; W4; W4; W4; W4; W4; 826 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 827 count -= 64; 828 } 829 while (count >= 4) { 830 W4; count -= 4; 831 } 832 #undef W4 833 data = (u_int8_t *) long_data; 834 drq = (u_int8_t *) long_drq; 835 #define W1 *drq++ = *data++ 836 while (count) { 837 W1; count--; 838 } 839 #undef W1 840 dh->dh_len -= dcount; 841 dh->dh_addr += dcount; 842 } 843 } else { /* Data In */ 844 /* 845 * Get the dest address aligned. 846 */ 847 resid = count = min(dh->dh_len, 848 4 - (((int) dh->dh_addr) & 0x3)); 849 if (count && count < 4) { 850 data = (u_int8_t *) dh->dh_addr; 851 drq = (u_int8_t *) sc->sc_drq_addr; 852 #define R1 *data++ = *drq++ 853 while (count) { 854 R1; count--; 855 } 856 #undef R1 857 dh->dh_addr += resid; 858 dh->dh_len -= resid; 859 } 860 861 /* 862 * Get ready to start the transfer. 863 */ 864 while (dh->dh_len) { 865 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 866 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 867 long_data = (u_int32_t *) dh->dh_addr; 868 869 #define R4 *long_data++ = *long_drq++ 870 while (count >= 512) { 871 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0) { 872 nofault = (int *) 0; 873 874 dh->dh_addr += (dcount - count); 875 dh->dh_len -= (dcount - count); 876 return; 877 } 878 R4; R4; R4; R4; R4; R4; R4; R4; 879 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 880 R4; R4; R4; R4; R4; R4; R4; R4; 881 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 882 R4; R4; R4; R4; R4; R4; R4; R4; 883 R4; R4; R4; R4; R4; R4; R4; R4; 884 R4; R4; R4; R4; R4; R4; R4; R4; 885 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 886 R4; R4; R4; R4; R4; R4; R4; R4; 887 R4; R4; R4; R4; R4; R4; R4; R4; 888 R4; R4; R4; R4; R4; R4; R4; R4; 889 R4; R4; R4; R4; R4; R4; R4; R4; 890 R4; R4; R4; R4; R4; R4; R4; R4; 891 R4; R4; R4; R4; R4; R4; R4; R4; 892 R4; R4; R4; R4; R4; R4; R4; R4; 893 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 894 count -= 512; 895 } 896 while (count >= 4) { 897 R4; count -= 4; 898 } 899 #undef R4 900 data = (u_int8_t *) long_data; 901 drq = (u_int8_t *) long_drq; 902 #define R1 *data++ = *drq++ 903 while (count) { 904 R1; count--; 905 } 906 #undef R1 907 dh->dh_len -= dcount; 908 dh->dh_addr += dcount; 909 } 910 } 911 912 /* 913 * OK. No bus error occurred above. Clear the nofault flag 914 * so we no longer short-circuit bus errors. 915 */ 916 nofault = (int *) 0; 917 } 918 919 void 920 sbc_dma_alloc(ncr_sc) 921 struct ncr5380_softc *ncr_sc; 922 { 923 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 924 struct sci_req *sr = ncr_sc->sc_current; 925 struct scsi_xfer *xs = sr->sr_xs; 926 struct sbc_pdma_handle *dh; 927 int i, xlen; 928 929 #ifdef DIAGNOSTIC 930 if (sr->sr_dma_hand != NULL) 931 panic("sbc_dma_alloc: already have PDMA handle"); 932 #endif 933 934 /* Polled transfers shouldn't allocate a PDMA handle. */ 935 if (sr->sr_flags & SR_IMMED) 936 return; 937 938 /* XXX - we don't trust PDMA writes yet! */ 939 if (xs->flags & SCSI_DATA_OUT) 940 return; 941 942 xlen = ncr_sc->sc_datalen; 943 944 /* Make sure our caller checked sc_min_dma_len. */ 945 if (xlen < MIN_DMA_LEN) 946 panic("sbc_dma_alloc: len=0x%x\n", xlen); 947 948 /* 949 * Find free PDMA handle. Guaranteed to find one since we 950 * have as many PDMA handles as the driver has processes. 951 * (instances?) 952 */ 953 for (i = 0; i < SCI_OPENINGS; i++) { 954 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 955 goto found; 956 } 957 panic("sbc: no free PDMA handles"); 958 found: 959 dh = &sc->sc_pdma[i]; 960 dh->dh_flags = SBC_DH_BUSY; 961 dh->dh_addr = ncr_sc->sc_dataptr; 962 dh->dh_len = xlen; 963 964 /* Copy the 'write' flag for convenience. */ 965 if (xs->flags & SCSI_DATA_OUT) 966 dh->dh_flags |= SBC_DH_OUT; 967 968 sr->sr_dma_hand = dh; 969 } 970 971 void 972 sbc_dma_free(ncr_sc) 973 struct ncr5380_softc *ncr_sc; 974 { 975 struct sci_req *sr = ncr_sc->sc_current; 976 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 977 978 #ifdef DIAGNOSTIC 979 if (sr->sr_dma_hand == NULL) 980 panic("sbc_dma_free: no DMA handle"); 981 #endif 982 983 if (ncr_sc->sc_state & NCR_DOINGDMA) 984 panic("sbc_dma_free: free while in progress"); 985 986 if (dh->dh_flags & SBC_DH_BUSY) { 987 dh->dh_flags = 0; 988 dh->dh_addr = NULL; 989 dh->dh_len = 0; 990 } 991 sr->sr_dma_hand = NULL; 992 } 993 994 void 995 sbc_dma_poll(ncr_sc) 996 struct ncr5380_softc *ncr_sc; 997 { 998 struct sci_req *sr = ncr_sc->sc_current; 999 1000 /* 1001 * We shouldn't arrive here; if SR_IMMED is set, then 1002 * dma_alloc() should have refused to allocate a handle 1003 * for the transfer. This forces the polled PDMA code 1004 * to handle the request... 1005 */ 1006 #ifdef SBC_DEBUG 1007 if (sbc_debug & SBC_DB_DMA) 1008 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 1009 #endif 1010 sr->sr_flags |= SR_OVERDUE; 1011 } 1012 1013 void 1014 sbc_dma_setup(ncr_sc) 1015 struct ncr5380_softc *ncr_sc; 1016 { 1017 /* Not needed; we don't have real DMA */ 1018 } 1019 1020 void 1021 sbc_dma_start(ncr_sc) 1022 struct ncr5380_softc *ncr_sc; 1023 { 1024 struct sci_req *sr = ncr_sc->sc_current; 1025 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1026 1027 /* 1028 * Match bus phase, set DMA mode, and assert data bus (for 1029 * writing only), then start the transfer. 1030 */ 1031 if (dh->dh_flags & SBC_DH_OUT) { 1032 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 1033 SCI_CLR_INTR(ncr_sc); 1034 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1035 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 1036 *ncr_sc->sci_dma_send = 0; 1037 } else { 1038 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 1039 SCI_CLR_INTR(ncr_sc); 1040 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1041 *ncr_sc->sci_icmd = 0; 1042 *ncr_sc->sci_irecv = 0; 1043 } 1044 ncr_sc->sc_state |= NCR_DOINGDMA; 1045 1046 #ifdef SBC_DEBUG 1047 if (sbc_debug & SBC_DB_DMA) 1048 printf("%s: PDMA started, va=%p, len=0x%x\n", 1049 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 1050 #endif 1051 } 1052 1053 void 1054 sbc_dma_eop(ncr_sc) 1055 struct ncr5380_softc *ncr_sc; 1056 { 1057 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 1058 } 1059 1060 void 1061 sbc_dma_stop(ncr_sc) 1062 struct ncr5380_softc *ncr_sc; 1063 { 1064 struct sci_req *sr = ncr_sc->sc_current; 1065 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1066 register int ntrans; 1067 1068 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 1069 #ifdef SBC_DEBUG 1070 if (sbc_debug & SBC_DB_DMA) 1071 printf("%s: dma_stop: DMA not running\n", 1072 ncr_sc->sc_dev.dv_xname); 1073 #endif 1074 return; 1075 } 1076 ncr_sc->sc_state &= ~NCR_DOINGDMA; 1077 1078 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 1079 ntrans = ncr_sc->sc_datalen - dh->dh_len; 1080 1081 #ifdef SBC_DEBUG 1082 if (sbc_debug & SBC_DB_DMA) 1083 printf("%s: dma_stop: ntrans=0x%x\n", 1084 ncr_sc->sc_dev.dv_xname, ntrans); 1085 #endif 1086 1087 if (ntrans > ncr_sc->sc_datalen) 1088 panic("sbc_dma_stop: excess transfer\n"); 1089 1090 /* Adjust data pointer */ 1091 ncr_sc->sc_dataptr += ntrans; 1092 ncr_sc->sc_datalen -= ntrans; 1093 1094 /* Clear any pending interrupts. */ 1095 SCI_CLR_INTR(ncr_sc); 1096 } 1097 1098 /* Put SBIC back into PIO mode. */ 1099 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 1100 *ncr_sc->sci_icmd = 0; 1101 1102 #ifdef SBC_DEBUG 1103 if (sbc_debug & SBC_DB_REG) 1104 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 1105 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 1106 *ncr_sc->sci_bus_csr); 1107 #endif 1108 } 1109
Indexes created Thu Oct 02 14:10:14 GMT 2025