sbc.c revision 1.53
1 /* $NetBSD: sbc.c,v 1.53 2008/04/04 16:00:57 tsutsui Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.53 2008/04/04 16:00:57 tsutsui Exp $"); 49 50 #include "opt_ddb.h" 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/buf.h> 59 #include <sys/proc.h> 60 #include <sys/user.h> 61 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsipi_all.h> 64 #include <dev/scsipi/scsipi_debug.h> 65 #include <dev/scsipi/scsiconf.h> 66 67 #include <dev/ic/ncr5380reg.h> 68 #include <dev/ic/ncr5380var.h> 69 70 #include <machine/cpu.h> 71 #include <machine/viareg.h> 72 73 #include <mac68k/dev/sbcreg.h> 74 #include <mac68k/dev/sbcvar.h> 75 76 /* SBC_DEBUG -- relies on DDB */ 77 #ifdef SBC_DEBUG 78 # define SBC_DB_INTR 0x01 79 # define SBC_DB_DMA 0x02 80 # define SBC_DB_REG 0x04 81 # define SBC_DB_BREAK 0x08 82 # ifndef DDB 83 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 84 # endif 85 # define SBC_BREAK \ 86 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 87 #else 88 # define SBC_BREAK 89 #endif 90 91 92 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 93 int sbc_link_flags = 0 /* | SDEV_DB2 */; 94 int sbc_options = 0 /* | SBC_PDMA */; 95 96 extern label_t *nofault; 97 extern void * m68k_fault_addr; 98 99 static int sbc_wait_busy(struct ncr5380_softc *); 100 static int sbc_ready(struct ncr5380_softc *); 101 static int sbc_wait_dreq(struct ncr5380_softc *); 102 103 104 /*** 105 * General support for Mac-specific SCSI logic. 106 ***/ 107 108 /* These are used in the following inline functions. */ 109 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 110 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 111 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 112 113 /* Return zero on success. */ 114 static inline int 115 sbc_wait_busy(struct ncr5380_softc *sc) 116 { 117 int timo = sbc_wait_busy_timo; 118 for (;;) { 119 if (SCI_BUSY(sc)) { 120 timo = 0; /* return 0 */ 121 break; 122 } 123 if (--timo < 0) 124 break; /* return -1 */ 125 delay(2); 126 } 127 return (timo); 128 } 129 130 static inline int 131 sbc_ready(struct ncr5380_softc *sc) 132 { 133 int timo = sbc_ready_timo; 134 135 for (;;) { 136 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 137 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 138 timo = 0; 139 break; 140 } 141 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 142 || (SCI_BUSY(sc) == 0)) { 143 timo = -1; 144 break; 145 } 146 if (--timo < 0) 147 break; /* return -1 */ 148 delay(2); 149 } 150 return (timo); 151 } 152 153 static inline int 154 sbc_wait_dreq(struct ncr5380_softc *sc) 155 { 156 int timo = sbc_wait_dreq_timo; 157 158 for (;;) { 159 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 160 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 161 timo = 0; 162 break; 163 } 164 if (--timo < 0) 165 break; /* return -1 */ 166 delay(2); 167 } 168 return (timo); 169 } 170 171 void 172 sbc_irq_intr(void *p) 173 { 174 struct ncr5380_softc *ncr_sc = p; 175 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 176 int claimed = 0; 177 178 /* How we ever arrive here without IRQ set is a mystery... */ 179 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 180 #ifdef SBC_DEBUG 181 if (sbc_debug & SBC_DB_INTR) 182 decode_5380_intr(ncr_sc); 183 #endif 184 if (!cold) 185 claimed = ncr5380_intr(ncr_sc); 186 if (!claimed) { 187 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 188 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 189 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 190 if (sc->sc_clrintr) 191 (*sc->sc_clrintr)(ncr_sc); 192 } 193 #ifdef SBC_DEBUG 194 else { 195 printf("%s: spurious intr\n", 196 device_xname(ncr_sc->sc_dev)); 197 SBC_BREAK; 198 } 199 #endif 200 } 201 } 202 } 203 204 #ifdef SBC_DEBUG 205 void 206 decode_5380_intr(struct ncr5380_softc *ncr_sc) 207 { 208 u_int8_t csr = *ncr_sc->sci_csr; 209 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 210 211 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 212 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 213 if (csr & SCI_BUS_IO) 214 printf("%s: reselect\n", device_xname(ncr_sc->sc_dev)); 215 else 216 printf("%s: select\n", device_xname(ncr_sc->sc_dev)); 217 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 218 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 219 printf("%s: DMA eop\n", device_xname(ncr_sc->sc_dev)); 220 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 221 ((bus_csr & ~SCI_BUS_RST) == 0)) 222 printf("%s: bus reset\n", device_xname(ncr_sc->sc_dev)); 223 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 224 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 225 printf("%s: parity error\n", device_xname(ncr_sc->sc_dev)); 226 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 227 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 228 printf("%s: phase mismatch\n", device_xname(ncr_sc->sc_dev)); 229 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 230 (bus_csr == 0)) 231 printf("%s: disconnect\n", device_xname(ncr_sc->sc_dev)); 232 else 233 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 234 device_xname(ncr_sc->sc_dev), csr, bus_csr); 235 } 236 #endif 237 238 239 /*** 240 * The following code implements polled PDMA. 241 ***/ 242 243 int 244 sbc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 245 { 246 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 247 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 248 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 249 label_t faultbuf; 250 int resid, s; 251 252 if (datalen < ncr_sc->sc_min_dma_len || 253 (sc->sc_options & SBC_PDMA) == 0) 254 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 255 256 s = splbio(); 257 if (sbc_wait_busy(ncr_sc)) { 258 splx(s); 259 return 0; 260 } 261 262 *ncr_sc->sci_mode |= SCI_MODE_DMA; 263 *ncr_sc->sci_irecv = 0; 264 265 resid = datalen; 266 267 /* 268 * Setup for a possible bus error caused by SCSI controller 269 * switching out of DATA OUT before we're done with the 270 * current transfer. (See comment before sbc_drq_intr().) 271 */ 272 nofault = &faultbuf; 273 if (setjmp(nofault)) { 274 goto interrupt; 275 } 276 277 #define R4 *(u_int32_t *)data = *long_data, data += 4; 278 #define R1 *(u_int8_t *)data = *byte_data, data += 1; 279 for (; resid >= 128; resid -= 128) { 280 if (sbc_ready(ncr_sc)) 281 goto interrupt; 282 R4; R4; R4; R4; R4; R4; R4; R4; 283 R4; R4; R4; R4; R4; R4; R4; R4; 284 R4; R4; R4; R4; R4; R4; R4; R4; 285 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 286 } 287 while (resid) { 288 if (sbc_ready(ncr_sc)) 289 goto interrupt; 290 R1; 291 resid--; 292 } 293 #undef R4 294 #undef R1 295 296 interrupt: 297 nofault = NULL; 298 SCI_CLR_INTR(ncr_sc); 299 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 300 *ncr_sc->sci_icmd = 0; 301 splx(s); 302 return (datalen - resid); 303 } 304 305 int 306 sbc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 307 { 308 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 309 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 310 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 311 label_t faultbuf; 312 int resid, s; 313 u_int8_t icmd; 314 315 #if 1 316 /* Work around lame gcc initialization bug */ 317 (void)&data; 318 #endif 319 320 if (datalen < ncr_sc->sc_min_dma_len || 321 (sc->sc_options & SBC_PDMA) == 0) 322 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 323 324 s = splbio(); 325 if (sbc_wait_busy(ncr_sc)) { 326 splx(s); 327 return 0; 328 } 329 330 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 331 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 332 *ncr_sc->sci_mode |= SCI_MODE_DMA; 333 *ncr_sc->sci_dma_send = 0; 334 335 /* 336 * Setup for a possible bus error caused by SCSI controller 337 * switching out of DATA OUT before we're done with the 338 * current transfer. (See comment before sbc_drq_intr().) 339 */ 340 nofault = &faultbuf; 341 342 if (setjmp(nofault)) { 343 printf("buf = 0x%lx, fault = 0x%lx\n", 344 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 345 panic("Unexpected bus error in sbc_pdma_out()"); 346 } 347 348 #define W1 *byte_data = *(u_int8_t *)data, data += 1 349 #define W4 *long_data = *(u_int32_t *)data, data += 4 350 for (resid = datalen; resid >= 64; resid -= 64) { 351 if (sbc_ready(ncr_sc)) 352 goto interrupt; 353 W1; 354 if (sbc_ready(ncr_sc)) 355 goto interrupt; 356 W1; 357 if (sbc_ready(ncr_sc)) 358 goto interrupt; 359 W1; 360 if (sbc_ready(ncr_sc)) 361 goto interrupt; 362 W1; 363 if (sbc_ready(ncr_sc)) 364 goto interrupt; 365 W4; W4; W4; W4; 366 W4; W4; W4; W4; 367 W4; W4; W4; W4; 368 W4; W4; W4; 369 } 370 while (resid) { 371 if (sbc_ready(ncr_sc)) 372 goto interrupt; 373 W1; 374 resid--; 375 } 376 #undef W1 377 #undef W4 378 if (sbc_wait_dreq(ncr_sc)) 379 printf("%s: timeout waiting for DREQ.\n", 380 device_xname(ncr_sc->sc_dev)); 381 382 *byte_data = 0; 383 goto done; 384 385 interrupt: 386 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 387 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 388 --resid; 389 } 390 391 done: 392 SCI_CLR_INTR(ncr_sc); 393 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 394 *ncr_sc->sci_icmd = icmd; 395 splx(s); 396 return (datalen - resid); 397 } 398 399 400 /*** 401 * The following code implements interrupt-driven PDMA. 402 ***/ 403 404 /* 405 * This is the meat of the PDMA transfer. 406 * When we get here, we shove data as fast as the mac can take it. 407 * We depend on several things: 408 * * All macs after the Mac Plus that have a 5380 chip should have a general 409 * logic IC that handshakes data for blind transfers. 410 * * If the SCSI controller finishes sending/receiving data before we do, 411 * the same general logic IC will generate a /BERR for us in short order. 412 * * The fault address for said /BERR minus the base address for the 413 * transfer will be the amount of data that was actually written. 414 * 415 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 416 * detect and handle the bus error for early termination of a command. 417 * This is usually caused by a disconnecting target. 418 */ 419 void 420 sbc_drq_intr(void *p) 421 { 422 struct sbc_softc *sc = (struct sbc_softc *)p; 423 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 424 struct sci_req *sr = ncr_sc->sc_current; 425 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 426 label_t faultbuf; 427 volatile u_int32_t *long_drq; 428 u_int32_t *long_data; 429 volatile u_int8_t *drq = 0; /* XXX gcc4 -Wuninitialized */ 430 u_int8_t *data; 431 int count, dcount, resid; 432 u_int8_t tmp; 433 434 /* 435 * If we're not ready to xfer data, or have no more, just return. 436 */ 437 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 438 return; 439 440 #ifdef SBC_DEBUG 441 if (sbc_debug & SBC_DB_INTR) 442 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 443 device_xname(ncr_sc->sc_dev), dh->dh_len, dh->dh_flags); 444 #endif 445 446 /* 447 * Setup for a possible bus error caused by SCSI controller 448 * switching out of DATA-IN/OUT before we're done with the 449 * current transfer. 450 */ 451 nofault = &faultbuf; 452 453 if (setjmp(nofault)) { 454 nofault = (label_t *)0; 455 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 456 count = (( (u_long)m68k_fault_addr 457 - (u_long)sc->sc_drq_addr)); 458 459 if ((count < 0) || (count > dh->dh_len)) { 460 printf("%s: complete=0x%x (pending 0x%x)\n", 461 device_xname(ncr_sc->sc_dev), count, 462 dh->dh_len); 463 panic("something is wrong"); 464 } 465 466 dh->dh_addr += count; 467 dh->dh_len -= count; 468 } else 469 count = 0; 470 471 #ifdef SBC_DEBUG 472 if (sbc_debug & SBC_DB_INTR) 473 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 474 device_xname(ncr_sc->sc_dev), count, dh->dh_len); 475 #endif 476 m68k_fault_addr = 0; 477 478 return; 479 } 480 481 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 482 dcount = 0; 483 484 /* 485 * Get the source address aligned. 486 */ 487 resid = 488 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 489 if (count && count < 4) { 490 drq = (volatile u_int8_t *)sc->sc_drq_addr; 491 data = (u_int8_t *)dh->dh_addr; 492 493 #define W1 *drq++ = *data++ 494 while (count) { 495 W1; count--; 496 } 497 #undef W1 498 dh->dh_addr += resid; 499 dh->dh_len -= resid; 500 } 501 502 /* 503 * Start the transfer. 504 */ 505 while (dh->dh_len) { 506 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 507 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 508 long_data = (u_int32_t *)dh->dh_addr; 509 510 #define W4 *long_drq++ = *long_data++ 511 while (count >= 64) { 512 W4; W4; W4; W4; W4; W4; W4; W4; 513 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 514 count -= 64; 515 } 516 while (count >= 4) { 517 W4; count -= 4; 518 } 519 #undef W4 520 data = (u_int8_t *)long_data; 521 drq = (volatile u_int8_t *)long_drq; 522 523 #define W1 *drq++ = *data++ 524 while (count) { 525 W1; count--; 526 } 527 #undef W1 528 dh->dh_len -= dcount; 529 dh->dh_addr += dcount; 530 } 531 dh->dh_flags |= SBC_DH_DONE; 532 533 /* 534 * XXX -- Read a byte from the SBC to trigger a /BERR. 535 * This seems to be necessary for us to notice that 536 * the target has disconnected. Ick. 06 jun 1996 (sr) 537 */ 538 if (dcount >= MAX_DMA_LEN) 539 drq = (volatile u_int8_t *)sc->sc_drq_addr; 540 tmp = *drq; 541 } else { /* Data In */ 542 /* 543 * Get the dest address aligned. 544 */ 545 resid = 546 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 547 if (count && count < 4) { 548 data = (u_int8_t *)dh->dh_addr; 549 drq = (volatile u_int8_t *)sc->sc_drq_addr; 550 551 #define R1 *data++ = *drq++ 552 while (count) { 553 R1; count--; 554 } 555 #undef R1 556 dh->dh_addr += resid; 557 dh->dh_len -= resid; 558 } 559 560 /* 561 * Start the transfer. 562 */ 563 while (dh->dh_len) { 564 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 565 long_data = (u_int32_t *)dh->dh_addr; 566 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 567 568 #define R4 *long_data++ = *long_drq++ 569 while (count >= 64) { 570 R4; R4; R4; R4; R4; R4; R4; R4; 571 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 572 count -= 64; 573 } 574 while (count >= 4) { 575 R4; count -= 4; 576 } 577 #undef R4 578 data = (u_int8_t *)long_data; 579 drq = (volatile u_int8_t *)long_drq; 580 581 #define R1 *data++ = *drq++ 582 while (count) { 583 R1; count--; 584 } 585 #undef R1 586 dh->dh_len -= dcount; 587 dh->dh_addr += dcount; 588 } 589 dh->dh_flags |= SBC_DH_DONE; 590 } 591 592 /* 593 * OK. No bus error occurred above. Clear the nofault flag 594 * so we no longer short-circuit bus errors. 595 */ 596 nofault = (label_t *)0; 597 598 #ifdef SBC_DEBUG 599 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 600 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 601 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 602 *ncr_sc->sci_bus_csr); 603 #endif 604 } 605 606 void 607 sbc_dma_alloc(struct ncr5380_softc *ncr_sc) 608 { 609 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 610 struct sci_req *sr = ncr_sc->sc_current; 611 struct scsipi_xfer *xs = sr->sr_xs; 612 struct sbc_pdma_handle *dh; 613 int i, xlen; 614 615 #ifdef DIAGNOSTIC 616 if (sr->sr_dma_hand != NULL) 617 panic("sbc_dma_alloc: already have PDMA handle"); 618 #endif 619 620 /* Polled transfers shouldn't allocate a PDMA handle. */ 621 if (sr->sr_flags & SR_IMMED) 622 return; 623 624 xlen = ncr_sc->sc_datalen; 625 626 /* Make sure our caller checked sc_min_dma_len. */ 627 if (xlen < MIN_DMA_LEN) 628 panic("sbc_dma_alloc: len=0x%x", xlen); 629 630 /* 631 * Find free PDMA handle. Guaranteed to find one since we 632 * have as many PDMA handles as the driver has processes. 633 * (instances?) 634 */ 635 for (i = 0; i < SCI_OPENINGS; i++) { 636 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 637 goto found; 638 } 639 panic("sbc: no free PDMA handles"); 640 found: 641 dh = &sc->sc_pdma[i]; 642 dh->dh_flags = SBC_DH_BUSY; 643 dh->dh_addr = ncr_sc->sc_dataptr; 644 dh->dh_len = xlen; 645 646 /* Copy the 'write' flag for convenience. */ 647 if (xs->xs_control & XS_CTL_DATA_OUT) 648 dh->dh_flags |= SBC_DH_OUT; 649 650 sr->sr_dma_hand = dh; 651 } 652 653 void 654 sbc_dma_free(struct ncr5380_softc *ncr_sc) 655 { 656 struct sci_req *sr = ncr_sc->sc_current; 657 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 658 659 #ifdef DIAGNOSTIC 660 if (sr->sr_dma_hand == NULL) 661 panic("sbc_dma_free: no DMA handle"); 662 #endif 663 664 if (ncr_sc->sc_state & NCR_DOINGDMA) 665 panic("sbc_dma_free: free while in progress"); 666 667 if (dh->dh_flags & SBC_DH_BUSY) { 668 dh->dh_flags = 0; 669 dh->dh_addr = NULL; 670 dh->dh_len = 0; 671 } 672 sr->sr_dma_hand = NULL; 673 } 674 675 void 676 sbc_dma_poll(struct ncr5380_softc *ncr_sc) 677 { 678 struct sci_req *sr = ncr_sc->sc_current; 679 680 /* 681 * We shouldn't arrive here; if SR_IMMED is set, then 682 * dma_alloc() should have refused to allocate a handle 683 * for the transfer. This forces the polled PDMA code 684 * to handle the request... 685 */ 686 #ifdef SBC_DEBUG 687 if (sbc_debug & SBC_DB_DMA) 688 printf("%s: lost DRQ interrupt?\n", 689 device_xname(ncr_sc->sc_dev)); 690 #endif 691 sr->sr_flags |= SR_OVERDUE; 692 } 693 694 void 695 sbc_dma_setup(struct ncr5380_softc *ncr_sc) 696 { 697 /* Not needed; we don't have real DMA */ 698 } 699 700 void 701 sbc_dma_start(struct ncr5380_softc *ncr_sc) 702 { 703 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 704 struct sci_req *sr = ncr_sc->sc_current; 705 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 706 707 /* 708 * Match bus phase, clear pending interrupts, set DMA mode, and 709 * assert data bus (for writing only), then start the transfer. 710 */ 711 if (dh->dh_flags & SBC_DH_OUT) { 712 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 713 SCI_CLR_INTR(ncr_sc); 714 if (sc->sc_clrintr) 715 (*sc->sc_clrintr)(ncr_sc); 716 *ncr_sc->sci_mode |= SCI_MODE_DMA; 717 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 718 *ncr_sc->sci_dma_send = 0; 719 } else { 720 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 721 SCI_CLR_INTR(ncr_sc); 722 if (sc->sc_clrintr) 723 (*sc->sc_clrintr)(ncr_sc); 724 *ncr_sc->sci_mode |= SCI_MODE_DMA; 725 *ncr_sc->sci_icmd = 0; 726 *ncr_sc->sci_irecv = 0; 727 } 728 ncr_sc->sc_state |= NCR_DOINGDMA; 729 730 #ifdef SBC_DEBUG 731 if (sbc_debug & SBC_DB_DMA) 732 printf("%s: PDMA started, va=%p, len=0x%x\n", 733 device_xname(ncr_sc->sc_dev), dh->dh_addr, dh->dh_len); 734 #endif 735 } 736 737 void 738 sbc_dma_eop(struct ncr5380_softc *ncr_sc) 739 { 740 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 741 } 742 743 void 744 sbc_dma_stop(struct ncr5380_softc *ncr_sc) 745 { 746 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 747 struct sci_req *sr = ncr_sc->sc_current; 748 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 749 int ntrans; 750 751 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 752 #ifdef SBC_DEBUG 753 if (sbc_debug & SBC_DB_DMA) 754 printf("%s: dma_stop: DMA not running\n", 755 device_xname(ncr_sc->sc_dev)); 756 #endif 757 return; 758 } 759 ncr_sc->sc_state &= ~NCR_DOINGDMA; 760 761 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 762 ntrans = ncr_sc->sc_datalen - dh->dh_len; 763 764 #ifdef SBC_DEBUG 765 if (sbc_debug & SBC_DB_DMA) 766 printf("%s: dma_stop: ntrans=0x%x\n", 767 device_xname(ncr_sc->sc_dev), ntrans); 768 #endif 769 770 if (ntrans > ncr_sc->sc_datalen) 771 panic("sbc_dma_stop: excess transfer"); 772 773 /* Adjust data pointer */ 774 ncr_sc->sc_dataptr += ntrans; 775 ncr_sc->sc_datalen -= ntrans; 776 777 /* Clear any pending interrupts. */ 778 SCI_CLR_INTR(ncr_sc); 779 if (sc->sc_clrintr) 780 (*sc->sc_clrintr)(ncr_sc); 781 } 782 783 /* Put SBIC back into PIO mode. */ 784 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 785 *ncr_sc->sci_icmd = 0; 786 787 #ifdef SBC_DEBUG 788 if (sbc_debug & SBC_DB_REG) 789 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 790 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 791 *ncr_sc->sci_bus_csr); 792 #endif 793 } 794
Indexes created Mon Sep 22 13:09:51 GMT 2025