sbc.c revision 1.53.4.1
1 /* $NetBSD: sbc.c,v 1.53.4.1 2010/03/11 15:02:35 yamt Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.53.4.1 2010/03/11 15:02:35 yamt Exp $"); 49 50 #include "opt_ddb.h" 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/buf.h> 59 #include <sys/proc.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsipi_debug.h> 64 #include <dev/scsipi/scsiconf.h> 65 66 #include <dev/ic/ncr5380reg.h> 67 #include <dev/ic/ncr5380var.h> 68 69 #include <machine/cpu.h> 70 #include <machine/viareg.h> 71 72 #include <mac68k/dev/sbcreg.h> 73 #include <mac68k/dev/sbcvar.h> 74 75 /* SBC_DEBUG -- relies on DDB */ 76 #ifdef SBC_DEBUG 77 # define SBC_DB_INTR 0x01 78 # define SBC_DB_DMA 0x02 79 # define SBC_DB_REG 0x04 80 # define SBC_DB_BREAK 0x08 81 # ifndef DDB 82 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 83 # endif 84 # define SBC_BREAK \ 85 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 86 #else 87 # define SBC_BREAK 88 #endif 89 90 91 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 92 int sbc_link_flags = 0 /* | SDEV_DB2 */; 93 int sbc_options = 0 /* | SBC_PDMA */; 94 95 extern label_t *nofault; 96 extern void * m68k_fault_addr; 97 98 static int sbc_wait_busy(struct ncr5380_softc *); 99 static int sbc_ready(struct ncr5380_softc *); 100 static int sbc_wait_dreq(struct ncr5380_softc *); 101 102 103 /*** 104 * General support for Mac-specific SCSI logic. 105 ***/ 106 107 /* These are used in the following inline functions. */ 108 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 109 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 110 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 111 112 /* Return zero on success. */ 113 static inline int 114 sbc_wait_busy(struct ncr5380_softc *sc) 115 { 116 int timo = sbc_wait_busy_timo; 117 for (;;) { 118 if (SCI_BUSY(sc)) { 119 timo = 0; /* return 0 */ 120 break; 121 } 122 if (--timo < 0) 123 break; /* return -1 */ 124 delay(2); 125 } 126 return (timo); 127 } 128 129 static inline int 130 sbc_ready(struct ncr5380_softc *sc) 131 { 132 int timo = sbc_ready_timo; 133 134 for (;;) { 135 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 136 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 137 timo = 0; 138 break; 139 } 140 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 141 || (SCI_BUSY(sc) == 0)) { 142 timo = -1; 143 break; 144 } 145 if (--timo < 0) 146 break; /* return -1 */ 147 delay(2); 148 } 149 return (timo); 150 } 151 152 static inline int 153 sbc_wait_dreq(struct ncr5380_softc *sc) 154 { 155 int timo = sbc_wait_dreq_timo; 156 157 for (;;) { 158 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 159 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 160 timo = 0; 161 break; 162 } 163 if (--timo < 0) 164 break; /* return -1 */ 165 delay(2); 166 } 167 return (timo); 168 } 169 170 void 171 sbc_irq_intr(void *p) 172 { 173 struct ncr5380_softc *ncr_sc = p; 174 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 175 int claimed = 0; 176 177 /* How we ever arrive here without IRQ set is a mystery... */ 178 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 179 #ifdef SBC_DEBUG 180 if (sbc_debug & SBC_DB_INTR) 181 decode_5380_intr(ncr_sc); 182 #endif 183 if (!cold) 184 claimed = ncr5380_intr(ncr_sc); 185 if (!claimed) { 186 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 187 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 188 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 189 if (sc->sc_clrintr) 190 (*sc->sc_clrintr)(ncr_sc); 191 } 192 #ifdef SBC_DEBUG 193 else { 194 printf("%s: spurious intr\n", 195 device_xname(ncr_sc->sc_dev)); 196 SBC_BREAK; 197 } 198 #endif 199 } 200 } 201 } 202 203 #ifdef SBC_DEBUG 204 void 205 decode_5380_intr(struct ncr5380_softc *ncr_sc) 206 { 207 u_int8_t csr = *ncr_sc->sci_csr; 208 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 209 210 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 211 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 212 if (csr & SCI_BUS_IO) 213 printf("%s: reselect\n", device_xname(ncr_sc->sc_dev)); 214 else 215 printf("%s: select\n", device_xname(ncr_sc->sc_dev)); 216 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 217 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 218 printf("%s: DMA eop\n", device_xname(ncr_sc->sc_dev)); 219 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 220 ((bus_csr & ~SCI_BUS_RST) == 0)) 221 printf("%s: bus reset\n", device_xname(ncr_sc->sc_dev)); 222 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 223 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 224 printf("%s: parity error\n", device_xname(ncr_sc->sc_dev)); 225 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 226 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 227 printf("%s: phase mismatch\n", device_xname(ncr_sc->sc_dev)); 228 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 229 (bus_csr == 0)) 230 printf("%s: disconnect\n", device_xname(ncr_sc->sc_dev)); 231 else 232 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 233 device_xname(ncr_sc->sc_dev), csr, bus_csr); 234 } 235 #endif 236 237 238 /*** 239 * The following code implements polled PDMA. 240 ***/ 241 242 int 243 sbc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 244 { 245 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 246 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 247 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 248 label_t faultbuf; 249 int resid, s; 250 251 if (datalen < ncr_sc->sc_min_dma_len || 252 (sc->sc_options & SBC_PDMA) == 0) 253 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 254 255 s = splbio(); 256 if (sbc_wait_busy(ncr_sc)) { 257 splx(s); 258 return 0; 259 } 260 261 *ncr_sc->sci_mode |= SCI_MODE_DMA; 262 *ncr_sc->sci_irecv = 0; 263 264 resid = datalen; 265 266 /* 267 * Setup for a possible bus error caused by SCSI controller 268 * switching out of DATA OUT before we're done with the 269 * current transfer. (See comment before sbc_drq_intr().) 270 */ 271 nofault = &faultbuf; 272 if (setjmp(nofault)) { 273 goto interrupt; 274 } 275 276 #define R4 *(u_int32_t *)data = *long_data, data += 4; 277 #define R1 *(u_int8_t *)data = *byte_data, data += 1; 278 for (; resid >= 128; resid -= 128) { 279 if (sbc_ready(ncr_sc)) 280 goto interrupt; 281 R4; R4; R4; R4; R4; R4; R4; R4; 282 R4; R4; R4; R4; R4; R4; R4; R4; 283 R4; R4; R4; R4; R4; R4; R4; R4; 284 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 285 } 286 while (resid) { 287 if (sbc_ready(ncr_sc)) 288 goto interrupt; 289 R1; 290 resid--; 291 } 292 #undef R4 293 #undef R1 294 295 interrupt: 296 nofault = NULL; 297 SCI_CLR_INTR(ncr_sc); 298 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 299 *ncr_sc->sci_icmd = 0; 300 splx(s); 301 return (datalen - resid); 302 } 303 304 int 305 sbc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 306 { 307 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 308 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 309 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 310 label_t faultbuf; 311 int resid, s; 312 u_int8_t icmd; 313 314 #if 1 315 /* Work around lame gcc initialization bug */ 316 (void)&data; 317 #endif 318 319 if (datalen < ncr_sc->sc_min_dma_len || 320 (sc->sc_options & SBC_PDMA) == 0) 321 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 322 323 s = splbio(); 324 if (sbc_wait_busy(ncr_sc)) { 325 splx(s); 326 return 0; 327 } 328 329 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 330 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 331 *ncr_sc->sci_mode |= SCI_MODE_DMA; 332 *ncr_sc->sci_dma_send = 0; 333 334 /* 335 * Setup for a possible bus error caused by SCSI controller 336 * switching out of DATA OUT before we're done with the 337 * current transfer. (See comment before sbc_drq_intr().) 338 */ 339 nofault = &faultbuf; 340 341 if (setjmp(nofault)) { 342 printf("buf = 0x%lx, fault = 0x%lx\n", 343 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 344 panic("Unexpected bus error in sbc_pdma_out()"); 345 } 346 347 #define W1 *byte_data = *(u_int8_t *)data, data += 1 348 #define W4 *long_data = *(u_int32_t *)data, data += 4 349 for (resid = datalen; resid >= 64; resid -= 64) { 350 if (sbc_ready(ncr_sc)) 351 goto interrupt; 352 W1; 353 if (sbc_ready(ncr_sc)) 354 goto interrupt; 355 W1; 356 if (sbc_ready(ncr_sc)) 357 goto interrupt; 358 W1; 359 if (sbc_ready(ncr_sc)) 360 goto interrupt; 361 W1; 362 if (sbc_ready(ncr_sc)) 363 goto interrupt; 364 W4; W4; W4; W4; 365 W4; W4; W4; W4; 366 W4; W4; W4; W4; 367 W4; W4; W4; 368 } 369 while (resid) { 370 if (sbc_ready(ncr_sc)) 371 goto interrupt; 372 W1; 373 resid--; 374 } 375 #undef W1 376 #undef W4 377 if (sbc_wait_dreq(ncr_sc)) 378 printf("%s: timeout waiting for DREQ.\n", 379 device_xname(ncr_sc->sc_dev)); 380 381 *byte_data = 0; 382 goto done; 383 384 interrupt: 385 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 386 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 387 --resid; 388 } 389 390 done: 391 SCI_CLR_INTR(ncr_sc); 392 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 393 *ncr_sc->sci_icmd = icmd; 394 splx(s); 395 return (datalen - resid); 396 } 397 398 399 /*** 400 * The following code implements interrupt-driven PDMA. 401 ***/ 402 403 /* 404 * This is the meat of the PDMA transfer. 405 * When we get here, we shove data as fast as the mac can take it. 406 * We depend on several things: 407 * * All macs after the Mac Plus that have a 5380 chip should have a general 408 * logic IC that handshakes data for blind transfers. 409 * * If the SCSI controller finishes sending/receiving data before we do, 410 * the same general logic IC will generate a /BERR for us in short order. 411 * * The fault address for said /BERR minus the base address for the 412 * transfer will be the amount of data that was actually written. 413 * 414 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 415 * detect and handle the bus error for early termination of a command. 416 * This is usually caused by a disconnecting target. 417 */ 418 void 419 sbc_drq_intr(void *p) 420 { 421 struct sbc_softc *sc = (struct sbc_softc *)p; 422 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 423 struct sci_req *sr = ncr_sc->sc_current; 424 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 425 label_t faultbuf; 426 volatile u_int32_t *long_drq; 427 u_int32_t *long_data; 428 volatile u_int8_t *drq = 0; /* XXX gcc4 -Wuninitialized */ 429 u_int8_t *data; 430 int count, dcount, resid; 431 u_int8_t tmp; 432 433 /* 434 * If we're not ready to xfer data, or have no more, just return. 435 */ 436 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 437 return; 438 439 #ifdef SBC_DEBUG 440 if (sbc_debug & SBC_DB_INTR) 441 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 442 device_xname(ncr_sc->sc_dev), dh->dh_len, dh->dh_flags); 443 #endif 444 445 /* 446 * Setup for a possible bus error caused by SCSI controller 447 * switching out of DATA-IN/OUT before we're done with the 448 * current transfer. 449 */ 450 nofault = &faultbuf; 451 452 if (setjmp(nofault)) { 453 nofault = (label_t *)0; 454 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 455 count = (( (u_long)m68k_fault_addr 456 - (u_long)sc->sc_drq_addr)); 457 458 if ((count < 0) || (count > dh->dh_len)) { 459 printf("%s: complete=0x%x (pending 0x%x)\n", 460 device_xname(ncr_sc->sc_dev), count, 461 dh->dh_len); 462 panic("something is wrong"); 463 } 464 465 dh->dh_addr += count; 466 dh->dh_len -= count; 467 } else 468 count = 0; 469 470 #ifdef SBC_DEBUG 471 if (sbc_debug & SBC_DB_INTR) 472 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 473 device_xname(ncr_sc->sc_dev), count, dh->dh_len); 474 #endif 475 m68k_fault_addr = 0; 476 477 return; 478 } 479 480 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 481 dcount = 0; 482 483 /* 484 * Get the source address aligned. 485 */ 486 resid = 487 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 488 if (count && count < 4) { 489 drq = (volatile u_int8_t *)sc->sc_drq_addr; 490 data = (u_int8_t *)dh->dh_addr; 491 492 #define W1 *drq++ = *data++ 493 while (count) { 494 W1; count--; 495 } 496 #undef W1 497 dh->dh_addr += resid; 498 dh->dh_len -= resid; 499 } 500 501 /* 502 * Start the transfer. 503 */ 504 while (dh->dh_len) { 505 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 506 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 507 long_data = (u_int32_t *)dh->dh_addr; 508 509 #define W4 *long_drq++ = *long_data++ 510 while (count >= 64) { 511 W4; W4; W4; W4; W4; W4; W4; W4; 512 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 513 count -= 64; 514 } 515 while (count >= 4) { 516 W4; count -= 4; 517 } 518 #undef W4 519 data = (u_int8_t *)long_data; 520 drq = (volatile u_int8_t *)long_drq; 521 522 #define W1 *drq++ = *data++ 523 while (count) { 524 W1; count--; 525 } 526 #undef W1 527 dh->dh_len -= dcount; 528 dh->dh_addr += dcount; 529 } 530 dh->dh_flags |= SBC_DH_DONE; 531 532 /* 533 * XXX -- Read a byte from the SBC to trigger a /BERR. 534 * This seems to be necessary for us to notice that 535 * the target has disconnected. Ick. 06 jun 1996 (sr) 536 */ 537 if (dcount >= MAX_DMA_LEN) 538 drq = (volatile u_int8_t *)sc->sc_drq_addr; 539 tmp = *drq; 540 } else { /* Data In */ 541 /* 542 * Get the dest address aligned. 543 */ 544 resid = 545 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 546 if (count && count < 4) { 547 data = (u_int8_t *)dh->dh_addr; 548 drq = (volatile u_int8_t *)sc->sc_drq_addr; 549 550 #define R1 *data++ = *drq++ 551 while (count) { 552 R1; count--; 553 } 554 #undef R1 555 dh->dh_addr += resid; 556 dh->dh_len -= resid; 557 } 558 559 /* 560 * Start the transfer. 561 */ 562 while (dh->dh_len) { 563 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 564 long_data = (u_int32_t *)dh->dh_addr; 565 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 566 567 #define R4 *long_data++ = *long_drq++ 568 while (count >= 64) { 569 R4; R4; R4; R4; R4; R4; R4; R4; 570 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 571 count -= 64; 572 } 573 while (count >= 4) { 574 R4; count -= 4; 575 } 576 #undef R4 577 data = (u_int8_t *)long_data; 578 drq = (volatile u_int8_t *)long_drq; 579 580 #define R1 *data++ = *drq++ 581 while (count) { 582 R1; count--; 583 } 584 #undef R1 585 dh->dh_len -= dcount; 586 dh->dh_addr += dcount; 587 } 588 dh->dh_flags |= SBC_DH_DONE; 589 } 590 591 /* 592 * OK. No bus error occurred above. Clear the nofault flag 593 * so we no longer short-circuit bus errors. 594 */ 595 nofault = (label_t *)0; 596 597 #ifdef SBC_DEBUG 598 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 599 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 600 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 601 *ncr_sc->sci_bus_csr); 602 #endif 603 } 604 605 void 606 sbc_dma_alloc(struct ncr5380_softc *ncr_sc) 607 { 608 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 609 struct sci_req *sr = ncr_sc->sc_current; 610 struct scsipi_xfer *xs = sr->sr_xs; 611 struct sbc_pdma_handle *dh; 612 int i, xlen; 613 614 #ifdef DIAGNOSTIC 615 if (sr->sr_dma_hand != NULL) 616 panic("sbc_dma_alloc: already have PDMA handle"); 617 #endif 618 619 /* Polled transfers shouldn't allocate a PDMA handle. */ 620 if (sr->sr_flags & SR_IMMED) 621 return; 622 623 xlen = ncr_sc->sc_datalen; 624 625 /* Make sure our caller checked sc_min_dma_len. */ 626 if (xlen < MIN_DMA_LEN) 627 panic("sbc_dma_alloc: len=0x%x", xlen); 628 629 /* 630 * Find free PDMA handle. Guaranteed to find one since we 631 * have as many PDMA handles as the driver has processes. 632 * (instances?) 633 */ 634 for (i = 0; i < SCI_OPENINGS; i++) { 635 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 636 goto found; 637 } 638 panic("sbc: no free PDMA handles"); 639 found: 640 dh = &sc->sc_pdma[i]; 641 dh->dh_flags = SBC_DH_BUSY; 642 dh->dh_addr = ncr_sc->sc_dataptr; 643 dh->dh_len = xlen; 644 645 /* Copy the 'write' flag for convenience. */ 646 if (xs->xs_control & XS_CTL_DATA_OUT) 647 dh->dh_flags |= SBC_DH_OUT; 648 649 sr->sr_dma_hand = dh; 650 } 651 652 void 653 sbc_dma_free(struct ncr5380_softc *ncr_sc) 654 { 655 struct sci_req *sr = ncr_sc->sc_current; 656 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 657 658 #ifdef DIAGNOSTIC 659 if (sr->sr_dma_hand == NULL) 660 panic("sbc_dma_free: no DMA handle"); 661 #endif 662 663 if (ncr_sc->sc_state & NCR_DOINGDMA) 664 panic("sbc_dma_free: free while in progress"); 665 666 if (dh->dh_flags & SBC_DH_BUSY) { 667 dh->dh_flags = 0; 668 dh->dh_addr = NULL; 669 dh->dh_len = 0; 670 } 671 sr->sr_dma_hand = NULL; 672 } 673 674 void 675 sbc_dma_poll(struct ncr5380_softc *ncr_sc) 676 { 677 struct sci_req *sr = ncr_sc->sc_current; 678 679 /* 680 * We shouldn't arrive here; if SR_IMMED is set, then 681 * dma_alloc() should have refused to allocate a handle 682 * for the transfer. This forces the polled PDMA code 683 * to handle the request... 684 */ 685 #ifdef SBC_DEBUG 686 if (sbc_debug & SBC_DB_DMA) 687 printf("%s: lost DRQ interrupt?\n", 688 device_xname(ncr_sc->sc_dev)); 689 #endif 690 sr->sr_flags |= SR_OVERDUE; 691 } 692 693 void 694 sbc_dma_setup(struct ncr5380_softc *ncr_sc) 695 { 696 /* Not needed; we don't have real DMA */ 697 } 698 699 void 700 sbc_dma_start(struct ncr5380_softc *ncr_sc) 701 { 702 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 703 struct sci_req *sr = ncr_sc->sc_current; 704 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 705 706 /* 707 * Match bus phase, clear pending interrupts, set DMA mode, and 708 * assert data bus (for writing only), then start the transfer. 709 */ 710 if (dh->dh_flags & SBC_DH_OUT) { 711 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 712 SCI_CLR_INTR(ncr_sc); 713 if (sc->sc_clrintr) 714 (*sc->sc_clrintr)(ncr_sc); 715 *ncr_sc->sci_mode |= SCI_MODE_DMA; 716 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 717 *ncr_sc->sci_dma_send = 0; 718 } else { 719 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 720 SCI_CLR_INTR(ncr_sc); 721 if (sc->sc_clrintr) 722 (*sc->sc_clrintr)(ncr_sc); 723 *ncr_sc->sci_mode |= SCI_MODE_DMA; 724 *ncr_sc->sci_icmd = 0; 725 *ncr_sc->sci_irecv = 0; 726 } 727 ncr_sc->sc_state |= NCR_DOINGDMA; 728 729 #ifdef SBC_DEBUG 730 if (sbc_debug & SBC_DB_DMA) 731 printf("%s: PDMA started, va=%p, len=0x%x\n", 732 device_xname(ncr_sc->sc_dev), dh->dh_addr, dh->dh_len); 733 #endif 734 } 735 736 void 737 sbc_dma_eop(struct ncr5380_softc *ncr_sc) 738 { 739 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 740 } 741 742 void 743 sbc_dma_stop(struct ncr5380_softc *ncr_sc) 744 { 745 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 746 struct sci_req *sr = ncr_sc->sc_current; 747 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 748 int ntrans; 749 750 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 751 #ifdef SBC_DEBUG 752 if (sbc_debug & SBC_DB_DMA) 753 printf("%s: dma_stop: DMA not running\n", 754 device_xname(ncr_sc->sc_dev)); 755 #endif 756 return; 757 } 758 ncr_sc->sc_state &= ~NCR_DOINGDMA; 759 760 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 761 ntrans = ncr_sc->sc_datalen - dh->dh_len; 762 763 #ifdef SBC_DEBUG 764 if (sbc_debug & SBC_DB_DMA) 765 printf("%s: dma_stop: ntrans=0x%x\n", 766 device_xname(ncr_sc->sc_dev), ntrans); 767 #endif 768 769 if (ntrans > ncr_sc->sc_datalen) 770 panic("sbc_dma_stop: excess transfer"); 771 772 /* Adjust data pointer */ 773 ncr_sc->sc_dataptr += ntrans; 774 ncr_sc->sc_datalen -= ntrans; 775 776 /* Clear any pending interrupts. */ 777 SCI_CLR_INTR(ncr_sc); 778 if (sc->sc_clrintr) 779 (*sc->sc_clrintr)(ncr_sc); 780 } 781 782 /* Put SBIC back into PIO mode. */ 783 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 784 *ncr_sc->sci_icmd = 0; 785 786 #ifdef SBC_DEBUG 787 if (sbc_debug & SBC_DB_REG) 788 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 789 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 790 *ncr_sc->sci_bus_csr); 791 #endif 792 } 793
Indexes created Thu Oct 02 14:10:14 GMT 2025