sbc.c revision 1.59
1 /* $NetBSD: sbc.c,v 1.59 2023/02/18 13:28:05 nat Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.59 2023/02/18 13:28:05 nat Exp $"); 49 50 #include "opt_ddb.h" 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/buf.h> 59 #include <sys/proc.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsipi_debug.h> 64 #include <dev/scsipi/scsiconf.h> 65 66 #include <dev/ic/ncr5380reg.h> 67 #include <dev/ic/ncr5380var.h> 68 69 #include <machine/cpu.h> 70 #include <machine/viareg.h> 71 72 #include <mac68k/dev/sbcreg.h> 73 #include <mac68k/dev/sbcvar.h> 74 75 /* SBC_DEBUG -- relies on DDB */ 76 #ifdef SBC_DEBUG 77 # define SBC_DB_INTR 0x01 78 # define SBC_DB_DMA 0x02 79 # define SBC_DB_REG 0x04 80 # define SBC_DB_BREAK 0x08 81 # ifndef DDB 82 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 83 # endif 84 # define SBC_BREAK \ 85 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 86 #else 87 # define SBC_BREAK 88 #endif 89 90 91 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 92 int sbc_link_flags = 0 /* | SDEV_DB2 */; 93 int sbc_options = 0 /* | SBC_PDMA */; 94 95 extern label_t *nofault; 96 extern void * m68k_fault_addr; 97 98 static int sbc_wait_busy(struct ncr5380_softc *); 99 static int sbc_ready(struct ncr5380_softc *); 100 static int sbc_wait_dreq(struct ncr5380_softc *); 101 102 103 /*** 104 * General support for Mac-specific SCSI logic. 105 ***/ 106 107 /* These are used in the following inline functions. */ 108 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 109 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 110 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 111 112 /* Return zero on success. */ 113 static inline int 114 sbc_wait_busy(struct ncr5380_softc *sc) 115 { 116 int timo = sbc_wait_busy_timo; 117 for (;;) { 118 if (SCI_BUSY(sc)) { 119 timo = 0; /* return 0 */ 120 break; 121 } 122 if (--timo < 0) 123 break; /* return -1 */ 124 delay(2); 125 } 126 return (timo); 127 } 128 129 static inline int 130 sbc_ready(struct ncr5380_softc *sc) 131 { 132 int timo = sbc_ready_timo; 133 134 for (;;) { 135 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 136 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 137 timo = 0; 138 break; 139 } 140 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 141 || (SCI_BUSY(sc) == 0)) { 142 timo = -1; 143 break; 144 } 145 if (--timo < 0) 146 break; /* return -1 */ 147 delay(2); 148 } 149 return (timo); 150 } 151 152 static inline int 153 sbc_wait_dreq(struct ncr5380_softc *sc) 154 { 155 int timo = sbc_wait_dreq_timo; 156 157 for (;;) { 158 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 159 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 160 timo = 0; 161 break; 162 } 163 if (--timo < 0) 164 break; /* return -1 */ 165 delay(2); 166 } 167 return (timo); 168 } 169 170 void 171 sbc_irq_intr(void *p) 172 { 173 struct ncr5380_softc *ncr_sc = p; 174 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 175 int claimed = 0; 176 177 /* How we ever arrive here without IRQ set is a mystery... */ 178 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 179 #ifdef SBC_DEBUG 180 if (sbc_debug & SBC_DB_INTR) 181 decode_5380_intr(ncr_sc); 182 #endif 183 if (!cold) 184 claimed = ncr5380_intr(ncr_sc); 185 if (!claimed) { 186 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 187 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 188 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 189 if (sc->sc_clrintr) 190 (*sc->sc_clrintr)(ncr_sc); 191 } 192 #ifdef SBC_DEBUG 193 else { 194 printf("%s: spurious intr\n", 195 device_xname(ncr_sc->sc_dev)); 196 SBC_BREAK; 197 } 198 #endif 199 } 200 } 201 } 202 203 #ifdef SBC_DEBUG 204 void 205 decode_5380_intr(struct ncr5380_softc *ncr_sc) 206 { 207 u_int8_t csr = *ncr_sc->sci_csr; 208 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 209 210 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 211 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 212 if (csr & SCI_BUS_IO) 213 printf("%s: reselect\n", device_xname(ncr_sc->sc_dev)); 214 else 215 printf("%s: select\n", device_xname(ncr_sc->sc_dev)); 216 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 217 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 218 printf("%s: DMA eop\n", device_xname(ncr_sc->sc_dev)); 219 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 220 ((bus_csr & ~SCI_BUS_RST) == 0)) 221 printf("%s: bus reset\n", device_xname(ncr_sc->sc_dev)); 222 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 223 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 224 printf("%s: parity error\n", device_xname(ncr_sc->sc_dev)); 225 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 226 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 227 printf("%s: phase mismatch\n", device_xname(ncr_sc->sc_dev)); 228 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 229 (bus_csr == 0)) 230 printf("%s: disconnect\n", device_xname(ncr_sc->sc_dev)); 231 else 232 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 233 device_xname(ncr_sc->sc_dev), csr, bus_csr); 234 } 235 #endif 236 237 238 /*** 239 * The following code implements polled PDMA. 240 ***/ 241 242 int 243 sbc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 244 { 245 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 246 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 247 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 248 label_t faultbuf; 249 int resid, s; 250 251 if (datalen < ncr_sc->sc_min_dma_len || 252 (sc->sc_options & SBC_PDMA) == 0 || 253 (ncr_sc->sc_current != NULL && 254 (ncr_sc->sc_current->sr_xs->xs_control & XS_CTL_POLL))) 255 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 256 257 s = splbio(); 258 if (sbc_wait_busy(ncr_sc)) { 259 splx(s); 260 return 0; 261 } 262 263 *ncr_sc->sci_mode |= SCI_MODE_DMA; 264 *ncr_sc->sci_irecv = 0; 265 266 resid = datalen; 267 268 /* 269 * Setup for a possible bus error caused by SCSI controller 270 * switching out of DATA OUT before we're done with the 271 * current transfer. (See comment before sbc_drq_intr().) 272 */ 273 nofault = &faultbuf; 274 if (setjmp(nofault)) { 275 goto interrupt; 276 } 277 278 #define R4 *(u_int32_t *)data = *long_data, data += 4; 279 for (; resid >= 128; resid -= 128) { 280 if (sbc_ready(ncr_sc)) 281 goto interrupt; 282 R4; R4; R4; R4; R4; R4; R4; R4; 283 R4; R4; R4; R4; R4; R4; R4; R4; 284 R4; R4; R4; R4; R4; R4; R4; R4; 285 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 286 } 287 while (resid) { 288 if (sbc_ready(ncr_sc)) 289 goto interrupt; 290 *(u_int8_t *)data = *byte_data, data += 1; 291 resid--; 292 } 293 #undef R4 294 295 interrupt: 296 nofault = NULL; 297 SCI_CLR_INTR(ncr_sc); 298 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 299 *ncr_sc->sci_icmd = 0; 300 splx(s); 301 return (datalen - resid); 302 } 303 304 int 305 sbc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 306 { 307 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 308 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 309 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 310 label_t faultbuf; 311 int resid, s; 312 u_int8_t icmd; 313 314 #if 1 315 /* Work around lame gcc initialization bug */ 316 (void)&data; 317 #endif 318 319 if (datalen < ncr_sc->sc_min_dma_len || 320 (sc->sc_options & SBC_PDMA) == 0 || 321 (sc->sc_options & SBC_PDMA_NO_WRITE) || 322 (ncr_sc->sc_current != NULL && 323 (ncr_sc->sc_current->sr_xs->xs_control & XS_CTL_POLL))) 324 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 325 326 s = splbio(); 327 if (sbc_wait_busy(ncr_sc)) { 328 splx(s); 329 return 0; 330 } 331 332 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 333 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 334 *ncr_sc->sci_mode |= SCI_MODE_DMA; 335 *ncr_sc->sci_dma_send = 0; 336 337 /* 338 * Setup for a possible bus error caused by SCSI controller 339 * switching out of DATA OUT before we're done with the 340 * current transfer. (See comment before sbc_drq_intr().) 341 */ 342 nofault = &faultbuf; 343 344 if (setjmp(nofault)) { 345 printf("buf = 0x%lx, fault = 0x%lx\n", 346 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 347 panic("Unexpected bus error in sbc_pdma_out()"); 348 } 349 350 #define W1 *byte_data = *(u_int8_t *)data, data += 1 351 #define W4 *long_data = *(u_int32_t *)data, data += 4 352 for (resid = datalen; resid >= 64; resid -= 64) { 353 if (sbc_ready(ncr_sc)) 354 goto interrupt; 355 W1; 356 if (sbc_ready(ncr_sc)) 357 goto interrupt; 358 W1; 359 if (sbc_ready(ncr_sc)) 360 goto interrupt; 361 W1; 362 if (sbc_ready(ncr_sc)) 363 goto interrupt; 364 W1; 365 if (sbc_ready(ncr_sc)) 366 goto interrupt; 367 W4; W4; W4; W4; 368 W4; W4; W4; W4; 369 W4; W4; W4; W4; 370 W4; W4; W4; 371 } 372 while (resid) { 373 if (sbc_ready(ncr_sc)) 374 goto interrupt; 375 W1; 376 resid--; 377 } 378 #undef W1 379 #undef W4 380 if (sbc_wait_dreq(ncr_sc)) 381 printf("%s: timeout waiting for DREQ.\n", 382 device_xname(ncr_sc->sc_dev)); 383 384 *byte_data = 0; 385 goto done; 386 387 interrupt: 388 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 389 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 390 --resid; 391 } 392 393 done: 394 SCI_CLR_INTR(ncr_sc); 395 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 396 *ncr_sc->sci_icmd = icmd; 397 splx(s); 398 return (datalen - resid); 399 } 400 401 402 /*** 403 * The following code implements interrupt-driven PDMA. 404 ***/ 405 406 /* 407 * This is the meat of the PDMA transfer. 408 * When we get here, we shove data as fast as the mac can take it. 409 * We depend on several things: 410 * * All macs after the Mac Plus that have a 5380 chip should have a general 411 * logic IC that handshakes data for blind transfers. 412 * * If the SCSI controller finishes sending/receiving data before we do, 413 * the same general logic IC will generate a /BERR for us in short order. 414 * * The fault address for said /BERR minus the base address for the 415 * transfer will be the amount of data that was actually written. 416 * 417 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 418 * detect and handle the bus error for early termination of a command. 419 * This is usually caused by a disconnecting target. 420 */ 421 void 422 sbc_drq_intr(void *p) 423 { 424 struct sbc_softc *sc = (struct sbc_softc *)p; 425 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 426 struct sci_req *sr = ncr_sc->sc_current; 427 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 428 label_t faultbuf; 429 volatile u_int32_t *long_drq; 430 u_int32_t *long_data; 431 volatile u_int8_t *drq = 0; /* XXX gcc4 -Wuninitialized */ 432 u_int8_t *data; 433 int count, dcount, resid; 434 435 /* 436 * If we're not ready to xfer data, or have no more, just return. 437 */ 438 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 439 return; 440 441 #ifdef SBC_DEBUG 442 if (sbc_debug & SBC_DB_INTR) 443 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 444 device_xname(ncr_sc->sc_dev), dh->dh_len, dh->dh_flags); 445 #endif 446 447 /* 448 * Setup for a possible bus error caused by SCSI controller 449 * switching out of DATA-IN/OUT before we're done with the 450 * current transfer. 451 */ 452 nofault = &faultbuf; 453 454 if (setjmp(nofault)) { 455 nofault = (label_t *)0; 456 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 457 count = (( (u_long)m68k_fault_addr 458 - (u_long)sc->sc_drq_addr)); 459 460 if ((count < 0) || (count > dh->dh_len)) { 461 printf("%s: complete=0x%x (pending 0x%x)\n", 462 device_xname(ncr_sc->sc_dev), count, 463 dh->dh_len); 464 panic("something is wrong"); 465 } 466 467 dh->dh_addr += count; 468 dh->dh_len -= count; 469 } else 470 count = 0; 471 472 #ifdef SBC_DEBUG 473 if (sbc_debug & SBC_DB_INTR) 474 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 475 device_xname(ncr_sc->sc_dev), count, dh->dh_len); 476 #endif 477 m68k_fault_addr = 0; 478 479 return; 480 } 481 482 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 483 dcount = 0; 484 485 /* 486 * Get the source address aligned. 487 */ 488 resid = 489 count = uimin(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 490 if (count && count < 4) { 491 drq = (volatile u_int8_t *)sc->sc_drq_addr; 492 data = (u_int8_t *)dh->dh_addr; 493 494 #define W1 *drq++ = *data++ 495 while (count) { 496 W1; count--; 497 } 498 #undef W1 499 dh->dh_addr += resid; 500 dh->dh_len -= resid; 501 } 502 503 /* 504 * Start the transfer. 505 */ 506 while (dh->dh_len) { 507 dcount = count = uimin(dh->dh_len, MAX_DMA_LEN); 508 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 509 long_data = (u_int32_t *)dh->dh_addr; 510 511 #define W4 *long_drq++ = *long_data++ 512 while (count >= 64) { 513 W4; W4; W4; W4; W4; W4; W4; W4; 514 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 515 count -= 64; 516 } 517 while (count >= 4) { 518 W4; count -= 4; 519 } 520 #undef W4 521 data = (u_int8_t *)long_data; 522 drq = (volatile u_int8_t *)long_drq; 523 524 #define W1 *drq++ = *data++ 525 while (count) { 526 W1; count--; 527 } 528 #undef W1 529 dh->dh_len -= dcount; 530 dh->dh_addr += dcount; 531 } 532 dh->dh_flags |= SBC_DH_DONE; 533 534 /* 535 * XXX -- Read a byte from the SBC to trigger a /BERR. 536 * This seems to be necessary for us to notice that 537 * the target has disconnected. Ick. 06 jun 1996 (sr) 538 */ 539 if (dcount >= MAX_DMA_LEN) 540 drq = (volatile u_int8_t *)sc->sc_drq_addr; 541 (void)*drq; 542 } else { /* Data In */ 543 /* 544 * Get the dest address aligned. 545 */ 546 resid = 547 count = uimin(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 548 if (count && count < 4) { 549 data = (u_int8_t *)dh->dh_addr; 550 drq = (volatile u_int8_t *)sc->sc_drq_addr; 551 while (count) { 552 *data++ = *drq++; 553 count--; 554 } 555 dh->dh_addr += resid; 556 dh->dh_len -= resid; 557 } 558 559 /* 560 * Start the transfer. 561 */ 562 while (dh->dh_len) { 563 dcount = count = uimin(dh->dh_len, MAX_DMA_LEN); 564 long_data = (u_int32_t *)dh->dh_addr; 565 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 566 567 #define R4 *long_data++ = *long_drq++ 568 while (count >= 64) { 569 R4; R4; R4; R4; R4; R4; R4; R4; 570 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 571 count -= 64; 572 } 573 while (count >= 4) { 574 R4; count -= 4; 575 } 576 #undef R4 577 data = (u_int8_t *)long_data; 578 drq = (volatile u_int8_t *)long_drq; 579 while (count) { 580 *data++ = *drq++; 581 count--; 582 } 583 dh->dh_len -= dcount; 584 dh->dh_addr += dcount; 585 } 586 dh->dh_flags |= SBC_DH_DONE; 587 } 588 589 /* 590 * OK. No bus error occurred above. Clear the nofault flag 591 * so we no longer short-circuit bus errors. 592 */ 593 nofault = (label_t *)0; 594 595 #ifdef SBC_DEBUG 596 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 597 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 598 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 599 *ncr_sc->sci_bus_csr); 600 #endif 601 } 602 603 void 604 sbc_dma_alloc(struct ncr5380_softc *ncr_sc) 605 { 606 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 607 struct sci_req *sr = ncr_sc->sc_current; 608 struct scsipi_xfer *xs = sr->sr_xs; 609 struct sbc_pdma_handle *dh; 610 int i, xlen; 611 612 #ifdef DIAGNOSTIC 613 if (sr->sr_dma_hand != NULL) 614 panic("sbc_dma_alloc: already have PDMA handle"); 615 #endif 616 617 /* Polled transfers shouldn't allocate a PDMA handle. */ 618 if (sr->sr_flags & SR_IMMED) 619 return; 620 621 xlen = ncr_sc->sc_datalen; 622 623 /* Make sure our caller checked sc_min_dma_len. */ 624 if (xlen < MIN_DMA_LEN) 625 panic("sbc_dma_alloc: len=0x%x", xlen); 626 627 /* 628 * Find free PDMA handle. Guaranteed to find one since we 629 * have as many PDMA handles as the driver has processes. 630 * (instances?) 631 */ 632 for (i = 0; i < SCI_OPENINGS; i++) { 633 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 634 goto found; 635 } 636 panic("sbc: no free PDMA handles"); 637 found: 638 dh = &sc->sc_pdma[i]; 639 dh->dh_flags = SBC_DH_BUSY; 640 dh->dh_addr = ncr_sc->sc_dataptr; 641 dh->dh_len = xlen; 642 643 /* Copy the 'write' flag for convenience. */ 644 if (xs->xs_control & XS_CTL_DATA_OUT) 645 dh->dh_flags |= SBC_DH_OUT; 646 647 sr->sr_dma_hand = dh; 648 } 649 650 void 651 sbc_dma_free(struct ncr5380_softc *ncr_sc) 652 { 653 struct sci_req *sr = ncr_sc->sc_current; 654 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 655 656 #ifdef DIAGNOSTIC 657 if (sr->sr_dma_hand == NULL) 658 panic("sbc_dma_free: no DMA handle"); 659 #endif 660 661 if (ncr_sc->sc_state & NCR_DOINGDMA) 662 panic("sbc_dma_free: free while in progress"); 663 664 if (dh->dh_flags & SBC_DH_BUSY) { 665 dh->dh_flags = 0; 666 dh->dh_addr = NULL; 667 dh->dh_len = 0; 668 } 669 sr->sr_dma_hand = NULL; 670 } 671 672 void 673 sbc_dma_poll(struct ncr5380_softc *ncr_sc) 674 { 675 struct sci_req *sr = ncr_sc->sc_current; 676 677 /* 678 * We shouldn't arrive here; if SR_IMMED is set, then 679 * dma_alloc() should have refused to allocate a handle 680 * for the transfer. This forces the polled PDMA code 681 * to handle the request... 682 */ 683 #ifdef SBC_DEBUG 684 if (sbc_debug & SBC_DB_DMA) 685 printf("%s: lost DRQ interrupt?\n", 686 device_xname(ncr_sc->sc_dev)); 687 #endif 688 sr->sr_flags |= SR_OVERDUE; 689 } 690 691 void 692 sbc_dma_setup(struct ncr5380_softc *ncr_sc) 693 { 694 /* Not needed; we don't have real DMA */ 695 } 696 697 void 698 sbc_dma_start(struct ncr5380_softc *ncr_sc) 699 { 700 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 701 struct sci_req *sr = ncr_sc->sc_current; 702 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 703 704 /* 705 * Match bus phase, clear pending interrupts, set DMA mode, and 706 * assert data bus (for writing only), then start the transfer. 707 */ 708 if (dh->dh_flags & SBC_DH_OUT) { 709 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 710 SCI_CLR_INTR(ncr_sc); 711 if (sc->sc_clrintr) 712 (*sc->sc_clrintr)(ncr_sc); 713 *ncr_sc->sci_mode |= SCI_MODE_DMA; 714 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 715 *ncr_sc->sci_dma_send = 0; 716 } else { 717 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 718 SCI_CLR_INTR(ncr_sc); 719 if (sc->sc_clrintr) 720 (*sc->sc_clrintr)(ncr_sc); 721 *ncr_sc->sci_mode |= SCI_MODE_DMA; 722 *ncr_sc->sci_icmd = 0; 723 *ncr_sc->sci_irecv = 0; 724 } 725 ncr_sc->sc_state |= NCR_DOINGDMA; 726 727 #ifdef SBC_DEBUG 728 if (sbc_debug & SBC_DB_DMA) 729 printf("%s: PDMA started, va=%p, len=0x%x\n", 730 device_xname(ncr_sc->sc_dev), dh->dh_addr, dh->dh_len); 731 #endif 732 } 733 734 void 735 sbc_dma_eop(struct ncr5380_softc *ncr_sc) 736 { 737 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 738 } 739 740 void 741 sbc_dma_stop(struct ncr5380_softc *ncr_sc) 742 { 743 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 744 struct sci_req *sr = ncr_sc->sc_current; 745 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 746 int ntrans; 747 748 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 749 #ifdef SBC_DEBUG 750 if (sbc_debug & SBC_DB_DMA) 751 printf("%s: dma_stop: DMA not running\n", 752 device_xname(ncr_sc->sc_dev)); 753 #endif 754 return; 755 } 756 ncr_sc->sc_state &= ~NCR_DOINGDMA; 757 758 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 759 ntrans = ncr_sc->sc_datalen - dh->dh_len; 760 761 #ifdef SBC_DEBUG 762 if (sbc_debug & SBC_DB_DMA) 763 printf("%s: dma_stop: ntrans=0x%x\n", 764 device_xname(ncr_sc->sc_dev), ntrans); 765 #endif 766 767 if (ntrans > ncr_sc->sc_datalen) 768 panic("sbc_dma_stop: excess transfer"); 769 770 /* Adjust data pointer */ 771 ncr_sc->sc_dataptr += ntrans; 772 ncr_sc->sc_datalen -= ntrans; 773 774 /* Clear any pending interrupts. */ 775 SCI_CLR_INTR(ncr_sc); 776 if (sc->sc_clrintr) 777 (*sc->sc_clrintr)(ncr_sc); 778 } 779 780 /* Put SBIC back into PIO mode. */ 781 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 782 *ncr_sc->sci_icmd = 0; 783 784 #ifdef SBC_DEBUG 785 if (sbc_debug & SBC_DB_REG) 786 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 787 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 788 *ncr_sc->sci_bus_csr); 789 #endif 790 } 791
Indexes created Thu Sep 25 16:09:42 GMT 2025