sbc.c revision 1.70
1 /* $NetBSD: sbc.c,v 1.70 2025/05/24 10:10:10 nat Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.70 2025/05/24 10:10:10 nat Exp $"); 49 50 #include "opt_ddb.h" 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/buf.h> 59 #include <sys/proc.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsipi_debug.h> 64 #include <dev/scsipi/scsiconf.h> 65 66 #include <dev/ic/ncr5380reg.h> 67 #include <dev/ic/ncr5380var.h> 68 69 #include <machine/cpu.h> 70 #include <machine/viareg.h> 71 72 #include <mac68k/dev/sbcreg.h> 73 #include <mac68k/dev/sbcvar.h> 74 75 /* SBC_DEBUG -- relies on DDB */ 76 #ifdef SBC_DEBUG 77 # define SBC_DB_INTR 0x01 78 # define SBC_DB_DMA 0x02 79 # define SBC_DB_REG 0x04 80 # define SBC_DB_BREAK 0x08 81 # ifndef DDB 82 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 83 # endif 84 # define SBC_BREAK \ 85 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 86 #else 87 # define SBC_BREAK 88 #endif 89 90 91 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 92 int sbc_link_flags = 0 /* | SDEV_DB2 */; 93 int sbc_options = 0 /* | SBC_PDMA */; 94 95 extern label_t *nofault; 96 extern void * m68k_fault_addr; 97 98 static int sbc_wait_busy(struct ncr5380_softc *); 99 static int sbc_ready(struct ncr5380_softc *); 100 static int sbc_wait_dreq(struct ncr5380_softc *); 101 102 103 /*** 104 * General support for Mac-specific SCSI logic. 105 ***/ 106 107 /* These are used in the following inline functions. */ 108 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 109 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 110 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 111 112 /* Return zero on success. */ 113 static inline int 114 sbc_wait_busy(struct ncr5380_softc *sc) 115 { 116 int timo = sbc_wait_busy_timo; 117 for (;;) { 118 if (SCI_BUSY(sc)) { 119 timo = 0; /* return 0 */ 120 break; 121 } 122 if (--timo < 0) 123 break; /* return -1 */ 124 delay(2); 125 } 126 return (timo); 127 } 128 129 static inline int 130 sbc_ready(struct ncr5380_softc *sc) 131 { 132 int timo = sbc_ready_timo; 133 134 for (;;) { 135 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 136 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 137 timo = 0; 138 break; 139 } 140 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 141 || (SCI_BUSY(sc) == 0)) { 142 timo = -1; 143 break; 144 } 145 if (--timo < 0) 146 break; /* return -1 */ 147 delay(2); 148 } 149 return (timo); 150 } 151 152 static inline int 153 sbc_wait_dreq(struct ncr5380_softc *sc) 154 { 155 int timo = sbc_wait_dreq_timo; 156 157 for (;;) { 158 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 159 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 160 timo = 0; 161 break; 162 } 163 if (--timo < 0) 164 break; /* return -1 */ 165 delay(2); 166 } 167 return (timo); 168 } 169 170 void 171 sbc_irq_intr(void *p) 172 { 173 struct ncr5380_softc *ncr_sc = p; 174 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 175 int claimed = 0; 176 177 /* How we ever arrive here without IRQ set is a mystery... */ 178 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 179 #ifdef SBC_DEBUG 180 if (sbc_debug & SBC_DB_INTR) 181 decode_5380_intr(ncr_sc); 182 #endif 183 if (!cold) 184 claimed = ncr5380_intr(ncr_sc); 185 if (!claimed) { 186 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 187 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 188 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 189 if (sc->sc_clrintr) 190 (*sc->sc_clrintr)(ncr_sc); 191 } 192 #ifdef SBC_DEBUG 193 else { 194 printf("%s: spurious intr\n", 195 device_xname(ncr_sc->sc_dev)); 196 SBC_BREAK; 197 } 198 #endif 199 } 200 } 201 } 202 203 #ifdef SBC_DEBUG 204 void 205 decode_5380_intr(struct ncr5380_softc *ncr_sc) 206 { 207 u_int8_t csr = *ncr_sc->sci_csr; 208 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 209 210 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 211 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 212 if (csr & SCI_BUS_IO) 213 printf("%s: reselect\n", device_xname(ncr_sc->sc_dev)); 214 else 215 printf("%s: select\n", device_xname(ncr_sc->sc_dev)); 216 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 217 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 218 printf("%s: DMA eop\n", device_xname(ncr_sc->sc_dev)); 219 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 220 ((bus_csr & ~SCI_BUS_RST) == 0)) 221 printf("%s: bus reset\n", device_xname(ncr_sc->sc_dev)); 222 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 223 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 224 printf("%s: parity error\n", device_xname(ncr_sc->sc_dev)); 225 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 226 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 227 printf("%s: phase mismatch\n", device_xname(ncr_sc->sc_dev)); 228 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 229 (bus_csr == 0)) 230 printf("%s: disconnect\n", device_xname(ncr_sc->sc_dev)); 231 else 232 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 233 device_xname(ncr_sc->sc_dev), csr, bus_csr); 234 } 235 #endif 236 237 238 /*** 239 * The following code implements polled PDMA. 240 ***/ 241 242 int 243 sbc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 244 { 245 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 246 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 247 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 248 label_t faultbuf; 249 int resid, s; 250 251 if (datalen < ncr_sc->sc_min_dma_len || 252 (sc->sc_options & SBC_PDMA) == 0 || 253 (ncr_sc->sc_current != NULL && 254 (ncr_sc->sc_current->sr_xs->xs_control & XS_CTL_POLL))) 255 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 256 257 mutex_enter(&sc->sc_drq_lock); 258 s = splbio(); 259 if (sbc_wait_busy(ncr_sc)) { 260 splx(s); 261 mutex_exit(&sc->sc_drq_lock); 262 263 return 0; 264 } 265 266 *ncr_sc->sci_mode |= SCI_MODE_DMA; 267 *ncr_sc->sci_irecv = 0; 268 269 resid = datalen; 270 271 /* 272 * Setup for a possible bus error caused by SCSI controller 273 * switching out of DATA OUT before we're done with the 274 * current transfer. (See comment before sbc_drq_intr().) 275 */ 276 nofault = &faultbuf; 277 if (setjmp(nofault)) { 278 goto interrupt; 279 } 280 281 #define R4 *(u_int32_t *)data = *long_data, data += 4; 282 for (; resid >= 128; resid -= 128) { 283 if (sbc_ready(ncr_sc)) 284 goto interrupt; 285 R4; R4; R4; R4; R4; R4; R4; R4; 286 R4; R4; R4; R4; R4; R4; R4; R4; 287 R4; R4; R4; R4; R4; R4; R4; R4; 288 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 289 } 290 while (resid) { 291 if (sbc_ready(ncr_sc)) 292 goto interrupt; 293 *(u_int8_t *)data = *byte_data, data += 1; 294 resid--; 295 } 296 #undef R4 297 298 interrupt: 299 nofault = NULL; 300 SCI_CLR_INTR(ncr_sc); 301 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 302 *ncr_sc->sci_icmd = 0; 303 splx(s); 304 mutex_exit(&sc->sc_drq_lock); 305 306 return (datalen - resid); 307 } 308 309 int 310 sbc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, u_char *data) 311 { 312 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 313 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 314 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 315 label_t faultbuf; 316 int resid, s; 317 u_int8_t icmd; 318 319 #if 1 320 /* Work around lame gcc initialization bug */ 321 (void)&data; 322 #endif 323 324 if (datalen < ncr_sc->sc_min_dma_len || 325 (sc->sc_options & SBC_PDMA) == 0 || 326 (sc->sc_options & SBC_PDMA_NO_WRITE) || 327 (ncr_sc->sc_current != NULL && 328 (ncr_sc->sc_current->sr_xs->xs_control & XS_CTL_POLL))) 329 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 330 331 mutex_enter(&sc->sc_drq_lock); 332 s = splbio(); 333 if (sbc_wait_busy(ncr_sc)) { 334 splx(s); 335 mutex_exit(&sc->sc_drq_lock); 336 337 return 0; 338 } 339 340 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 341 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 342 *ncr_sc->sci_mode |= SCI_MODE_DMA; 343 *ncr_sc->sci_dma_send = 0; 344 345 /* 346 * Setup for a possible bus error caused by SCSI controller 347 * switching out of DATA OUT before we're done with the 348 * current transfer. (See comment before sbc_drq_intr().) 349 */ 350 nofault = &faultbuf; 351 352 if (setjmp(nofault)) { 353 printf("buf = 0x%lx, fault = 0x%lx\n", 354 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 355 panic("Unexpected bus error in sbc_pdma_out()"); 356 } 357 358 #define W1 *byte_data = *(u_int8_t *)data, data += 1 359 #define W4 *long_data = *(u_int32_t *)data, data += 4 360 for (resid = datalen; resid >= 64; resid -= 60) { 361 if (sbc_ready(ncr_sc)) 362 goto interrupt; 363 W1; 364 resid--; 365 if (sbc_ready(ncr_sc)) 366 goto interrupt; 367 W1; 368 resid--; 369 if (sbc_ready(ncr_sc)) 370 goto interrupt; 371 W1; 372 resid--; 373 if (sbc_ready(ncr_sc)) 374 goto interrupt; 375 W1; 376 resid--; 377 if (sbc_ready(ncr_sc)) 378 goto interrupt; 379 W4; W4; W4; W4; 380 W4; W4; W4; W4; 381 W4; W4; W4; W4; 382 W4; W4; W4; 383 } 384 while (resid) { 385 if (sbc_ready(ncr_sc)) 386 goto interrupt; 387 W1; 388 resid--; 389 } 390 #undef W1 391 #undef W4 392 if (sbc_wait_dreq(ncr_sc)) 393 printf("%s: timeout waiting for DREQ.\n", 394 device_xname(ncr_sc->sc_dev)); 395 396 *byte_data = 0; 397 goto done; 398 399 interrupt: 400 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 401 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 402 --resid; 403 } 404 405 done: 406 SCI_CLR_INTR(ncr_sc); 407 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 408 *ncr_sc->sci_icmd = icmd; 409 splx(s); 410 mutex_exit(&sc->sc_drq_lock); 411 412 return (datalen - resid); 413 } 414 415 416 /*** 417 * The following code implements interrupt-driven PDMA. 418 ***/ 419 420 /* 421 * This is the meat of the PDMA transfer. 422 * When we get here, we shove data as fast as the mac can take it. 423 * We depend on several things: 424 * * All macs after the Mac Plus that have a 5380 chip should have a general 425 * logic IC that handshakes data for blind transfers. 426 * * If the SCSI controller finishes sending/receiving data before we do, 427 * the same general logic IC will generate a /BERR for us in short order. 428 * * The fault address for said /BERR minus the base address for the 429 * transfer will be the amount of data that was actually written. 430 * 431 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 432 * detect and handle the bus error for early termination of a command. 433 * This is usually caused by a disconnecting target. 434 */ 435 void 436 sbc_drq_intr(void *p) 437 { 438 struct sbc_softc *sc = (struct sbc_softc *)p; 439 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 440 struct sci_req *sr = ncr_sc->sc_current; 441 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 442 label_t faultbuf; 443 volatile u_int32_t *long_drq; 444 u_int32_t *long_data; 445 volatile u_int8_t *drq = 0; /* XXX gcc4 -Wuninitialized */ 446 u_int8_t *data; 447 int count, dcount, s; 448 449 /* 450 * If we're not ready to xfer data, or have no more, just return. 451 */ 452 if (sbc_ready(ncr_sc) || dh->dh_len == 0) 453 return; 454 455 #ifdef SBC_DEBUG 456 if (sbc_debug & SBC_DB_INTR) 457 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 458 device_xname(ncr_sc->sc_dev), dh->dh_len, dh->dh_flags); 459 #endif 460 mutex_enter(&sc->sc_drq_lock); 461 s = splbio(); 462 463 /* 464 * Setup for a possible bus error caused by SCSI controller 465 * switching out of DATA-IN/OUT before we're done with the 466 * current transfer. 467 */ 468 nofault = &faultbuf; 469 470 m68k_fault_addr = 0; 471 if (setjmp(nofault)) { 472 nofault = (label_t *)0; 473 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 474 count = (( (u_long)m68k_fault_addr 475 - (u_long)sc->sc_drq_addr)); 476 477 if ((count < 0) || (count > dh->dh_len)) { 478 printf("%s: complete=0x%x (pending 0x%x)\n", 479 device_xname(ncr_sc->sc_dev), count, 480 dh->dh_len); 481 panic("something is wrong"); 482 } 483 484 dh->dh_addr += count; 485 dh->dh_len -= count; 486 } else 487 count = 0; 488 489 #ifdef SBC_DEBUG 490 if (sbc_debug & SBC_DB_INTR) 491 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 492 device_xname(ncr_sc->sc_dev), count, dh->dh_len); 493 #endif 494 m68k_fault_addr = 0; 495 496 splx(s); 497 498 mutex_exit(&sc->sc_drq_lock); 499 500 return; 501 } 502 503 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 504 dcount = 0; 505 506 /* 507 * Get the source address aligned. 508 */ 509 dcount = 510 count = uimin(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 511 if (count && count < 4) { 512 drq = (volatile u_int8_t *)sc->sc_drq_addr; 513 data = (u_int8_t *)dh->dh_addr; 514 515 #define W1 *drq++ = *data++ 516 while (count) { 517 W1; count--; 518 } 519 #undef W1 520 dh->dh_addr += dcount; 521 dh->dh_len -= dcount; 522 } 523 524 /* 525 * Start the transfer. 526 */ 527 while (dh->dh_len) { 528 #define W4 *long_drq++ = *long_data++; count -= 4 529 530 dcount = count = uimin(dh->dh_len, MAX_DMA_LEN); 531 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 532 long_data = (u_int32_t *)dh->dh_addr; 533 534 while (count >= 64) { 535 W4; W4; W4; W4; W4; W4; W4; W4; 536 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 537 } 538 while (count >= 4) { 539 W4; 540 } 541 #undef W4 542 data = (u_int8_t *)long_data; 543 drq = (volatile u_int8_t *)long_drq; 544 545 #define W1 *drq++ = *data++ 546 while (count) { 547 W1; count--; 548 } 549 #undef W1 550 dh->dh_len -= dcount; 551 dh->dh_addr += dcount; 552 } 553 dh->dh_flags |= SBC_DH_DONE; 554 if (dcount >= MAX_DMA_LEN) 555 drq = (volatile u_int8_t *)sc->sc_drq_addr; 556 /* 557 * Write an extra byte to handle last ack. 558 * From NCR5380 Interface manual. 559 */ 560 if (*ncr_sc->sci_csr & SCI_CSR_ACK) 561 *drq = 0; 562 563 /* 564 * XXX -- Read a byte from the SBC to trigger a /BERR. 565 * This seems to be necessary for us to notice that 566 * the target has disconnected. Ick. 06 jun 1996 (sr) 567 * Unsure if this is still necessary - See comment above. 568 */ 569 (void)*drq; 570 } else { /* Data In */ 571 /* 572 * Get the dest address aligned. 573 */ 574 dcount = 575 count = uimin(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 576 if (count && count < 4) { 577 data = (u_int8_t *)dh->dh_addr; 578 drq = (volatile u_int8_t *)sc->sc_drq_addr; 579 while (count) { 580 *data++ = *drq++; 581 count--; 582 } 583 dh->dh_addr += dcount; 584 dh->dh_len -= dcount; 585 } 586 587 /* 588 * Start the transfer. 589 */ 590 while (dh->dh_len) { 591 dcount = count = uimin(dh->dh_len, MAX_DMA_LEN); 592 long_data = (u_int32_t *)dh->dh_addr; 593 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 594 595 #define R4 *long_data++ = *long_drq++; count -= 4 596 while (count >= 64) { 597 R4; R4; R4; R4; R4; R4; R4; R4; 598 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 599 } 600 while (count >= 4) { 601 R4; 602 } 603 #undef R4 604 data = (u_int8_t *)long_data; 605 drq = (volatile u_int8_t *)long_drq; 606 while (count) { 607 *data++ = *drq++; 608 count--; 609 } 610 dh->dh_len -= dcount; 611 dh->dh_addr += dcount; 612 } 613 dh->dh_flags |= SBC_DH_DONE; 614 } 615 616 /* 617 * OK. No bus error occurred above. Clear the nofault flag 618 * so we no longer short-circuit bus errors. 619 */ 620 nofault = (label_t *)0; 621 622 splx(s); 623 624 mutex_exit(&sc->sc_drq_lock); 625 626 #ifdef SBC_DEBUG 627 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 628 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 629 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 630 *ncr_sc->sci_bus_csr); 631 #endif 632 } 633 634 void 635 sbc_dma_alloc(struct ncr5380_softc *ncr_sc) 636 { 637 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 638 struct sci_req *sr = ncr_sc->sc_current; 639 struct scsipi_xfer *xs = sr->sr_xs; 640 struct sbc_pdma_handle *dh; 641 int i, xlen; 642 643 #ifdef DIAGNOSTIC 644 if (sr->sr_dma_hand != NULL) 645 panic("sbc_dma_alloc: already have PDMA handle"); 646 #endif 647 648 /* Polled transfers shouldn't allocate a PDMA handle. */ 649 if (sr->sr_flags & SR_IMMED) 650 return; 651 652 xlen = ncr_sc->sc_datalen; 653 654 /* Make sure our caller checked sc_min_dma_len. */ 655 if (xlen < MIN_DMA_LEN) 656 panic("sbc_dma_alloc: len=0x%x", xlen); 657 658 /* 659 * Find free PDMA handle. Guaranteed to find one since we 660 * have as many PDMA handles as the driver has processes. 661 * (instances?) 662 */ 663 for (i = 0; i < SCI_OPENINGS; i++) { 664 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 665 goto found; 666 } 667 panic("sbc: no free PDMA handles"); 668 found: 669 dh = &sc->sc_pdma[i]; 670 dh->dh_flags = SBC_DH_BUSY; 671 dh->dh_addr = ncr_sc->sc_dataptr; 672 dh->dh_len = xlen; 673 674 /* Copy the 'write' flag for convenience. */ 675 if (xs->xs_control & XS_CTL_DATA_OUT) 676 dh->dh_flags |= SBC_DH_OUT; 677 678 sr->sr_dma_hand = dh; 679 } 680 681 void 682 sbc_dma_free(struct ncr5380_softc *ncr_sc) 683 { 684 struct sci_req *sr = ncr_sc->sc_current; 685 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 686 687 #ifdef DIAGNOSTIC 688 if (sr->sr_dma_hand == NULL) 689 panic("sbc_dma_free: no DMA handle"); 690 #endif 691 692 if (ncr_sc->sc_state & NCR_DOINGDMA) 693 panic("sbc_dma_free: free while in progress"); 694 695 if (dh->dh_flags & SBC_DH_BUSY) { 696 dh->dh_flags = 0; 697 dh->dh_addr = NULL; 698 dh->dh_len = 0; 699 } 700 sr->sr_dma_hand = NULL; 701 } 702 703 void 704 sbc_dma_poll(struct ncr5380_softc *ncr_sc) 705 { 706 struct sci_req *sr = ncr_sc->sc_current; 707 708 /* 709 * We shouldn't arrive here; if SR_IMMED is set, then 710 * dma_alloc() should have refused to allocate a handle 711 * for the transfer. This forces the polled PDMA code 712 * to handle the request... 713 */ 714 #ifdef SBC_DEBUG 715 if (sbc_debug & SBC_DB_DMA) 716 printf("%s: lost DRQ interrupt?\n", 717 device_xname(ncr_sc->sc_dev)); 718 #endif 719 sr->sr_flags |= SR_OVERDUE; 720 } 721 722 void 723 sbc_dma_setup(struct ncr5380_softc *ncr_sc) 724 { 725 /* Not needed; we don't have real DMA */ 726 } 727 728 void 729 sbc_dma_start(struct ncr5380_softc *ncr_sc) 730 { 731 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 732 struct sci_req *sr = ncr_sc->sc_current; 733 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 734 735 /* 736 * Match bus phase, clear pending interrupts, set DMA mode, and 737 * assert data bus (for writing only), then start the transfer. 738 */ 739 if (dh->dh_flags & SBC_DH_OUT) { 740 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 741 SCI_CLR_INTR(ncr_sc); 742 if (sc->sc_clrintr) 743 (*sc->sc_clrintr)(ncr_sc); 744 *ncr_sc->sci_mode |= SCI_MODE_DMA; 745 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 746 *ncr_sc->sci_dma_send = 0; 747 } else { 748 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 749 SCI_CLR_INTR(ncr_sc); 750 if (sc->sc_clrintr) 751 (*sc->sc_clrintr)(ncr_sc); 752 *ncr_sc->sci_mode |= SCI_MODE_DMA; 753 *ncr_sc->sci_icmd = 0; 754 *ncr_sc->sci_irecv = 0; 755 } 756 ncr_sc->sc_state |= NCR_DOINGDMA; 757 758 #ifdef SBC_DEBUG 759 if (sbc_debug & SBC_DB_DMA) 760 printf("%s: PDMA started, va=%p, len=0x%x\n", 761 device_xname(ncr_sc->sc_dev), dh->dh_addr, dh->dh_len); 762 #endif 763 } 764 765 void 766 sbc_dma_eop(struct ncr5380_softc *ncr_sc) 767 { 768 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 769 } 770 771 void 772 sbc_dma_stop(struct ncr5380_softc *ncr_sc) 773 { 774 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 775 struct sci_req *sr = ncr_sc->sc_current; 776 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 777 int ntrans; 778 779 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 780 #ifdef SBC_DEBUG 781 if (sbc_debug & SBC_DB_DMA) 782 printf("%s: dma_stop: DMA not running\n", 783 device_xname(ncr_sc->sc_dev)); 784 #endif 785 return; 786 } 787 ncr_sc->sc_state &= ~NCR_DOINGDMA; 788 789 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 790 ntrans = ncr_sc->sc_datalen - dh->dh_len; 791 792 #ifdef SBC_DEBUG 793 if (sbc_debug & SBC_DB_DMA) 794 printf("%s: dma_stop: ntrans=0x%x\n", 795 device_xname(ncr_sc->sc_dev), ntrans); 796 #endif 797 798 if (ntrans > ncr_sc->sc_datalen) 799 panic("sbc_dma_stop: excess transfer"); 800 801 /* Adjust data pointer */ 802 ncr_sc->sc_dataptr += ntrans; 803 ncr_sc->sc_datalen -= ntrans; 804 805 /* Clear any pending interrupts. */ 806 SCI_CLR_INTR(ncr_sc); 807 if (sc->sc_clrintr) 808 (*sc->sc_clrintr)(ncr_sc); 809 } 810 811 /* Put SBIC back into PIO mode. */ 812 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 813 *ncr_sc->sci_icmd = 0; 814 815 #ifdef SBC_DEBUG 816 if (sbc_debug & SBC_DB_REG) 817 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 818 device_xname(ncr_sc->sc_dev), *ncr_sc->sci_csr, 819 *ncr_sc->sci_bus_csr); 820 #endif 821 } 822
Indexes created Mon Sep 22 10:09:38 GMT 2025