sbc.c revision 1.8
1 /* $NetBSD: sbc.c,v 1.8 1996/06/11 03:20:23 scottr Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott Reynolds 5 * Copyright (c) 1995 Allen Briggs 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the authors may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 4. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Allen Briggs and 21 * Scott Reynolds. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * This file contains only the machine-dependent parts of the mac68k 37 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 38 * The machine-independent parts are in ncr5380sbc.c 39 * 40 * Supported hardware includes: 41 * Macintosh II family 5380-based controller 42 * 43 * Credits, history: 44 * 45 * Scott Reynolds wrote this module, based on work by Allen Briggs 46 * (mac68k), David Jones (sun3), and Leo Weppelman (atari). Allen 47 * supplied some crucial interpretation of the NetBSD 1.1 'ncrscsi' 48 * driver. Allen, Gordon W. Ross, and Jason Thorpe all helped to 49 * refine this code, and were considerable sources of moral support. 50 * 51 * The sbc_options code is based on similar code in Jason's modified 52 * NetBSD/sparc 'si' driver. 53 */ 54 55 #include <sys/types.h> 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/errno.h> 60 #include <sys/device.h> 61 #include <sys/buf.h> 62 #include <sys/proc.h> 63 #include <sys/user.h> 64 65 #include <scsi/scsi_all.h> 66 #include <scsi/scsi_debug.h> 67 #include <scsi/scsiconf.h> 68 69 #include <dev/ic/ncr5380reg.h> 70 #include <dev/ic/ncr5380var.h> 71 72 #include <machine/cpu.h> 73 #include <machine/viareg.h> 74 75 #include "sbcreg.h" 76 77 /* 78 * Transfers smaller than this are done using PIO 79 * (on assumption they're not worth PDMA overhead) 80 */ 81 #define MIN_DMA_LEN 128 82 83 /* 84 * Transfers larger than 8192 bytes need to be split up 85 * due to the size of the PDMA space. 86 */ 87 #define MAX_DMA_LEN 0x2000 88 89 /* 90 * From Guide to the Macintosh Family Hardware, pp. 137-143 91 * These are offsets from SCSIBase (see pmap_bootstrap.c) 92 */ 93 #define SBC_REG_OFS 0x10000 94 #define SBC_HSK_OFS 0x06000 95 #define SBC_DMA_OFS 0x12000 96 97 #define SBC_DMA_OFS_PB500 0x06000 98 99 #define SBC_REG_OFS_IIFX 0x08000 /* Just guessing... */ 100 #define SBC_HSK_OFS_IIFX 0x0e000 101 #define SBC_DMA_OFS_IIFX 0x0c000 102 103 #ifdef SBC_DEBUG 104 # define SBC_DB_INTR 0x01 105 # define SBC_DB_DMA 0x02 106 # define SBC_DB_REG 0x04 107 # define SBC_DB_BREAK 0x08 108 109 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 110 int sbc_link_flags = 0 /* | SDEV_DB2 */; 111 112 # ifndef DDB 113 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 114 # endif 115 # define SBC_BREAK \ 116 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 117 #else 118 # define SBC_BREAK 119 #endif 120 121 /* 122 * This structure is used to keep track of PDMA requests. 123 */ 124 struct sbc_pdma_handle { 125 int dh_flags; /* flags */ 126 #define SBC_DH_BUSY 0x01 /* This handle is in use */ 127 #define SBC_DH_OUT 0x02 /* PDMA data out (write) */ 128 #define SBC_DH_DONE 0x04 /* PDMA transfer is complete */ 129 u_char *dh_addr; /* data buffer */ 130 int dh_len; /* length of data buffer */ 131 }; 132 133 /* 134 * The first structure member has to be the ncr5380_softc 135 * so we can just cast to go back and forth between them. 136 */ 137 struct sbc_softc { 138 struct ncr5380_softc ncr_sc; 139 volatile struct sbc_regs *sc_regs; 140 volatile vm_offset_t sc_drq_addr; 141 volatile vm_offset_t sc_nodrq_addr; 142 volatile u_int8_t *sc_ienable; 143 volatile u_int8_t *sc_iflag; 144 int sc_options; /* options for this instance. */ 145 struct sbc_pdma_handle sc_pdma[SCI_OPENINGS]; 146 }; 147 148 /* 149 * Options. By default, SCSI interrupts and reselect are disabled. 150 * You may enable either of these features with the `flags' directive 151 * in your kernel's configuration file. 152 * 153 * Alternatively, you can patch your kernel with DDB or some other 154 * mechanism. The sc_options member of the softc is OR'd with 155 * the value in sbc_options. 156 */ 157 #define SBC_PDMA 0x01 /* Use PDMA for polled transfers */ 158 #define SBC_INTR 0x02 /* Allow SCSI IRQ/DRQ interrupts */ 159 #define SBC_RESELECT 0x04 /* Allow disconnect/reselect */ 160 #define SBC_OPTIONS_MASK (SBC_RESELECT|SBC_INTR|SBC_PDMA) 161 #define SBC_OPTIONS_BITS "\10\3RESELECT\2INTR\1PDMA" 162 int sbc_options = SBC_PDMA; 163 164 static int sbc_match __P((struct device *, void *, void *)); 165 static void sbc_attach __P((struct device *, struct device *, void *)); 166 static int sbc_print __P((void *, char *)); 167 static void sbc_minphys __P((struct buf *bp)); 168 169 static int sbc_wait_busy __P((struct ncr5380_softc *)); 170 static int sbc_ready __P((struct ncr5380_softc *)); 171 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 172 static int sbc_pdma_in __P((struct ncr5380_softc *, int, int, u_char *)); 173 static int sbc_pdma_out __P((struct ncr5380_softc *, int, int, u_char *)); 174 #ifdef SBC_DEBUG 175 static void decode_5380_intr __P((struct ncr5380_softc *)); 176 #endif 177 178 void sbc_intr_enable __P((struct ncr5380_softc *)); 179 void sbc_intr_disable __P((struct ncr5380_softc *)); 180 void sbc_irq_intr __P((void *)); 181 void sbc_drq_intr __P((void *)); 182 void sbc_dma_alloc __P((struct ncr5380_softc *)); 183 void sbc_dma_free __P((struct ncr5380_softc *)); 184 void sbc_dma_poll __P((struct ncr5380_softc *)); 185 void sbc_dma_setup __P((struct ncr5380_softc *)); 186 void sbc_dma_start __P((struct ncr5380_softc *)); 187 void sbc_dma_eop __P((struct ncr5380_softc *)); 188 void sbc_dma_stop __P((struct ncr5380_softc *)); 189 190 static struct scsi_adapter sbc_ops = { 191 ncr5380_scsi_cmd, /* scsi_cmd() */ 192 sbc_minphys, /* scsi_minphys() */ 193 NULL, /* open_target_lu() */ 194 NULL, /* close_target_lu() */ 195 }; 196 197 /* This is copied from julian's bt driver */ 198 /* "so we have a default dev struct for our link struct." */ 199 static struct scsi_device sbc_dev = { 200 NULL, /* Use default error handler. */ 201 NULL, /* Use default start handler. */ 202 NULL, /* Use default async handler. */ 203 NULL, /* Use default "done" routine. */ 204 }; 205 206 struct cfattach sbc_ca = { 207 sizeof(struct sbc_softc), sbc_match, sbc_attach 208 }; 209 210 struct cfdriver sbc_cd = { 211 NULL, "sbc", DV_DULL 212 }; 213 214 215 static int 216 sbc_match(parent, match, args) 217 struct device *parent; 218 void *match, *args; 219 { 220 if (!mac68k_machine.scsi80) 221 return 0; 222 return 1; 223 } 224 225 static void 226 sbc_attach(parent, self, args) 227 struct device *parent, *self; 228 void *args; 229 { 230 struct sbc_softc *sc = (struct sbc_softc *) self; 231 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) sc; 232 extern vm_offset_t SCSIBase; 233 234 /* Pull in the options flags. */ 235 sc->sc_options = ((ncr_sc->sc_dev.dv_cfdata->cf_flags | sbc_options) 236 & SBC_OPTIONS_MASK); 237 238 /* 239 * Set up offsets to 5380 registers and GLUE I/O space, and turn 240 * off options we know we can't support on certain models. 241 */ 242 switch (current_mac_model->machineid) { 243 case MACH_MACIIFX: /* Note: the IIfx isn't (yet) supported. */ 244 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS_IIFX); 245 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS_IIFX); 246 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_IIFX); 247 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 248 break; 249 case MACH_MACPB500: 250 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 251 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); /*??*/ 252 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_PB500); 253 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 254 break; 255 default: 256 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 257 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); 258 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS); 259 break; 260 } 261 262 /* 263 * Fill in the prototype scsi_link. 264 */ 265 ncr_sc->sc_link.adapter_softc = sc; 266 ncr_sc->sc_link.adapter_target = 7; 267 ncr_sc->sc_link.adapter = &sbc_ops; 268 ncr_sc->sc_link.device = &sbc_dev; 269 270 /* 271 * Initialize fields used by the MI code 272 */ 273 ncr_sc->sci_r0 = &sc->sc_regs->sci_pr0.sci_reg; 274 ncr_sc->sci_r1 = &sc->sc_regs->sci_pr1.sci_reg; 275 ncr_sc->sci_r2 = &sc->sc_regs->sci_pr2.sci_reg; 276 ncr_sc->sci_r3 = &sc->sc_regs->sci_pr3.sci_reg; 277 ncr_sc->sci_r4 = &sc->sc_regs->sci_pr4.sci_reg; 278 ncr_sc->sci_r5 = &sc->sc_regs->sci_pr5.sci_reg; 279 ncr_sc->sci_r6 = &sc->sc_regs->sci_pr6.sci_reg; 280 ncr_sc->sci_r7 = &sc->sc_regs->sci_pr7.sci_reg; 281 282 /* 283 * MD function pointers used by the MI code. 284 */ 285 if (sc->sc_options & SBC_PDMA) { 286 ncr_sc->sc_pio_out = sbc_pdma_out; 287 ncr_sc->sc_pio_in = sbc_pdma_in; 288 } else { 289 ncr_sc->sc_pio_out = ncr5380_pio_out; 290 ncr_sc->sc_pio_in = ncr5380_pio_in; 291 } 292 ncr_sc->sc_dma_alloc = NULL; 293 ncr_sc->sc_dma_free = NULL; 294 ncr_sc->sc_dma_poll = NULL; 295 ncr_sc->sc_intr_on = NULL; 296 ncr_sc->sc_intr_off = NULL; 297 ncr_sc->sc_dma_setup = NULL; 298 ncr_sc->sc_dma_start = NULL; 299 ncr_sc->sc_dma_eop = NULL; 300 ncr_sc->sc_dma_stop = NULL; 301 ncr_sc->sc_flags = 0; 302 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 303 304 if (sc->sc_options & SBC_INTR) { 305 if (sc->sc_options & SBC_RESELECT) 306 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 307 ncr_sc->sc_dma_alloc = sbc_dma_alloc; 308 ncr_sc->sc_dma_free = sbc_dma_free; 309 ncr_sc->sc_dma_poll = sbc_dma_poll; 310 ncr_sc->sc_dma_setup = sbc_dma_setup; 311 ncr_sc->sc_dma_start = sbc_dma_start; 312 ncr_sc->sc_dma_eop = sbc_dma_eop; 313 ncr_sc->sc_dma_stop = sbc_dma_stop; 314 mac68k_register_scsi_drq(sbc_drq_intr, ncr_sc); 315 mac68k_register_scsi_irq(sbc_irq_intr, ncr_sc); 316 } else 317 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 318 319 /* 320 * Initialize fields used only here in the MD code. 321 */ 322 if (VIA2 == VIA2OFF) { 323 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + vIER; 324 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + vIFR; 325 } else { 326 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + rIER; 327 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + rIFR; 328 } 329 330 if (sc->sc_options) 331 printf(": options=%b", sc->sc_options, SBC_OPTIONS_BITS); 332 printf("\n"); 333 334 /* Now enable SCSI interrupts through VIA2, if appropriate */ 335 if (sc->sc_options & SBC_INTR) 336 sbc_intr_enable(ncr_sc); 337 338 #ifdef SBC_DEBUG 339 if (sbc_debug) 340 printf("%s: softc=%p regs=%p\n", ncr_sc->sc_dev.dv_xname, 341 sc, sc->sc_regs); 342 ncr_sc->sc_link.flags |= sbc_link_flags; 343 #endif 344 345 /* 346 * Initialize the SCSI controller itself. 347 */ 348 ncr5380_init(ncr_sc); 349 ncr5380_reset_scsibus(ncr_sc); 350 config_found(self, &(ncr_sc->sc_link), sbc_print); 351 } 352 353 static int 354 sbc_print(aux, name) 355 void *aux; 356 char *name; 357 { 358 if (name != NULL) 359 printf("%s: scsibus ", name); 360 return UNCONF; 361 } 362 363 static void 364 sbc_minphys(struct buf *bp) 365 { 366 if (bp->b_bcount > MAX_DMA_LEN) 367 bp->b_bcount = MAX_DMA_LEN; 368 return (minphys(bp)); 369 } 370 371 372 /*** 373 * General support for Mac-specific SCSI logic. 374 ***/ 375 376 /* These are used in the following inline functions. */ 377 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 378 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 379 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 380 381 /* Return zero on success. */ 382 static __inline__ int 383 sbc_wait_busy(sc) 384 struct ncr5380_softc *sc; 385 { 386 register int timo = sbc_wait_busy_timo; 387 for (;;) { 388 if (SCI_BUSY(sc)) { 389 timo = 0; /* return 0 */ 390 break; 391 } 392 if (--timo < 0) 393 break; /* return -1 */ 394 delay(2); 395 } 396 return (timo); 397 } 398 399 static __inline__ int 400 sbc_ready(sc) 401 struct ncr5380_softc *sc; 402 { 403 register int timo = sbc_ready_timo; 404 405 for (;;) { 406 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 407 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 408 timo = 0; 409 break; 410 } 411 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 412 || (SCI_BUSY(sc) == 0)) { 413 timo = -1; 414 break; 415 } 416 if (--timo < 0) 417 break; /* return -1 */ 418 delay(2); 419 } 420 return (timo); 421 } 422 423 static __inline__ int 424 sbc_wait_dreq(sc) 425 struct ncr5380_softc *sc; 426 { 427 register int timo = sbc_wait_dreq_timo; 428 429 for (;;) { 430 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 431 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 432 timo = 0; 433 break; 434 } 435 if (--timo < 0) 436 break; /* return -1 */ 437 delay(2); 438 } 439 return (timo); 440 } 441 442 443 /*** 444 * Macintosh SCSI interrupt support routines. 445 ***/ 446 447 void 448 sbc_intr_enable(ncr_sc) 449 struct ncr5380_softc *ncr_sc; 450 { 451 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 452 int s; 453 454 s = splhigh(); 455 *sc->sc_ienable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 456 splx(s); 457 } 458 459 void 460 sbc_intr_disable(ncr_sc) 461 struct ncr5380_softc *ncr_sc; 462 { 463 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 464 int s; 465 466 s = splhigh(); 467 *sc->sc_ienable = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 468 splx(s); 469 } 470 471 void 472 sbc_irq_intr(p) 473 void *p; 474 { 475 register struct ncr5380_softc *ncr_sc = p; 476 register int claimed = 0; 477 478 /* How we ever arrive here without IRQ set is a mystery... */ 479 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 480 #ifdef SBC_DEBUG 481 if (sbc_debug & SBC_DB_INTR) 482 decode_5380_intr(ncr_sc); 483 #endif 484 claimed = ncr5380_intr(ncr_sc); 485 if (!claimed) { 486 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 487 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 488 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 489 #ifdef SBC_DEBUG 490 else { 491 printf("%s: spurious intr\n", 492 ncr_sc->sc_dev.dv_xname); 493 SBC_BREAK; 494 } 495 #endif 496 } 497 } 498 } 499 500 #ifdef SBC_DEBUG 501 void 502 decode_5380_intr(ncr_sc) 503 struct ncr5380_softc *ncr_sc; 504 { 505 register u_char csr = *ncr_sc->sci_csr; 506 register u_char bus_csr = *ncr_sc->sci_bus_csr; 507 508 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 509 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 510 if (csr & SCI_BUS_IO) 511 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 512 else 513 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 514 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 515 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 516 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 517 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 518 ((bus_csr & ~SCI_BUS_RST) == 0)) 519 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 520 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 521 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 522 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 523 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 524 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 525 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 526 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 527 (bus_csr == 0)) 528 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 529 else 530 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 531 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 532 } 533 #endif 534 535 536 /*** 537 * The following code implements polled PDMA. 538 ***/ 539 540 static int 541 sbc_pdma_out(ncr_sc, phase, count, data) 542 struct ncr5380_softc *ncr_sc; 543 int phase; 544 int count; 545 u_char *data; 546 { 547 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 548 register volatile long *long_data = (long *) sc->sc_drq_addr; 549 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 550 register int len = count; 551 552 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 553 return ncr5380_pio_out(ncr_sc, phase, count, data); 554 555 if (sbc_wait_busy(ncr_sc) == 0) { 556 *ncr_sc->sci_mode |= SCI_MODE_DMA; 557 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 558 *ncr_sc->sci_dma_send = 0; 559 560 #define W1 *byte_data = *data++ 561 #define W4 *long_data = *((long*)data)++ 562 while (len >= 64) { 563 if (sbc_ready(ncr_sc)) 564 goto timeout; 565 W1; 566 if (sbc_ready(ncr_sc)) 567 goto timeout; 568 W1; 569 if (sbc_ready(ncr_sc)) 570 goto timeout; 571 W1; 572 if (sbc_ready(ncr_sc)) 573 goto timeout; 574 W1; 575 if (sbc_ready(ncr_sc)) 576 goto timeout; 577 W4; W4; W4; W4; 578 W4; W4; W4; W4; 579 W4; W4; W4; W4; 580 W4; W4; W4; 581 len -= 64; 582 } 583 while (len) { 584 if (sbc_ready(ncr_sc)) 585 goto timeout; 586 W1; 587 len--; 588 } 589 #undef W1 590 #undef W4 591 if (sbc_wait_dreq(ncr_sc)) 592 printf("%s: timeout waiting for DREQ.\n", 593 ncr_sc->sc_dev.dv_xname); 594 595 *byte_data = 0; 596 597 SCI_CLR_INTR(ncr_sc); 598 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 599 *ncr_sc->sci_icmd = 0; 600 } 601 return count - len; 602 603 timeout: 604 printf("%s: pdma_out: timeout len=%d count=%d\n", 605 ncr_sc->sc_dev.dv_xname, len, count); 606 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 607 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 608 --len; 609 } 610 611 SCI_CLR_INTR(ncr_sc); 612 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 613 *ncr_sc->sci_icmd = 0; 614 return count - len; 615 } 616 617 static int 618 sbc_pdma_in(ncr_sc, phase, count, data) 619 struct ncr5380_softc *ncr_sc; 620 int phase; 621 int count; 622 u_char *data; 623 { 624 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 625 register volatile long *long_data = (long *) sc->sc_drq_addr; 626 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 627 register int len = count; 628 629 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 630 return ncr5380_pio_in(ncr_sc, phase, count, data); 631 632 if (sbc_wait_busy(ncr_sc) == 0) { 633 *ncr_sc->sci_mode |= SCI_MODE_DMA; 634 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 635 *ncr_sc->sci_irecv = 0; 636 637 #define R4 *((long *)data)++ = *long_data 638 #define R1 *data++ = *byte_data 639 while (len >= 1024) { 640 if (sbc_ready(ncr_sc)) 641 goto timeout; 642 R4; R4; R4; R4; R4; R4; R4; R4; 643 R4; R4; R4; R4; R4; R4; R4; R4; 644 R4; R4; R4; R4; R4; R4; R4; R4; 645 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 646 if (sbc_ready(ncr_sc)) 647 goto timeout; 648 R4; R4; R4; R4; R4; R4; R4; R4; 649 R4; R4; R4; R4; R4; R4; R4; R4; 650 R4; R4; R4; R4; R4; R4; R4; R4; 651 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 652 if (sbc_ready(ncr_sc)) 653 goto timeout; 654 R4; R4; R4; R4; R4; R4; R4; R4; 655 R4; R4; R4; R4; R4; R4; R4; R4; 656 R4; R4; R4; R4; R4; R4; R4; R4; 657 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 658 if (sbc_ready(ncr_sc)) 659 goto timeout; 660 R4; R4; R4; R4; R4; R4; R4; R4; 661 R4; R4; R4; R4; R4; R4; R4; R4; 662 R4; R4; R4; R4; R4; R4; R4; R4; 663 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 664 if (sbc_ready(ncr_sc)) 665 goto timeout; 666 R4; R4; R4; R4; R4; R4; R4; R4; 667 R4; R4; R4; R4; R4; R4; R4; R4; 668 R4; R4; R4; R4; R4; R4; R4; R4; 669 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 670 if (sbc_ready(ncr_sc)) 671 goto timeout; 672 R4; R4; R4; R4; R4; R4; R4; R4; 673 R4; R4; R4; R4; R4; R4; R4; R4; 674 R4; R4; R4; R4; R4; R4; R4; R4; 675 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 676 if (sbc_ready(ncr_sc)) 677 goto timeout; 678 R4; R4; R4; R4; R4; R4; R4; R4; 679 R4; R4; R4; R4; R4; R4; R4; R4; 680 R4; R4; R4; R4; R4; R4; R4; R4; 681 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 682 if (sbc_ready(ncr_sc)) 683 goto timeout; 684 R4; R4; R4; R4; R4; R4; R4; R4; 685 R4; R4; R4; R4; R4; R4; R4; R4; 686 R4; R4; R4; R4; R4; R4; R4; R4; 687 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 688 len -= 1024; 689 } 690 while (len >= 128) { 691 if (sbc_ready(ncr_sc)) 692 goto timeout; 693 R4; R4; R4; R4; R4; R4; R4; R4; 694 R4; R4; R4; R4; R4; R4; R4; R4; 695 R4; R4; R4; R4; R4; R4; R4; R4; 696 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 697 len -= 128; 698 } 699 while (len) { 700 if (sbc_ready(ncr_sc)) 701 goto timeout; 702 R1; 703 len--; 704 } 705 #undef R4 706 #undef R1 707 SCI_CLR_INTR(ncr_sc); 708 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 709 *ncr_sc->sci_icmd = 0; 710 } 711 return count - len; 712 713 timeout: 714 printf("%s: pdma_in: timeout len=%d count=%d\n", 715 ncr_sc->sc_dev.dv_xname, len, count); 716 717 SCI_CLR_INTR(ncr_sc); 718 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 719 *ncr_sc->sci_icmd = 0; 720 return count - len; 721 } 722 723 724 /*** 725 * The following code implements interrupt-driven PDMA. 726 ***/ 727 728 /* 729 * This is the meat of the PDMA transfer. 730 * When we get here, we shove data as fast as the mac can take it. 731 * We depend on several things: 732 * * All macs after the Mac Plus that have a 5380 chip should have a general 733 * logic IC that handshakes data for blind transfers. 734 * * If the SCSI controller finishes sending/receiving data before we do, 735 * the same general logic IC will generate a /BERR for us in short order. 736 * * The fault address for said /BERR minus the base address for the 737 * transfer will be the amount of data that was actually written. 738 * 739 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 740 * detect and handle the bus error for early termination of a command. 741 * This is usually caused by a disconnecting target. 742 */ 743 void 744 sbc_drq_intr(p) 745 void *p; 746 { 747 extern int *nofault, mac68k_buserr_addr; 748 register struct sbc_softc *sc = (struct sbc_softc *) p; 749 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 750 register struct sci_req *sr = ncr_sc->sc_current; 751 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 752 label_t faultbuf; 753 volatile u_int32_t *long_drq; 754 u_int32_t *long_data; 755 volatile u_int8_t *drq; 756 u_int8_t *data; 757 register int count; 758 int dcount, resid; 759 u_int8_t tmp; 760 761 /* 762 * If we're not ready to xfer data, or have no more, just return. 763 */ 764 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 765 return; 766 767 #ifdef SBC_DEBUG 768 if (sbc_debug & SBC_DB_INTR) 769 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 770 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 771 #endif 772 773 /* 774 * Setup for a possible bus error caused by SCSI controller 775 * switching out of DATA-IN/OUT before we're done with the 776 * current transfer. 777 */ 778 nofault = (int *) &faultbuf; 779 780 if (setjmp((label_t *) nofault)) { 781 nofault = (int *) 0; 782 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 783 count = (( (u_long) mac68k_buserr_addr 784 - (u_long) sc->sc_drq_addr)); 785 786 if ((count < 0) || (count > dh->dh_len)) { 787 printf("%s: complete=0x%x (pending 0x%x)\n", 788 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 789 panic("something is wrong"); 790 } 791 792 dh->dh_addr += count; 793 dh->dh_len -= count; 794 } 795 796 #ifdef SBC_DEBUG 797 if (sbc_debug & SBC_DB_INTR) 798 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 799 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 800 #endif 801 mac68k_buserr_addr = 0; 802 803 return; 804 } 805 806 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 807 #if notyet /* XXX */ 808 /* 809 * Get the source address aligned. 810 */ 811 resid = 812 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 813 if (count && count < 4) { 814 drq = (volatile u_int8_t *) sc->sc_drq_addr; 815 data = (u_int8_t *) dh->dh_addr; 816 817 #define W1 *drq++ = *data++ 818 while (count) { 819 W1; count--; 820 } 821 #undef W1 822 dh->dh_addr += resid; 823 dh->dh_len -= resid; 824 } 825 826 /* 827 * Start the transfer. 828 */ 829 while (dh->dh_len) { 830 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 831 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 832 long_data = (u_int32_t *) dh->dh_addr; 833 834 #define W4 *long_drq++ = *long_data++ 835 while (count >= 64) { 836 W4; W4; W4; W4; W4; W4; W4; W4; 837 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 838 count -= 64; 839 } 840 while (count >= 4) { 841 W4; count -= 4; 842 } 843 #undef W4 844 data = (u_int8_t *) long_data; 845 drq = (u_int8_t *) long_drq; 846 #else /* notyet */ 847 /* 848 * Start the transfer. 849 */ 850 while (dh->dh_len) { 851 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 852 drq = (volatile u_int8_t *) sc->sc_drq_addr; 853 data = (u_int8_t *) dh->dh_addr; 854 #endif /* notyet */ 855 856 #define W1 *drq++ = *data++ 857 while (count) { 858 W1; count--; 859 } 860 #undef W1 861 dh->dh_len -= dcount; 862 dh->dh_addr += dcount; 863 } 864 dh->dh_flags |= SBC_DH_DONE; 865 866 /* 867 * XXX -- Read a byte from the SBC to trigger a /BERR. 868 * This seems to be necessary for us to notice that 869 * the target has disconnected. Ick. 06 jun 1996 (sr) 870 */ 871 if (dcount >= MAX_DMA_LEN) { 872 #if 0 873 while ((*ncr_sc->sci_csr & SCI_CSR_ACK) == 0) 874 ; 875 #endif 876 drq = (volatile u_int8_t *) sc->sc_drq_addr; 877 } 878 tmp = *drq; 879 } else { /* Data In */ 880 /* 881 * Get the dest address aligned. 882 */ 883 resid = 884 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 885 if (count && count < 4) { 886 data = (u_int8_t *) dh->dh_addr; 887 drq = (volatile u_int8_t *) sc->sc_drq_addr; 888 889 #define R1 *data++ = *drq++ 890 while (count) { 891 R1; count--; 892 } 893 #undef R1 894 dh->dh_addr += resid; 895 dh->dh_len -= resid; 896 } 897 898 /* 899 * Start the transfer. 900 */ 901 while (dh->dh_len) { 902 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 903 long_data = (u_int32_t *) dh->dh_addr; 904 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 905 906 #define R4 *long_data++ = *long_drq++ 907 while (count >= 64) { 908 R4; R4; R4; R4; R4; R4; R4; R4; 909 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 910 count -= 64; 911 } 912 while (count >= 4) { 913 R4; count -= 4; 914 } 915 #undef R4 916 data = (u_int8_t *) long_data; 917 drq = (volatile u_int8_t *) long_drq; 918 919 #define R1 *data++ = *drq++ 920 while (count) { 921 R1; count--; 922 } 923 #undef R1 924 dh->dh_len -= dcount; 925 dh->dh_addr += dcount; 926 } 927 dh->dh_flags |= SBC_DH_DONE; 928 } 929 930 /* 931 * OK. No bus error occurred above. Clear the nofault flag 932 * so we no longer short-circuit bus errors. 933 */ 934 nofault = (int *) 0; 935 936 #ifdef SBC_DEBUG 937 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 938 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 939 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 940 *ncr_sc->sci_bus_csr); 941 #endif 942 } 943 944 void 945 sbc_dma_alloc(ncr_sc) 946 struct ncr5380_softc *ncr_sc; 947 { 948 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 949 struct sci_req *sr = ncr_sc->sc_current; 950 struct scsi_xfer *xs = sr->sr_xs; 951 struct sbc_pdma_handle *dh; 952 int i, xlen; 953 954 #ifdef DIAGNOSTIC 955 if (sr->sr_dma_hand != NULL) 956 panic("sbc_dma_alloc: already have PDMA handle"); 957 #endif 958 959 /* Polled transfers shouldn't allocate a PDMA handle. */ 960 if (sr->sr_flags & SR_IMMED) 961 return; 962 963 xlen = ncr_sc->sc_datalen; 964 965 /* Make sure our caller checked sc_min_dma_len. */ 966 if (xlen < MIN_DMA_LEN) 967 panic("sbc_dma_alloc: len=0x%x\n", xlen); 968 969 /* 970 * Find free PDMA handle. Guaranteed to find one since we 971 * have as many PDMA handles as the driver has processes. 972 * (instances?) 973 */ 974 for (i = 0; i < SCI_OPENINGS; i++) { 975 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 976 goto found; 977 } 978 panic("sbc: no free PDMA handles"); 979 found: 980 dh = &sc->sc_pdma[i]; 981 dh->dh_flags = SBC_DH_BUSY; 982 dh->dh_addr = ncr_sc->sc_dataptr; 983 dh->dh_len = xlen; 984 985 /* Copy the 'write' flag for convenience. */ 986 if (xs->flags & SCSI_DATA_OUT) 987 dh->dh_flags |= SBC_DH_OUT; 988 989 sr->sr_dma_hand = dh; 990 } 991 992 void 993 sbc_dma_free(ncr_sc) 994 struct ncr5380_softc *ncr_sc; 995 { 996 struct sci_req *sr = ncr_sc->sc_current; 997 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 998 999 #ifdef DIAGNOSTIC 1000 if (sr->sr_dma_hand == NULL) 1001 panic("sbc_dma_free: no DMA handle"); 1002 #endif 1003 1004 if (ncr_sc->sc_state & NCR_DOINGDMA) 1005 panic("sbc_dma_free: free while in progress"); 1006 1007 if (dh->dh_flags & SBC_DH_BUSY) { 1008 dh->dh_flags = 0; 1009 dh->dh_addr = NULL; 1010 dh->dh_len = 0; 1011 } 1012 sr->sr_dma_hand = NULL; 1013 } 1014 1015 void 1016 sbc_dma_poll(ncr_sc) 1017 struct ncr5380_softc *ncr_sc; 1018 { 1019 struct sci_req *sr = ncr_sc->sc_current; 1020 1021 /* 1022 * We shouldn't arrive here; if SR_IMMED is set, then 1023 * dma_alloc() should have refused to allocate a handle 1024 * for the transfer. This forces the polled PDMA code 1025 * to handle the request... 1026 */ 1027 #ifdef SBC_DEBUG 1028 if (sbc_debug & SBC_DB_DMA) 1029 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 1030 #endif 1031 sr->sr_flags |= SR_OVERDUE; 1032 } 1033 1034 void 1035 sbc_dma_setup(ncr_sc) 1036 struct ncr5380_softc *ncr_sc; 1037 { 1038 /* Not needed; we don't have real DMA */ 1039 } 1040 1041 void 1042 sbc_dma_start(ncr_sc) 1043 struct ncr5380_softc *ncr_sc; 1044 { 1045 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1046 struct sci_req *sr = ncr_sc->sc_current; 1047 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1048 1049 /* 1050 * Match bus phase, clear pending interrupts, set DMA mode, and 1051 * assert data bus (for writing only), then start the transfer. 1052 */ 1053 if (dh->dh_flags & SBC_DH_OUT) { 1054 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 1055 SCI_CLR_INTR(ncr_sc); 1056 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1057 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1058 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 1059 *ncr_sc->sci_dma_send = 0; 1060 } else { 1061 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 1062 SCI_CLR_INTR(ncr_sc); 1063 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1064 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1065 *ncr_sc->sci_icmd = 0; 1066 *ncr_sc->sci_irecv = 0; 1067 } 1068 ncr_sc->sc_state |= NCR_DOINGDMA; 1069 1070 #ifdef SBC_DEBUG 1071 if (sbc_debug & SBC_DB_DMA) 1072 printf("%s: PDMA started, va=%p, len=0x%x\n", 1073 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 1074 #endif 1075 } 1076 1077 void 1078 sbc_dma_eop(ncr_sc) 1079 struct ncr5380_softc *ncr_sc; 1080 { 1081 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 1082 } 1083 1084 void 1085 sbc_dma_stop(ncr_sc) 1086 struct ncr5380_softc *ncr_sc; 1087 { 1088 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1089 struct sci_req *sr = ncr_sc->sc_current; 1090 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1091 register int ntrans; 1092 1093 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 1094 #ifdef SBC_DEBUG 1095 if (sbc_debug & SBC_DB_DMA) 1096 printf("%s: dma_stop: DMA not running\n", 1097 ncr_sc->sc_dev.dv_xname); 1098 #endif 1099 return; 1100 } 1101 ncr_sc->sc_state &= ~NCR_DOINGDMA; 1102 1103 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 1104 ntrans = ncr_sc->sc_datalen - dh->dh_len; 1105 1106 #ifdef SBC_DEBUG 1107 if (sbc_debug & SBC_DB_DMA) 1108 printf("%s: dma_stop: ntrans=0x%x\n", 1109 ncr_sc->sc_dev.dv_xname, ntrans); 1110 #endif 1111 1112 if (ntrans > ncr_sc->sc_datalen) 1113 panic("sbc_dma_stop: excess transfer\n"); 1114 1115 /* Adjust data pointer */ 1116 ncr_sc->sc_dataptr += ntrans; 1117 ncr_sc->sc_datalen -= ntrans; 1118 1119 /* Clear any pending interrupts. */ 1120 SCI_CLR_INTR(ncr_sc); 1121 *sc->sc_iflag = 0x80 | V2IF_SCSIIRQ; 1122 } 1123 1124 /* Put SBIC back into PIO mode. */ 1125 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 1126 *ncr_sc->sci_icmd = 0; 1127 1128 #ifdef SBC_DEBUG 1129 if (sbc_debug & SBC_DB_REG) 1130 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 1131 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 1132 *ncr_sc->sci_bus_csr); 1133 #endif 1134 } 1135
Indexes created Mon Sep 22 05:09:51 GMT 2025