sbc.c revision 1.9
1 /* $NetBSD: sbc.c,v 1.9 1996/06/19 01:47:28 scottr Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott Reynolds 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the authors may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgements: 19 * This product includes software developed by Scott Reynolds. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * This file contains only the machine-dependent parts of the mac68k 35 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 36 * The machine-independent parts are in ncr5380sbc.c 37 * 38 * Supported hardware includes: 39 * Macintosh II family 5380-based controller 40 * 41 * Credits, history: 42 * 43 * Scott Reynolds wrote this module, based on work by Allen Briggs 44 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 45 * (atari). Thanks to Allen for supplying crucial interpretation of the 46 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 47 * Thorpe all helped to refine this code, and were considerable sources 48 * of moral support. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 61 #include <scsi/scsi_all.h> 62 #include <scsi/scsi_debug.h> 63 #include <scsi/scsiconf.h> 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include <machine/cpu.h> 69 #include <machine/viareg.h> 70 71 #include "sbcreg.h" 72 73 /* 74 * Transfers smaller than this are done using PIO 75 * (on assumption they're not worth PDMA overhead) 76 */ 77 #define MIN_DMA_LEN 128 78 79 /* 80 * Transfers larger than 8192 bytes need to be split up 81 * due to the size of the PDMA space. 82 */ 83 #define MAX_DMA_LEN 0x2000 84 85 /* 86 * From Guide to the Macintosh Family Hardware, pp. 137-143 87 * These are offsets from SCSIBase (see pmap_bootstrap.c) 88 */ 89 #define SBC_REG_OFS 0x10000 90 #define SBC_HSK_OFS 0x06000 91 #define SBC_DMA_OFS 0x12000 92 93 #define SBC_DMA_OFS_PB500 0x06000 94 95 #define SBC_REG_OFS_IIFX 0x08000 /* Just guessing... */ 96 #define SBC_HSK_OFS_IIFX 0x0e000 97 #define SBC_DMA_OFS_IIFX 0x0c000 98 99 #ifdef SBC_DEBUG 100 # define SBC_DB_INTR 0x01 101 # define SBC_DB_DMA 0x02 102 # define SBC_DB_REG 0x04 103 # define SBC_DB_BREAK 0x08 104 105 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 106 int sbc_link_flags = 0 /* | SDEV_DB2 */; 107 108 # ifndef DDB 109 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 110 # endif 111 # define SBC_BREAK \ 112 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 113 #else 114 # define SBC_BREAK 115 #endif 116 117 /* 118 * This structure is used to keep track of PDMA requests. 119 */ 120 struct sbc_pdma_handle { 121 int dh_flags; /* flags */ 122 #define SBC_DH_BUSY 0x01 /* This handle is in use */ 123 #define SBC_DH_OUT 0x02 /* PDMA data out (write) */ 124 #define SBC_DH_DONE 0x04 /* PDMA transfer is complete */ 125 u_char *dh_addr; /* data buffer */ 126 int dh_len; /* length of data buffer */ 127 }; 128 129 /* 130 * The first structure member has to be the ncr5380_softc 131 * so we can just cast to go back and forth between them. 132 */ 133 struct sbc_softc { 134 struct ncr5380_softc ncr_sc; 135 volatile struct sbc_regs *sc_regs; 136 volatile vm_offset_t sc_drq_addr; 137 volatile vm_offset_t sc_nodrq_addr; 138 volatile u_int8_t *sc_ienable; 139 volatile u_int8_t *sc_iflag; 140 int sc_options; /* options for this instance. */ 141 struct sbc_pdma_handle sc_pdma[SCI_OPENINGS]; 142 }; 143 144 /* 145 * Options. By default, SCSI interrupts and reselect are disabled. 146 * You may enable either of these features with the `flags' directive 147 * in your kernel's configuration file. 148 * 149 * Alternatively, you can patch your kernel with DDB or some other 150 * mechanism. The sc_options member of the softc is OR'd with 151 * the value in sbc_options. 152 * 153 * The options code is based on the sparc 'si' driver's version of 154 * the same. 155 */ 156 #define SBC_PDMA 0x01 /* Use PDMA for polled transfers */ 157 #define SBC_INTR 0x02 /* Allow SCSI IRQ/DRQ interrupts */ 158 #define SBC_RESELECT 0x04 /* Allow disconnect/reselect */ 159 #define SBC_OPTIONS_MASK (SBC_RESELECT|SBC_INTR|SBC_PDMA) 160 #define SBC_OPTIONS_BITS "\10\3RESELECT\2INTR\1PDMA" 161 int sbc_options = SBC_PDMA; 162 163 static int sbc_match __P((struct device *, void *, void *)); 164 static void sbc_attach __P((struct device *, struct device *, void *)); 165 static int sbc_print __P((void *, char *)); 166 static void sbc_minphys __P((struct buf *bp)); 167 168 static int sbc_wait_busy __P((struct ncr5380_softc *)); 169 static int sbc_ready __P((struct ncr5380_softc *)); 170 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 171 static int sbc_pdma_in __P((struct ncr5380_softc *, int, int, u_char *)); 172 static int sbc_pdma_out __P((struct ncr5380_softc *, int, int, u_char *)); 173 #ifdef SBC_DEBUG 174 static void decode_5380_intr __P((struct ncr5380_softc *)); 175 #endif 176 177 void sbc_intr_enable __P((struct ncr5380_softc *)); 178 void sbc_intr_disable __P((struct ncr5380_softc *)); 179 void sbc_irq_intr __P((void *)); 180 void sbc_drq_intr __P((void *)); 181 void sbc_dma_alloc __P((struct ncr5380_softc *)); 182 void sbc_dma_free __P((struct ncr5380_softc *)); 183 void sbc_dma_poll __P((struct ncr5380_softc *)); 184 void sbc_dma_setup __P((struct ncr5380_softc *)); 185 void sbc_dma_start __P((struct ncr5380_softc *)); 186 void sbc_dma_eop __P((struct ncr5380_softc *)); 187 void sbc_dma_stop __P((struct ncr5380_softc *)); 188 189 static struct scsi_adapter sbc_ops = { 190 ncr5380_scsi_cmd, /* scsi_cmd() */ 191 sbc_minphys, /* scsi_minphys() */ 192 NULL, /* open_target_lu() */ 193 NULL, /* close_target_lu() */ 194 }; 195 196 /* This is copied from julian's bt driver */ 197 /* "so we have a default dev struct for our link struct." */ 198 static struct scsi_device sbc_dev = { 199 NULL, /* Use default error handler. */ 200 NULL, /* Use default start handler. */ 201 NULL, /* Use default async handler. */ 202 NULL, /* Use default "done" routine. */ 203 }; 204 205 struct cfattach sbc_ca = { 206 sizeof(struct sbc_softc), sbc_match, sbc_attach 207 }; 208 209 struct cfdriver sbc_cd = { 210 NULL, "sbc", DV_DULL 211 }; 212 213 214 static int 215 sbc_match(parent, match, args) 216 struct device *parent; 217 void *match, *args; 218 { 219 if (!mac68k_machine.scsi80) 220 return 0; 221 return 1; 222 } 223 224 static void 225 sbc_attach(parent, self, args) 226 struct device *parent, *self; 227 void *args; 228 { 229 struct sbc_softc *sc = (struct sbc_softc *) self; 230 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) sc; 231 extern vm_offset_t SCSIBase; 232 233 /* Pull in the options flags. */ 234 sc->sc_options = ((ncr_sc->sc_dev.dv_cfdata->cf_flags | sbc_options) 235 & SBC_OPTIONS_MASK); 236 237 /* 238 * Set up offsets to 5380 registers and GLUE I/O space, and turn 239 * off options we know we can't support on certain models. 240 */ 241 switch (current_mac_model->machineid) { 242 case MACH_MACIIFX: /* Note: the IIfx isn't (yet) supported. */ 243 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS_IIFX); 244 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS_IIFX); 245 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_IIFX); 246 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 247 break; 248 case MACH_MACPB500: 249 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 250 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); /*??*/ 251 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS_PB500); 252 sc->sc_options &= ~(SBC_INTR | SBC_RESELECT); 253 break; 254 default: 255 sc->sc_regs = (struct sbc_regs *)(SCSIBase + SBC_REG_OFS); 256 sc->sc_drq_addr = (vm_offset_t)(SCSIBase + SBC_HSK_OFS); 257 sc->sc_nodrq_addr = (vm_offset_t)(SCSIBase + SBC_DMA_OFS); 258 break; 259 } 260 261 /* 262 * Fill in the prototype scsi_link. 263 */ 264 ncr_sc->sc_link.adapter_softc = sc; 265 ncr_sc->sc_link.adapter_target = 7; 266 ncr_sc->sc_link.adapter = &sbc_ops; 267 ncr_sc->sc_link.device = &sbc_dev; 268 269 /* 270 * Initialize fields used by the MI code 271 */ 272 ncr_sc->sci_r0 = &sc->sc_regs->sci_pr0.sci_reg; 273 ncr_sc->sci_r1 = &sc->sc_regs->sci_pr1.sci_reg; 274 ncr_sc->sci_r2 = &sc->sc_regs->sci_pr2.sci_reg; 275 ncr_sc->sci_r3 = &sc->sc_regs->sci_pr3.sci_reg; 276 ncr_sc->sci_r4 = &sc->sc_regs->sci_pr4.sci_reg; 277 ncr_sc->sci_r5 = &sc->sc_regs->sci_pr5.sci_reg; 278 ncr_sc->sci_r6 = &sc->sc_regs->sci_pr6.sci_reg; 279 ncr_sc->sci_r7 = &sc->sc_regs->sci_pr7.sci_reg; 280 281 /* 282 * MD function pointers used by the MI code. 283 */ 284 if (sc->sc_options & SBC_PDMA) { 285 ncr_sc->sc_pio_out = sbc_pdma_out; 286 ncr_sc->sc_pio_in = sbc_pdma_in; 287 } else { 288 ncr_sc->sc_pio_out = ncr5380_pio_out; 289 ncr_sc->sc_pio_in = ncr5380_pio_in; 290 } 291 ncr_sc->sc_dma_alloc = NULL; 292 ncr_sc->sc_dma_free = NULL; 293 ncr_sc->sc_dma_poll = NULL; 294 ncr_sc->sc_intr_on = NULL; 295 ncr_sc->sc_intr_off = NULL; 296 ncr_sc->sc_dma_setup = NULL; 297 ncr_sc->sc_dma_start = NULL; 298 ncr_sc->sc_dma_eop = NULL; 299 ncr_sc->sc_dma_stop = NULL; 300 ncr_sc->sc_flags = 0; 301 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 302 303 if (sc->sc_options & SBC_INTR) { 304 if (sc->sc_options & SBC_RESELECT) 305 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 306 ncr_sc->sc_dma_alloc = sbc_dma_alloc; 307 ncr_sc->sc_dma_free = sbc_dma_free; 308 ncr_sc->sc_dma_poll = sbc_dma_poll; 309 ncr_sc->sc_dma_setup = sbc_dma_setup; 310 ncr_sc->sc_dma_start = sbc_dma_start; 311 ncr_sc->sc_dma_eop = sbc_dma_eop; 312 ncr_sc->sc_dma_stop = sbc_dma_stop; 313 mac68k_register_scsi_drq(sbc_drq_intr, ncr_sc); 314 mac68k_register_scsi_irq(sbc_irq_intr, ncr_sc); 315 } else 316 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 317 318 /* 319 * Initialize fields used only here in the MD code. 320 */ 321 if (VIA2 == VIA2OFF) { 322 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + vIER; 323 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + vIFR; 324 } else { 325 sc->sc_ienable = Via1Base + VIA2 * 0x2000 + rIER; 326 sc->sc_iflag = Via1Base + VIA2 * 0x2000 + rIFR; 327 } 328 329 if (sc->sc_options) 330 printf(": options=%b", sc->sc_options, SBC_OPTIONS_BITS); 331 printf("\n"); 332 333 /* Now enable SCSI interrupts through VIA2, if appropriate */ 334 if (sc->sc_options & SBC_INTR) 335 sbc_intr_enable(ncr_sc); 336 337 #ifdef SBC_DEBUG 338 if (sbc_debug) 339 printf("%s: softc=%p regs=%p\n", ncr_sc->sc_dev.dv_xname, 340 sc, sc->sc_regs); 341 ncr_sc->sc_link.flags |= sbc_link_flags; 342 #endif 343 344 /* 345 * Initialize the SCSI controller itself. 346 */ 347 ncr5380_init(ncr_sc); 348 ncr5380_reset_scsibus(ncr_sc); 349 config_found(self, &(ncr_sc->sc_link), sbc_print); 350 } 351 352 static int 353 sbc_print(aux, name) 354 void *aux; 355 char *name; 356 { 357 if (name != NULL) 358 printf("%s: scsibus ", name); 359 return UNCONF; 360 } 361 362 static void 363 sbc_minphys(struct buf *bp) 364 { 365 if (bp->b_bcount > MAX_DMA_LEN) 366 bp->b_bcount = MAX_DMA_LEN; 367 return (minphys(bp)); 368 } 369 370 371 /*** 372 * General support for Mac-specific SCSI logic. 373 ***/ 374 375 /* These are used in the following inline functions. */ 376 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 377 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 378 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 379 380 /* Return zero on success. */ 381 static __inline__ int 382 sbc_wait_busy(sc) 383 struct ncr5380_softc *sc; 384 { 385 register int timo = sbc_wait_busy_timo; 386 for (;;) { 387 if (SCI_BUSY(sc)) { 388 timo = 0; /* return 0 */ 389 break; 390 } 391 if (--timo < 0) 392 break; /* return -1 */ 393 delay(2); 394 } 395 return (timo); 396 } 397 398 static __inline__ int 399 sbc_ready(sc) 400 struct ncr5380_softc *sc; 401 { 402 register int timo = sbc_ready_timo; 403 404 for (;;) { 405 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 406 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 407 timo = 0; 408 break; 409 } 410 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 411 || (SCI_BUSY(sc) == 0)) { 412 timo = -1; 413 break; 414 } 415 if (--timo < 0) 416 break; /* return -1 */ 417 delay(2); 418 } 419 return (timo); 420 } 421 422 static __inline__ int 423 sbc_wait_dreq(sc) 424 struct ncr5380_softc *sc; 425 { 426 register int timo = sbc_wait_dreq_timo; 427 428 for (;;) { 429 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 430 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 431 timo = 0; 432 break; 433 } 434 if (--timo < 0) 435 break; /* return -1 */ 436 delay(2); 437 } 438 return (timo); 439 } 440 441 442 /*** 443 * Macintosh SCSI interrupt support routines. 444 ***/ 445 446 void 447 sbc_intr_enable(ncr_sc) 448 struct ncr5380_softc *ncr_sc; 449 { 450 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 451 int s; 452 453 s = splhigh(); 454 *sc->sc_ienable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 455 splx(s); 456 } 457 458 void 459 sbc_intr_disable(ncr_sc) 460 struct ncr5380_softc *ncr_sc; 461 { 462 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 463 int s; 464 465 s = splhigh(); 466 *sc->sc_ienable = (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 467 splx(s); 468 } 469 470 void 471 sbc_irq_intr(p) 472 void *p; 473 { 474 register struct ncr5380_softc *ncr_sc = p; 475 register int claimed = 0; 476 477 /* How we ever arrive here without IRQ set is a mystery... */ 478 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 479 #ifdef SBC_DEBUG 480 if (sbc_debug & SBC_DB_INTR) 481 decode_5380_intr(ncr_sc); 482 #endif 483 claimed = ncr5380_intr(ncr_sc); 484 if (!claimed) { 485 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 486 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) 487 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 488 #ifdef SBC_DEBUG 489 else { 490 printf("%s: spurious intr\n", 491 ncr_sc->sc_dev.dv_xname); 492 SBC_BREAK; 493 } 494 #endif 495 } 496 } 497 } 498 499 #ifdef SBC_DEBUG 500 void 501 decode_5380_intr(ncr_sc) 502 struct ncr5380_softc *ncr_sc; 503 { 504 register u_char csr = *ncr_sc->sci_csr; 505 register u_char bus_csr = *ncr_sc->sci_bus_csr; 506 507 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 508 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 509 if (csr & SCI_BUS_IO) 510 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 511 else 512 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 513 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 514 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 515 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 516 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 517 ((bus_csr & ~SCI_BUS_RST) == 0)) 518 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 519 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 520 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 521 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 522 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 523 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 524 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 525 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 526 (bus_csr == 0)) 527 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 528 else 529 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 530 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 531 } 532 #endif 533 534 535 /*** 536 * The following code implements polled PDMA. 537 ***/ 538 539 static int 540 sbc_pdma_out(ncr_sc, phase, count, data) 541 struct ncr5380_softc *ncr_sc; 542 int phase; 543 int count; 544 u_char *data; 545 { 546 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 547 register volatile long *long_data = (long *) sc->sc_drq_addr; 548 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 549 register int len = count; 550 551 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 552 return ncr5380_pio_out(ncr_sc, phase, count, data); 553 554 if (sbc_wait_busy(ncr_sc) == 0) { 555 *ncr_sc->sci_mode |= SCI_MODE_DMA; 556 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 557 *ncr_sc->sci_dma_send = 0; 558 559 #define W1 *byte_data = *data++ 560 #define W4 *long_data = *((long*)data)++ 561 while (len >= 64) { 562 if (sbc_ready(ncr_sc)) 563 goto timeout; 564 W1; 565 if (sbc_ready(ncr_sc)) 566 goto timeout; 567 W1; 568 if (sbc_ready(ncr_sc)) 569 goto timeout; 570 W1; 571 if (sbc_ready(ncr_sc)) 572 goto timeout; 573 W1; 574 if (sbc_ready(ncr_sc)) 575 goto timeout; 576 W4; W4; W4; W4; 577 W4; W4; W4; W4; 578 W4; W4; W4; W4; 579 W4; W4; W4; 580 len -= 64; 581 } 582 while (len) { 583 if (sbc_ready(ncr_sc)) 584 goto timeout; 585 W1; 586 len--; 587 } 588 #undef W1 589 #undef W4 590 if (sbc_wait_dreq(ncr_sc)) 591 printf("%s: timeout waiting for DREQ.\n", 592 ncr_sc->sc_dev.dv_xname); 593 594 *byte_data = 0; 595 596 SCI_CLR_INTR(ncr_sc); 597 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 598 *ncr_sc->sci_icmd = 0; 599 } 600 return count - len; 601 602 timeout: 603 printf("%s: pdma_out: timeout len=%d count=%d\n", 604 ncr_sc->sc_dev.dv_xname, len, count); 605 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 606 *ncr_sc->sci_icmd &= ~SCI_ICMD_DATA; 607 --len; 608 } 609 610 SCI_CLR_INTR(ncr_sc); 611 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 612 *ncr_sc->sci_icmd = 0; 613 return count - len; 614 } 615 616 static int 617 sbc_pdma_in(ncr_sc, phase, count, data) 618 struct ncr5380_softc *ncr_sc; 619 int phase; 620 int count; 621 u_char *data; 622 { 623 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 624 register volatile long *long_data = (long *) sc->sc_drq_addr; 625 register volatile u_char *byte_data = (u_char *) sc->sc_nodrq_addr; 626 register int len = count; 627 628 if (count < ncr_sc->sc_min_dma_len || (sc->sc_options & SBC_PDMA) == 0) 629 return ncr5380_pio_in(ncr_sc, phase, count, data); 630 631 if (sbc_wait_busy(ncr_sc) == 0) { 632 *ncr_sc->sci_mode |= SCI_MODE_DMA; 633 *ncr_sc->sci_icmd |= SCI_ICMD_DATA; 634 *ncr_sc->sci_irecv = 0; 635 636 #define R4 *((long *)data)++ = *long_data 637 #define R1 *data++ = *byte_data 638 while (len >= 1024) { 639 if (sbc_ready(ncr_sc)) 640 goto timeout; 641 R4; R4; R4; R4; R4; R4; R4; R4; 642 R4; R4; R4; R4; R4; R4; R4; R4; 643 R4; R4; R4; R4; R4; R4; R4; R4; 644 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 645 if (sbc_ready(ncr_sc)) 646 goto timeout; 647 R4; R4; R4; R4; R4; R4; R4; R4; 648 R4; R4; R4; R4; R4; R4; R4; R4; 649 R4; R4; R4; R4; R4; R4; R4; R4; 650 R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */ 651 if (sbc_ready(ncr_sc)) 652 goto timeout; 653 R4; R4; R4; R4; R4; R4; R4; R4; 654 R4; R4; R4; R4; R4; R4; R4; R4; 655 R4; R4; R4; R4; R4; R4; R4; R4; 656 R4; R4; R4; R4; R4; R4; R4; R4; /* 384 */ 657 if (sbc_ready(ncr_sc)) 658 goto timeout; 659 R4; R4; R4; R4; R4; R4; R4; R4; 660 R4; R4; R4; R4; R4; R4; R4; R4; 661 R4; R4; R4; R4; R4; R4; R4; R4; 662 R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */ 663 if (sbc_ready(ncr_sc)) 664 goto timeout; 665 R4; R4; R4; R4; R4; R4; R4; R4; 666 R4; R4; R4; R4; R4; R4; R4; R4; 667 R4; R4; R4; R4; R4; R4; R4; R4; 668 R4; R4; R4; R4; R4; R4; R4; R4; /* 640 */ 669 if (sbc_ready(ncr_sc)) 670 goto timeout; 671 R4; R4; R4; R4; R4; R4; R4; R4; 672 R4; R4; R4; R4; R4; R4; R4; R4; 673 R4; R4; R4; R4; R4; R4; R4; R4; 674 R4; R4; R4; R4; R4; R4; R4; R4; /* 768 */ 675 if (sbc_ready(ncr_sc)) 676 goto timeout; 677 R4; R4; R4; R4; R4; R4; R4; R4; 678 R4; R4; R4; R4; R4; R4; R4; R4; 679 R4; R4; R4; R4; R4; R4; R4; R4; 680 R4; R4; R4; R4; R4; R4; R4; R4; /* 896 */ 681 if (sbc_ready(ncr_sc)) 682 goto timeout; 683 R4; R4; R4; R4; R4; R4; R4; R4; 684 R4; R4; R4; R4; R4; R4; R4; R4; 685 R4; R4; R4; R4; R4; R4; R4; R4; 686 R4; R4; R4; R4; R4; R4; R4; R4; /* 1024 */ 687 len -= 1024; 688 } 689 while (len >= 128) { 690 if (sbc_ready(ncr_sc)) 691 goto timeout; 692 R4; R4; R4; R4; R4; R4; R4; R4; 693 R4; R4; R4; R4; R4; R4; R4; R4; 694 R4; R4; R4; R4; R4; R4; R4; R4; 695 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 696 len -= 128; 697 } 698 while (len) { 699 if (sbc_ready(ncr_sc)) 700 goto timeout; 701 R1; 702 len--; 703 } 704 #undef R4 705 #undef R1 706 SCI_CLR_INTR(ncr_sc); 707 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 708 *ncr_sc->sci_icmd = 0; 709 } 710 return count - len; 711 712 timeout: 713 printf("%s: pdma_in: timeout len=%d count=%d\n", 714 ncr_sc->sc_dev.dv_xname, len, count); 715 716 SCI_CLR_INTR(ncr_sc); 717 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 718 *ncr_sc->sci_icmd = 0; 719 return count - len; 720 } 721 722 723 /*** 724 * The following code implements interrupt-driven PDMA. 725 ***/ 726 727 /* 728 * This is the meat of the PDMA transfer. 729 * When we get here, we shove data as fast as the mac can take it. 730 * We depend on several things: 731 * * All macs after the Mac Plus that have a 5380 chip should have a general 732 * logic IC that handshakes data for blind transfers. 733 * * If the SCSI controller finishes sending/receiving data before we do, 734 * the same general logic IC will generate a /BERR for us in short order. 735 * * The fault address for said /BERR minus the base address for the 736 * transfer will be the amount of data that was actually written. 737 * 738 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 739 * detect and handle the bus error for early termination of a command. 740 * This is usually caused by a disconnecting target. 741 */ 742 void 743 sbc_drq_intr(p) 744 void *p; 745 { 746 extern int *nofault, mac68k_buserr_addr; 747 register struct sbc_softc *sc = (struct sbc_softc *) p; 748 register struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *) p; 749 register struct sci_req *sr = ncr_sc->sc_current; 750 register struct sbc_pdma_handle *dh = sr->sr_dma_hand; 751 label_t faultbuf; 752 volatile u_int32_t *long_drq; 753 u_int32_t *long_data; 754 volatile u_int8_t *drq; 755 u_int8_t *data; 756 register int count; 757 int dcount, resid; 758 u_int8_t tmp; 759 760 /* 761 * If we're not ready to xfer data, or have no more, just return. 762 */ 763 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 764 return; 765 766 #ifdef SBC_DEBUG 767 if (sbc_debug & SBC_DB_INTR) 768 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 769 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 770 #endif 771 772 /* 773 * Setup for a possible bus error caused by SCSI controller 774 * switching out of DATA-IN/OUT before we're done with the 775 * current transfer. 776 */ 777 nofault = (int *) &faultbuf; 778 779 if (setjmp((label_t *) nofault)) { 780 nofault = (int *) 0; 781 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 782 count = (( (u_long) mac68k_buserr_addr 783 - (u_long) sc->sc_drq_addr)); 784 785 if ((count < 0) || (count > dh->dh_len)) { 786 printf("%s: complete=0x%x (pending 0x%x)\n", 787 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 788 panic("something is wrong"); 789 } 790 791 dh->dh_addr += count; 792 dh->dh_len -= count; 793 } 794 795 #ifdef SBC_DEBUG 796 if (sbc_debug & SBC_DB_INTR) 797 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 798 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 799 #endif 800 mac68k_buserr_addr = 0; 801 802 return; 803 } 804 805 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 806 #if notyet /* XXX */ 807 /* 808 * Get the source address aligned. 809 */ 810 resid = 811 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 812 if (count && count < 4) { 813 drq = (volatile u_int8_t *) sc->sc_drq_addr; 814 data = (u_int8_t *) dh->dh_addr; 815 816 #define W1 *drq++ = *data++ 817 while (count) { 818 W1; count--; 819 } 820 #undef W1 821 dh->dh_addr += resid; 822 dh->dh_len -= resid; 823 } 824 825 /* 826 * Start the transfer. 827 */ 828 while (dh->dh_len) { 829 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 830 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 831 long_data = (u_int32_t *) dh->dh_addr; 832 833 #define W4 *long_drq++ = *long_data++ 834 while (count >= 64) { 835 W4; W4; W4; W4; W4; W4; W4; W4; 836 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 837 count -= 64; 838 } 839 while (count >= 4) { 840 W4; count -= 4; 841 } 842 #undef W4 843 data = (u_int8_t *) long_data; 844 drq = (u_int8_t *) long_drq; 845 #else /* notyet */ 846 /* 847 * Start the transfer. 848 */ 849 while (dh->dh_len) { 850 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 851 drq = (volatile u_int8_t *) sc->sc_drq_addr; 852 data = (u_int8_t *) dh->dh_addr; 853 #endif /* notyet */ 854 855 #define W1 *drq++ = *data++ 856 while (count) { 857 W1; count--; 858 } 859 #undef W1 860 dh->dh_len -= dcount; 861 dh->dh_addr += dcount; 862 } 863 dh->dh_flags |= SBC_DH_DONE; 864 865 /* 866 * XXX -- Read a byte from the SBC to trigger a /BERR. 867 * This seems to be necessary for us to notice that 868 * the target has disconnected. Ick. 06 jun 1996 (sr) 869 */ 870 if (dcount >= MAX_DMA_LEN) { 871 #if 0 872 while ((*ncr_sc->sci_csr & SCI_CSR_ACK) == 0) 873 ; 874 #endif 875 drq = (volatile u_int8_t *) sc->sc_drq_addr; 876 } 877 tmp = *drq; 878 } else { /* Data In */ 879 /* 880 * Get the dest address aligned. 881 */ 882 resid = 883 count = min(dh->dh_len, 4 - (((int) dh->dh_addr) & 0x3)); 884 if (count && count < 4) { 885 data = (u_int8_t *) dh->dh_addr; 886 drq = (volatile u_int8_t *) sc->sc_drq_addr; 887 888 #define R1 *data++ = *drq++ 889 while (count) { 890 R1; count--; 891 } 892 #undef R1 893 dh->dh_addr += resid; 894 dh->dh_len -= resid; 895 } 896 897 /* 898 * Start the transfer. 899 */ 900 while (dh->dh_len) { 901 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 902 long_data = (u_int32_t *) dh->dh_addr; 903 long_drq = (volatile u_int32_t *) sc->sc_drq_addr; 904 905 #define R4 *long_data++ = *long_drq++ 906 while (count >= 64) { 907 R4; R4; R4; R4; R4; R4; R4; R4; 908 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 909 count -= 64; 910 } 911 while (count >= 4) { 912 R4; count -= 4; 913 } 914 #undef R4 915 data = (u_int8_t *) long_data; 916 drq = (volatile u_int8_t *) long_drq; 917 918 #define R1 *data++ = *drq++ 919 while (count) { 920 R1; count--; 921 } 922 #undef R1 923 dh->dh_len -= dcount; 924 dh->dh_addr += dcount; 925 } 926 dh->dh_flags |= SBC_DH_DONE; 927 } 928 929 /* 930 * OK. No bus error occurred above. Clear the nofault flag 931 * so we no longer short-circuit bus errors. 932 */ 933 nofault = (int *) 0; 934 935 #ifdef SBC_DEBUG 936 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 937 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 938 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 939 *ncr_sc->sci_bus_csr); 940 #endif 941 } 942 943 void 944 sbc_dma_alloc(ncr_sc) 945 struct ncr5380_softc *ncr_sc; 946 { 947 struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 948 struct sci_req *sr = ncr_sc->sc_current; 949 struct scsi_xfer *xs = sr->sr_xs; 950 struct sbc_pdma_handle *dh; 951 int i, xlen; 952 953 #ifdef DIAGNOSTIC 954 if (sr->sr_dma_hand != NULL) 955 panic("sbc_dma_alloc: already have PDMA handle"); 956 #endif 957 958 /* Polled transfers shouldn't allocate a PDMA handle. */ 959 if (sr->sr_flags & SR_IMMED) 960 return; 961 962 xlen = ncr_sc->sc_datalen; 963 964 /* Make sure our caller checked sc_min_dma_len. */ 965 if (xlen < MIN_DMA_LEN) 966 panic("sbc_dma_alloc: len=0x%x\n", xlen); 967 968 /* 969 * Find free PDMA handle. Guaranteed to find one since we 970 * have as many PDMA handles as the driver has processes. 971 * (instances?) 972 */ 973 for (i = 0; i < SCI_OPENINGS; i++) { 974 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 975 goto found; 976 } 977 panic("sbc: no free PDMA handles"); 978 found: 979 dh = &sc->sc_pdma[i]; 980 dh->dh_flags = SBC_DH_BUSY; 981 dh->dh_addr = ncr_sc->sc_dataptr; 982 dh->dh_len = xlen; 983 984 /* Copy the 'write' flag for convenience. */ 985 if (xs->flags & SCSI_DATA_OUT) 986 dh->dh_flags |= SBC_DH_OUT; 987 988 sr->sr_dma_hand = dh; 989 } 990 991 void 992 sbc_dma_free(ncr_sc) 993 struct ncr5380_softc *ncr_sc; 994 { 995 struct sci_req *sr = ncr_sc->sc_current; 996 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 997 998 #ifdef DIAGNOSTIC 999 if (sr->sr_dma_hand == NULL) 1000 panic("sbc_dma_free: no DMA handle"); 1001 #endif 1002 1003 if (ncr_sc->sc_state & NCR_DOINGDMA) 1004 panic("sbc_dma_free: free while in progress"); 1005 1006 if (dh->dh_flags & SBC_DH_BUSY) { 1007 dh->dh_flags = 0; 1008 dh->dh_addr = NULL; 1009 dh->dh_len = 0; 1010 } 1011 sr->sr_dma_hand = NULL; 1012 } 1013 1014 void 1015 sbc_dma_poll(ncr_sc) 1016 struct ncr5380_softc *ncr_sc; 1017 { 1018 struct sci_req *sr = ncr_sc->sc_current; 1019 1020 /* 1021 * We shouldn't arrive here; if SR_IMMED is set, then 1022 * dma_alloc() should have refused to allocate a handle 1023 * for the transfer. This forces the polled PDMA code 1024 * to handle the request... 1025 */ 1026 #ifdef SBC_DEBUG 1027 if (sbc_debug & SBC_DB_DMA) 1028 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 1029 #endif 1030 sr->sr_flags |= SR_OVERDUE; 1031 } 1032 1033 void 1034 sbc_dma_setup(ncr_sc) 1035 struct ncr5380_softc *ncr_sc; 1036 { 1037 /* Not needed; we don't have real DMA */ 1038 } 1039 1040 void 1041 sbc_dma_start(ncr_sc) 1042 struct ncr5380_softc *ncr_sc; 1043 { 1044 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1045 struct sci_req *sr = ncr_sc->sc_current; 1046 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1047 1048 /* 1049 * Match bus phase, clear pending interrupts, set DMA mode, and 1050 * assert data bus (for writing only), then start the transfer. 1051 */ 1052 if (dh->dh_flags & SBC_DH_OUT) { 1053 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 1054 SCI_CLR_INTR(ncr_sc); 1055 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1056 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1057 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 1058 *ncr_sc->sci_dma_send = 0; 1059 } else { 1060 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 1061 SCI_CLR_INTR(ncr_sc); 1062 *sc->sc_iflag = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ); 1063 *ncr_sc->sci_mode |= SCI_MODE_DMA; 1064 *ncr_sc->sci_icmd = 0; 1065 *ncr_sc->sci_irecv = 0; 1066 } 1067 ncr_sc->sc_state |= NCR_DOINGDMA; 1068 1069 #ifdef SBC_DEBUG 1070 if (sbc_debug & SBC_DB_DMA) 1071 printf("%s: PDMA started, va=%p, len=0x%x\n", 1072 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 1073 #endif 1074 } 1075 1076 void 1077 sbc_dma_eop(ncr_sc) 1078 struct ncr5380_softc *ncr_sc; 1079 { 1080 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 1081 } 1082 1083 void 1084 sbc_dma_stop(ncr_sc) 1085 struct ncr5380_softc *ncr_sc; 1086 { 1087 register struct sbc_softc *sc = (struct sbc_softc *) ncr_sc; 1088 struct sci_req *sr = ncr_sc->sc_current; 1089 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 1090 register int ntrans; 1091 1092 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 1093 #ifdef SBC_DEBUG 1094 if (sbc_debug & SBC_DB_DMA) 1095 printf("%s: dma_stop: DMA not running\n", 1096 ncr_sc->sc_dev.dv_xname); 1097 #endif 1098 return; 1099 } 1100 ncr_sc->sc_state &= ~NCR_DOINGDMA; 1101 1102 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 1103 ntrans = ncr_sc->sc_datalen - dh->dh_len; 1104 1105 #ifdef SBC_DEBUG 1106 if (sbc_debug & SBC_DB_DMA) 1107 printf("%s: dma_stop: ntrans=0x%x\n", 1108 ncr_sc->sc_dev.dv_xname, ntrans); 1109 #endif 1110 1111 if (ntrans > ncr_sc->sc_datalen) 1112 panic("sbc_dma_stop: excess transfer\n"); 1113 1114 /* Adjust data pointer */ 1115 ncr_sc->sc_dataptr += ntrans; 1116 ncr_sc->sc_datalen -= ntrans; 1117 1118 /* Clear any pending interrupts. */ 1119 SCI_CLR_INTR(ncr_sc); 1120 *sc->sc_iflag = 0x80 | V2IF_SCSIIRQ; 1121 } 1122 1123 /* Put SBIC back into PIO mode. */ 1124 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 1125 *ncr_sc->sci_icmd = 0; 1126 1127 #ifdef SBC_DEBUG 1128 if (sbc_debug & SBC_DB_REG) 1129 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 1130 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 1131 *ncr_sc->sci_bus_csr); 1132 #endif 1133 } 1134
Indexes created Mon Sep 22 05:09:51 GMT 2025