cpu.h revision 1.14 1 1.1 briggs /*
2 1.1 briggs * Copyright (c) 1988 University of Utah.
3 1.1 briggs * Copyright (c) 1982, 1990 The Regents of the University of California.
4 1.1 briggs * All rights reserved.
5 1.1 briggs *
6 1.1 briggs * This code is derived from software contributed to Berkeley by
7 1.1 briggs * the Systems Programming Group of the University of Utah Computer
8 1.1 briggs * Science Department.
9 1.1 briggs *
10 1.1 briggs * Redistribution and use in source and binary forms, with or without
11 1.1 briggs * modification, are permitted provided that the following conditions
12 1.1 briggs * are met:
13 1.1 briggs * 1. Redistributions of source code must retain the above copyright
14 1.1 briggs * notice, this list of conditions and the following disclaimer.
15 1.1 briggs * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 briggs * notice, this list of conditions and the following disclaimer in the
17 1.1 briggs * documentation and/or other materials provided with the distribution.
18 1.1 briggs * 3. All advertising materials mentioning features or use of this software
19 1.1 briggs * must display the following acknowledgement:
20 1.1 briggs * This product includes software developed by the University of
21 1.1 briggs * California, Berkeley and its contributors.
22 1.1 briggs * 4. Neither the name of the University nor the names of its contributors
23 1.1 briggs * may be used to endorse or promote products derived from this software
24 1.1 briggs * without specific prior written permission.
25 1.1 briggs *
26 1.1 briggs * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 1.1 briggs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 1.1 briggs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 1.1 briggs * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 1.1 briggs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 1.1 briggs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 1.1 briggs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 1.1 briggs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 1.1 briggs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 1.1 briggs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 1.1 briggs * SUCH DAMAGE.
37 1.1 briggs */
38 1.2 briggs
39 1.2 briggs /*
40 1.2 briggs * Copyright (c) 1992, 1993 BCDL Labs. All rights reserved.
41 1.2 briggs * Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot
42 1.2 briggs
43 1.2 briggs * Redistribution of this source code or any part thereof is permitted,
44 1.2 briggs * provided that the following conditions are met:
45 1.2 briggs * 1) Utilized source contains the copyright message above, this list
46 1.2 briggs * of conditions, and the following disclaimer.
47 1.2 briggs * 2) Binary objects containing compiled source reproduce the
48 1.2 briggs * copyright notice above on startup.
49 1.1 briggs *
50 1.2 briggs * CAVEAT: This source code is provided "as-is" by BCDL Labs, and any
51 1.2 briggs * warranties of ANY kind are disclaimed. We don't even claim that it
52 1.2 briggs * won't crash your hard disk. Basically, we want a little credit if
53 1.2 briggs * it works, but we don't want to get mail-bombed if it doesn't.
54 1.1 briggs */
55 1.1 briggs
56 1.1 briggs /*
57 1.1 briggs * from: Utah $Hdr: cpu.h 1.16 91/03/25$
58 1.1 briggs *
59 1.2 briggs * from: @(#)cpu.h 7.7 (Berkeley) 6/27/91
60 1.14 briggs * $Id: cpu.h,v 1.14 1994/07/21 00:33:54 briggs Exp $
61 1.1 briggs */
62 1.1 briggs
63 1.1 briggs /*
64 1.1 briggs ALICE
65 1.1 briggs BG -- Sat May 23 23:58:23 EDT 1992
66 1.3 briggs Exported defines and stuff unique to mac68k.
67 1.3 briggs A lot of this stuff is really specific to the m68k, not just the macs,
68 1.3 briggs but there isn't time to do anything about that right now...
69 1.1 briggs */
70 1.1 briggs
71 1.8 briggs #ifndef _MACHINE_CPU_H_
72 1.8 briggs #define _MACHINE_CPU_H_ 1
73 1.8 briggs
74 1.1 briggs /*
75 1.1 briggs * definitions of cpu-dependent requirements
76 1.1 briggs * referenced in generic code
77 1.1 briggs */
78 1.1 briggs #define COPY_SIGCODE /* copy sigcode above user stack in exec */
79 1.1 briggs
80 1.11 briggs #define cpu_swapin(p) /* nothing */
81 1.11 briggs #define cpu_exec(p) /* nothing */
82 1.11 briggs #define cpu_wait(p) /* nothing */
83 1.11 briggs #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap
84 1.11 briggs #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp
85 1.1 briggs
86 1.1 briggs /*
87 1.1 briggs * Arguments to hardclock, softclock and gatherstats
88 1.1 briggs * encapsulate the previous machine state in an opaque
89 1.1 briggs * clockframe; for hp300, use just what the hardware
90 1.1 briggs * leaves on the stack.
91 1.1 briggs */
92 1.1 briggs
93 1.10 briggs struct clockframe {
94 1.11 briggs u_short sr;
95 1.11 briggs u_long pc;
96 1.11 briggs u_short vo;
97 1.10 briggs };
98 1.1 briggs
99 1.11 briggs #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
100 1.11 briggs #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
101 1.1 briggs #define CLKF_PC(framep) ((framep)->pc)
102 1.11 briggs #define CLKF_INTR(framep) (0) /* XXX should use PSL_M (see hp300) */
103 1.1 briggs
104 1.1 briggs /*
105 1.1 briggs * Preempt the current process if in interrupt from user mode,
106 1.1 briggs * or after the current trap/syscall if in system mode.
107 1.1 briggs */
108 1.1 briggs #define need_resched() { want_resched++; aston(); }
109 1.1 briggs
110 1.1 briggs /*
111 1.1 briggs * Give a profiling tick to the current process from the softclock
112 1.1 briggs * interrupt. Request an ast to send us through trap(),
113 1.1 briggs * marking the proc as needing a profiling tick.
114 1.1 briggs */
115 1.10 briggs #define profile_tick(p, framep) ( (p)->p_flag |= P_OWEUPC, aston() )
116 1.10 briggs #define need_proftick(p) ( (p)->p_flag |= P_OWEUPC, aston() )
117 1.1 briggs
118 1.1 briggs /*
119 1.1 briggs * Notify the current process (p) that it has a signal pending,
120 1.1 briggs * process as soon as possible.
121 1.1 briggs */
122 1.1 briggs #define signotify(p) aston()
123 1.1 briggs
124 1.1 briggs #define aston() (astpending++)
125 1.1 briggs
126 1.1 briggs int astpending; /* need to trap before returning to user mode */
127 1.1 briggs int want_resched; /* resched() was called */
128 1.1 briggs
129 1.1 briggs /*
130 1.1 briggs * simulated software interrupt register
131 1.1 briggs */
132 1.1 briggs extern unsigned char ssir;
133 1.1 briggs
134 1.1 briggs #define SIR_NET 0x1
135 1.1 briggs #define SIR_CLOCK 0x2
136 1.2 briggs #define SIR_SERIAL 0x4
137 1.1 briggs
138 1.1 briggs #define siroff(x) ssir &= ~(x)
139 1.1 briggs #define setsoftnet() ssir |= SIR_NET
140 1.1 briggs #define setsoftclock() ssir |= SIR_CLOCK
141 1.2 briggs #define setsoftserial() ssir |= SIR_SERIAL
142 1.1 briggs
143 1.11 briggs #define CPU_CONSDEV 1
144 1.11 briggs #define CPU_MAXID 2
145 1.11 briggs
146 1.11 briggs #define CTL_MACHDEP_NAMES { \
147 1.11 briggs { 0, 0 }, \
148 1.11 briggs { "console_device", CTLTYPE_STRUCT }, \
149 1.11 briggs }
150 1.1 briggs
151 1.7 briggs /* values for machineid --
152 1.7 briggs * These are equivalent to the MacOS Gestalt values. */
153 1.7 briggs #define MACH_MACII 6
154 1.7 briggs #define MACH_MACIIX 7
155 1.7 briggs #define MACH_MACIICX 8
156 1.2 briggs #define MACH_MACSE30 9
157 1.7 briggs #define MACH_MACIICI 11
158 1.7 briggs #define MACH_MACIIFX 13
159 1.7 briggs #define MACH_MACIISI 18
160 1.5 briggs #define MACH_MACQ900 20
161 1.5 briggs #define MACH_MACPB170 21
162 1.5 briggs #define MACH_MACQ700 22
163 1.7 briggs #define MACH_MACCLASSICII 23
164 1.7 briggs #define MACH_MACPB100 24
165 1.5 briggs #define MACH_MACPB140 25
166 1.7 briggs #define MACH_MACQ950 26
167 1.7 briggs #define MACH_MACLCIII 27
168 1.7 briggs #define MACH_MACPB210 29
169 1.7 briggs #define MACH_MACC650 30
170 1.7 briggs #define MACH_MACPB230 32
171 1.7 briggs #define MACH_MACPB180 33
172 1.7 briggs #define MACH_MACPB160 34
173 1.7 briggs #define MACH_MACQ800 35
174 1.7 briggs #define MACH_MACQ650 36
175 1.6 briggs #define MACH_MACLCII 37
176 1.7 briggs #define MACH_MACPB250 38
177 1.7 briggs #define MACH_MACIIVI 44
178 1.7 briggs #define MACH_MACP600 45
179 1.7 briggs #define MACH_MACIIVX 48
180 1.7 briggs #define MACH_MACCCLASSIC 49
181 1.7 briggs #define MACH_MACPB165C 50
182 1.7 briggs #define MACH_MACC610 52
183 1.7 briggs #define MACH_MACQ610 53
184 1.7 briggs #define MACH_MACPB145 54
185 1.7 briggs #define MACH_MACLC520 56
186 1.7 briggs #define MACH_MACC660AV 60
187 1.7 briggs #define MACH_MACP460 62
188 1.7 briggs #define MACH_MACPB180C 71
189 1.7 briggs #define MACH_MACPB270 77
190 1.7 briggs #define MACH_MACQ840AV 78
191 1.7 briggs #define MACH_MACP550 80
192 1.7 briggs #define MACH_MACPB165 84
193 1.7 briggs #define MACH_MACTV 88
194 1.7 briggs #define MACH_MACLC475 89
195 1.7 briggs #define MACH_MACLC575 92
196 1.7 briggs #define MACH_MACQ605 94
197 1.1 briggs
198 1.13 briggs /*
199 1.13 briggs * Machine classes. These define subsets of the above machines.
200 1.13 briggs */
201 1.13 briggs #define MACH_CLASSH 0x0000 /* Hopeless cases... */
202 1.13 briggs #define MACH_CLASSII 0x0001 /* MacII class */
203 1.13 briggs #define MACH_CLASSIIci 0x0003 /* Similar to IIci -- Have RBV. */
204 1.13 briggs #define MACH_CLASSIIfx 0x0004 /* The IIfx is in a class by itself. */
205 1.13 briggs #define MACH_CLASSPB 0x0008 /* Powerbooks. Power management. */
206 1.13 briggs #define MACH_CLASSLC 0x0010 /* Low-Cost/Performa/Wal-Mart Macs. */
207 1.13 briggs #define MACH_CLASSQ 0x0100 /* Centris/Quadras. */
208 1.13 briggs
209 1.1 briggs /* MF processor passed in */
210 1.1 briggs #define MACH_68020 0
211 1.1 briggs #define MACH_68030 1
212 1.1 briggs #define MACH_68040 2
213 1.1 briggs #define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */
214 1.1 briggs
215 1.8 briggs /* Defines for mmutype */
216 1.12 briggs #define MMU_68040 -2
217 1.12 briggs #define MMU_68030 -1
218 1.12 briggs /* #define MMU_HP 0 Just a reminder as to where this came from. */
219 1.12 briggs #define MMU_68851 1
220 1.8 briggs
221 1.1 briggs /* values for cpuspeed (not really related to clock speed due to caches) */
222 1.1 briggs #define MHZ_8 1
223 1.1 briggs #define MHZ_16 2
224 1.1 briggs #define MHZ_25 3
225 1.1 briggs #define MHZ_33 4
226 1.1 briggs #define MHZ_40 5
227 1.1 briggs
228 1.1 briggs #ifdef KERNEL
229 1.13 briggs struct mac68k_machine_S {
230 1.13 briggs int cpu_model_index;
231 1.13 briggs /*
232 1.13 briggs * Misc. info from booter.
233 1.13 briggs */
234 1.13 briggs int machineid;
235 1.13 briggs int mach_processor;
236 1.13 briggs int mach_memsize;
237 1.13 briggs int booter_version;
238 1.13 briggs /*
239 1.13 briggs * Debugging flags.
240 1.13 briggs */
241 1.13 briggs int do_graybars;
242 1.13 briggs int serial_boot_echo;
243 1.13 briggs /*
244 1.13 briggs * Misc. hardware info.
245 1.13 briggs */
246 1.13 briggs int scsi80; /* Has NCR 5380 */
247 1.13 briggs int scsi96; /* Has NCR 53C96 */
248 1.13 briggs int scsi96_2; /* Has 2nd 53C96 */
249 1.14 briggs int sonic; /* Has SONIC e-net */
250 1.13 briggs
251 1.13 briggs int sccClkConst; /* "Constant" for SCC bps */
252 1.13 briggs };
253 1.13 briggs
254 1.13 briggs extern unsigned long IOBase; /* Base address of I/O */
255 1.13 briggs extern unsigned long NuBusBase; /* Base address of NuBus */
256 1.11 briggs
257 1.13 briggs extern struct mac68k_machine_S mac68k_machine;
258 1.13 briggs extern int mmutype, cpu040;
259 1.13 briggs extern unsigned long load_addr ;
260 1.1 briggs #endif
261 1.1 briggs
262 1.1 briggs /* physical memory sections */
263 1.1 briggs #define ROMBASE (0x40000000)
264 1.13 briggs
265 1.13 briggs /* This should not be used. Use IOBase, instead. */
266 1.13 briggs #define INTIOBASE (0x50000000)
267 1.13 briggs
268 1.13 briggs #define INTIOTOP (IOBase+0x01000000)
269 1.13 briggs #define IIOMAPSIZE btoc(0x01000000)
270 1.1 briggs
271 1.11 briggs /* XXX -- Need to do something about superspace. */
272 1.1 briggs #ifdef NO_SUPER_SPACE_YET
273 1.1 briggs #define NBSBASE 0x60000000 /* NUBUS Super space */
274 1.1 briggs #define NBSTOP 0xF0000000
275 1.1 briggs #endif
276 1.1 briggs #define NBBASE 0xF9000000 /* NUBUS space */
277 1.1 briggs #define NBTOP 0xFF000000 /* NUBUS space */
278 1.1 briggs #define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */
279 1.1 briggs #define NBMEMSIZE 0x01000000 /* 16 megs per card */
280 1.1 briggs #define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */
281 1.1 briggs
282 1.1 briggs /*
283 1.1 briggs * 68851 and 68030 MMU
284 1.1 briggs */
285 1.1 briggs #define PMMU_LVLMASK 0x0007
286 1.1 briggs #define PMMU_INV 0x0400
287 1.1 briggs #define PMMU_WP 0x0800
288 1.1 briggs #define PMMU_ALV 0x1000
289 1.1 briggs #define PMMU_SO 0x2000
290 1.1 briggs #define PMMU_LV 0x4000
291 1.1 briggs #define PMMU_BE 0x8000
292 1.1 briggs #define PMMU_FAULT (PMMU_WP|PMMU_INV)
293 1.1 briggs
294 1.1 briggs /* 680X0 function codes */
295 1.1 briggs #define FC_USERD 1 /* user data space */
296 1.1 briggs #define FC_USERP 2 /* user program space */
297 1.1 briggs #define FC_SUPERD 5 /* supervisor data space */
298 1.1 briggs #define FC_SUPERP 6 /* supervisor program space */
299 1.1 briggs #define FC_CPU 7 /* CPU space */
300 1.1 briggs
301 1.1 briggs /* fields in the 68020 cache control register */
302 1.1 briggs #define IC_ENABLE 0x0001 /* enable instruction cache */
303 1.1 briggs #define IC_FREEZE 0x0002 /* freeze instruction cache */
304 1.1 briggs #define IC_CE 0x0004 /* clear instruction cache entry */
305 1.1 briggs #define IC_CLR 0x0008 /* clear entire instruction cache */
306 1.1 briggs
307 1.1 briggs /* additional fields in the 68030 cache control register */
308 1.1 briggs #define IC_BE 0x0010 /* instruction burst enable */
309 1.1 briggs #define DC_ENABLE 0x0100 /* data cache enable */
310 1.1 briggs #define DC_FREEZE 0x0200 /* data cache freeze */
311 1.1 briggs #define DC_CE 0x0400 /* clear data cache entry */
312 1.1 briggs #define DC_CLR 0x0800 /* clear entire data cache */
313 1.1 briggs #define DC_BE 0x1000 /* data burst enable */
314 1.1 briggs #define DC_WA 0x2000 /* write allocate */
315 1.1 briggs
316 1.8 briggs /* fields in the 68040 cache control register */
317 1.8 briggs #define IC40_ENABLE 0x00008000 /* enable instruction cache */
318 1.8 briggs #define DC40_ENABLE 0x80000000 /* enable data cache */
319 1.8 briggs
320 1.1 briggs #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
321 1.1 briggs #define CACHE_OFF (DC_CLR|IC_CLR)
322 1.1 briggs #define CACHE_CLR (CACHE_ON)
323 1.1 briggs #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
324 1.1 briggs #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
325 1.8 briggs
326 1.8 briggs /* 68040 cache control */
327 1.8 briggs #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE)
328 1.8 briggs #define CACHE40_OFF 0x00000000
329 1.8 briggs
330 1.8 briggs #endif /* !_MACHINE_CPU_H_ */
331