cpu.h revision 1.7 1 1.1 briggs /*
2 1.1 briggs * Copyright (c) 1988 University of Utah.
3 1.1 briggs * Copyright (c) 1982, 1990 The Regents of the University of California.
4 1.1 briggs * All rights reserved.
5 1.1 briggs *
6 1.1 briggs * This code is derived from software contributed to Berkeley by
7 1.1 briggs * the Systems Programming Group of the University of Utah Computer
8 1.1 briggs * Science Department.
9 1.1 briggs *
10 1.1 briggs * Redistribution and use in source and binary forms, with or without
11 1.1 briggs * modification, are permitted provided that the following conditions
12 1.1 briggs * are met:
13 1.1 briggs * 1. Redistributions of source code must retain the above copyright
14 1.1 briggs * notice, this list of conditions and the following disclaimer.
15 1.1 briggs * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 briggs * notice, this list of conditions and the following disclaimer in the
17 1.1 briggs * documentation and/or other materials provided with the distribution.
18 1.1 briggs * 3. All advertising materials mentioning features or use of this software
19 1.1 briggs * must display the following acknowledgement:
20 1.1 briggs * This product includes software developed by the University of
21 1.1 briggs * California, Berkeley and its contributors.
22 1.1 briggs * 4. Neither the name of the University nor the names of its contributors
23 1.1 briggs * may be used to endorse or promote products derived from this software
24 1.1 briggs * without specific prior written permission.
25 1.1 briggs *
26 1.1 briggs * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 1.1 briggs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 1.1 briggs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 1.1 briggs * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 1.1 briggs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 1.1 briggs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 1.1 briggs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 1.1 briggs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 1.1 briggs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 1.1 briggs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 1.1 briggs * SUCH DAMAGE.
37 1.1 briggs */
38 1.2 briggs
39 1.2 briggs /*
40 1.2 briggs * Copyright (c) 1992, 1993 BCDL Labs. All rights reserved.
41 1.2 briggs * Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot
42 1.2 briggs
43 1.2 briggs * Redistribution of this source code or any part thereof is permitted,
44 1.2 briggs * provided that the following conditions are met:
45 1.2 briggs * 1) Utilized source contains the copyright message above, this list
46 1.2 briggs * of conditions, and the following disclaimer.
47 1.2 briggs * 2) Binary objects containing compiled source reproduce the
48 1.2 briggs * copyright notice above on startup.
49 1.1 briggs *
50 1.2 briggs * CAVEAT: This source code is provided "as-is" by BCDL Labs, and any
51 1.2 briggs * warranties of ANY kind are disclaimed. We don't even claim that it
52 1.2 briggs * won't crash your hard disk. Basically, we want a little credit if
53 1.2 briggs * it works, but we don't want to get mail-bombed if it doesn't.
54 1.1 briggs */
55 1.1 briggs
56 1.1 briggs /*
57 1.1 briggs * from: Utah $Hdr: cpu.h 1.16 91/03/25$
58 1.1 briggs *
59 1.2 briggs * from: @(#)cpu.h 7.7 (Berkeley) 6/27/91
60 1.7 briggs * $Id: cpu.h,v 1.7 1994/03/01 15:22:47 briggs Exp $
61 1.1 briggs */
62 1.1 briggs
63 1.1 briggs /*
64 1.1 briggs ALICE
65 1.1 briggs BG -- Sat May 23 23:58:23 EDT 1992
66 1.3 briggs Exported defines and stuff unique to mac68k.
67 1.3 briggs A lot of this stuff is really specific to the m68k, not just the macs,
68 1.3 briggs but there isn't time to do anything about that right now...
69 1.1 briggs */
70 1.1 briggs
71 1.1 briggs /*
72 1.1 briggs * definitions of cpu-dependent requirements
73 1.1 briggs * referenced in generic code
74 1.1 briggs */
75 1.1 briggs #define COPY_SIGCODE /* copy sigcode above user stack in exec */
76 1.1 briggs
77 1.1 briggs /*
78 1.1 briggs * function vs. inline configuration;
79 1.1 briggs * these are defined to get generic functions
80 1.1 briggs * rather than inline or machine-dependent implementations
81 1.1 briggs */
82 1.1 briggs #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */
83 1.1 briggs #undef NEED_FFS /* don't need ffs function */
84 1.1 briggs #undef NEED_BCMP /* don't need bcmp function */
85 1.1 briggs #undef NEED_STRLEN /* don't need strlen function */
86 1.1 briggs
87 1.1 briggs /* ALICE BG -- Sun May 24 11:31:35 EDT 1992 -- what the hell do these things */
88 1.1 briggs /* do? */
89 1.1 briggs #define cpu_exec(p) /* nothing */
90 1.1 briggs #define cpu_wait(p) /* nothing */
91 1.1 briggs
92 1.1 briggs /*
93 1.1 briggs * Arguments to hardclock, softclock and gatherstats
94 1.1 briggs * encapsulate the previous machine state in an opaque
95 1.1 briggs * clockframe; for hp300, use just what the hardware
96 1.1 briggs * leaves on the stack.
97 1.1 briggs */
98 1.1 briggs /* ALICE 05/23/92 BG -- Oh, no. What does a VIA intleave on the stack? */
99 1.1 briggs /* ALICE 06/27/92 LK -- Make sure hardware clock routine does this: */
100 1.1 briggs
101 1.1 briggs typedef struct intrframe {
102 1.1 briggs int pc;
103 1.1 briggs int ps;
104 1.1 briggs } clockframe;
105 1.1 briggs
106 1.1 briggs #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0)
107 1.1 briggs #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0)
108 1.1 briggs #define CLKF_PC(framep) ((framep)->pc)
109 1.1 briggs
110 1.1 briggs /*
111 1.1 briggs * Preempt the current process if in interrupt from user mode,
112 1.1 briggs * or after the current trap/syscall if in system mode.
113 1.1 briggs */
114 1.1 briggs #define need_resched() { want_resched++; aston(); }
115 1.1 briggs
116 1.1 briggs /*
117 1.1 briggs * Give a profiling tick to the current process from the softclock
118 1.1 briggs * interrupt. Request an ast to send us through trap(),
119 1.1 briggs * marking the proc as needing a profiling tick.
120 1.1 briggs */
121 1.1 briggs #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); }
122 1.1 briggs
123 1.1 briggs /*
124 1.1 briggs * Notify the current process (p) that it has a signal pending,
125 1.1 briggs * process as soon as possible.
126 1.1 briggs */
127 1.1 briggs #define signotify(p) aston()
128 1.1 briggs
129 1.1 briggs #define aston() (astpending++)
130 1.1 briggs
131 1.1 briggs int astpending; /* need to trap before returning to user mode */
132 1.1 briggs int want_resched; /* resched() was called */
133 1.1 briggs
134 1.1 briggs /*
135 1.1 briggs * simulated software interrupt register
136 1.1 briggs */
137 1.1 briggs extern unsigned char ssir;
138 1.1 briggs
139 1.1 briggs #define SIR_NET 0x1
140 1.1 briggs #define SIR_CLOCK 0x2
141 1.2 briggs #define SIR_SERIAL 0x4
142 1.1 briggs
143 1.1 briggs #define siroff(x) ssir &= ~(x)
144 1.1 briggs #define setsoftnet() ssir |= SIR_NET
145 1.1 briggs #define setsoftclock() ssir |= SIR_CLOCK
146 1.2 briggs #define setsoftserial() ssir |= SIR_SERIAL
147 1.1 briggs
148 1.1 briggs
149 1.7 briggs /* values for machineid --
150 1.7 briggs * These are equivalent to the MacOS Gestalt values. */
151 1.7 briggs #define MACH_MACII 6
152 1.7 briggs #define MACH_MACIIX 7
153 1.7 briggs #define MACH_MACIICX 8
154 1.2 briggs #define MACH_MACSE30 9
155 1.7 briggs #define MACH_MACIICI 11
156 1.7 briggs #define MACH_MACIIFX 13
157 1.7 briggs #define MACH_MACIISI 18
158 1.5 briggs #define MACH_MACQ900 20
159 1.5 briggs #define MACH_MACPB170 21
160 1.5 briggs #define MACH_MACQ700 22
161 1.7 briggs #define MACH_MACCLASSICII 23
162 1.7 briggs #define MACH_MACPB100 24
163 1.5 briggs #define MACH_MACPB140 25
164 1.7 briggs #define MACH_MACQ950 26
165 1.7 briggs #define MACH_MACLCIII 27
166 1.7 briggs #define MACH_MACPB210 29
167 1.7 briggs #define MACH_MACC650 30
168 1.7 briggs #define MACH_MACPB230 32
169 1.7 briggs #define MACH_MACPB180 33
170 1.7 briggs #define MACH_MACPB160 34
171 1.7 briggs #define MACH_MACQ800 35
172 1.7 briggs #define MACH_MACQ650 36
173 1.6 briggs #define MACH_MACLCII 37
174 1.7 briggs #define MACH_MACPB250 38
175 1.7 briggs #define MACH_MACIIVI 44
176 1.7 briggs #define MACH_MACP600 45
177 1.7 briggs #define MACH_MACIIVX 48
178 1.7 briggs #define MACH_MACCCLASSIC 49
179 1.7 briggs #define MACH_MACPB165C 50
180 1.7 briggs #define MACH_MACC610 52
181 1.7 briggs #define MACH_MACQ610 53
182 1.7 briggs #define MACH_MACPB145 54
183 1.7 briggs #define MACH_MACLC520 56
184 1.7 briggs #define MACH_MACC660AV 60
185 1.7 briggs #define MACH_MACP460 62
186 1.7 briggs #define MACH_MACPB180C 71
187 1.7 briggs #define MACH_MACPB270 77
188 1.7 briggs #define MACH_MACQ840AV 78
189 1.7 briggs #define MACH_MACP550 80
190 1.7 briggs #define MACH_MACPB165 84
191 1.7 briggs #define MACH_MACTV 88
192 1.7 briggs #define MACH_MACLC475 89
193 1.7 briggs #define MACH_MACLC575 92
194 1.7 briggs #define MACH_MACQ605 94
195 1.1 briggs
196 1.1 briggs /* MF processor passed in */
197 1.1 briggs #define MACH_68020 0
198 1.1 briggs #define MACH_68030 1
199 1.1 briggs #define MACH_68040 2
200 1.1 briggs #define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */
201 1.1 briggs
202 1.1 briggs /* values for cpuspeed (not really related to clock speed due to caches) */
203 1.1 briggs #define MHZ_8 1
204 1.1 briggs #define MHZ_16 2
205 1.1 briggs #define MHZ_25 3
206 1.1 briggs #define MHZ_33 4
207 1.1 briggs #define MHZ_40 5
208 1.1 briggs
209 1.1 briggs #ifdef KERNEL
210 1.5 briggs extern int machineid, ectype;
211 1.5 briggs extern char *intiobase, *intiolimit;
212 1.5 briggs extern char *extiobase, *extiolimit;
213 1.5 briggs
214 1.5 briggs extern int mach_processor, mach_memsize;
215 1.5 briggs extern int do_graybars, serial_boot_echo;
216 1.5 briggs extern int booter_version;
217 1.1 briggs #endif
218 1.1 briggs
219 1.1 briggs /* physical memory sections */
220 1.1 briggs #define ROMBASE (0x40000000)
221 1.3 briggs #define INTIOBASE (0x50000000)
222 1.3 briggs #define INTIOTOP (0x51000000) /* ~ 128 K */
223 1.3 briggs #define IIOMAPSIZE btoc(INTIOTOP - INTIOBASE)
224 1.1 briggs
225 1.1 briggs /* ALICE 05/23/92 BG -- These need to be changed. */
226 1.1 briggs #ifdef NO_SUPER_SPACE_YET
227 1.1 briggs #define NBSBASE 0x60000000 /* NUBUS Super space */
228 1.1 briggs #define NBSTOP 0xF0000000
229 1.1 briggs #endif
230 1.1 briggs #define NBBASE 0xF9000000 /* NUBUS space */
231 1.1 briggs #define NBTOP 0xFF000000 /* NUBUS space */
232 1.1 briggs #define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */
233 1.1 briggs #define NBMEMSIZE 0x01000000 /* 16 megs per card */
234 1.1 briggs #define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */
235 1.1 briggs
236 1.1 briggs /*
237 1.1 briggs * IO space:
238 1.1 briggs *
239 1.1 briggs * Internal IO space is mapped in the kernel from ``intiobase'' to
240 1.1 briggs * ``intiolimit'' (defined in locore.s). Since it is always mapped,
241 1.1 briggs * conversion between physical and kernel virtual addresses is easy.
242 1.1 briggs */
243 1.2 briggs #define ISIIOVA(va) \
244 1.2 briggs ((char *)(va) >= intiobase && (char *)(va) < intiolimit)
245 1.2 briggs #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase)
246 1.2 briggs #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE)
247 1.2 briggs #define IIOPOFF(pa) ((int)(pa)-INTIOBASE)
248 1.1 briggs
249 1.1 briggs /*
250 1.1 briggs ALICE 05/24/92,13:25:19 BG -- We need to make sure to map NuBus memory in
251 1.1 briggs the kernel, too.
252 1.1 briggs ALICE 06/29/92,20:40:00 LK -- I did that, thank you very much. Been there.
253 1.1 briggs */
254 1.1 briggs
255 1.1 briggs
256 1.1 briggs /*
257 1.1 briggs * 68851 and 68030 MMU
258 1.1 briggs */
259 1.1 briggs #define PMMU_LVLMASK 0x0007
260 1.1 briggs #define PMMU_INV 0x0400
261 1.1 briggs #define PMMU_WP 0x0800
262 1.1 briggs #define PMMU_ALV 0x1000
263 1.1 briggs #define PMMU_SO 0x2000
264 1.1 briggs #define PMMU_LV 0x4000
265 1.1 briggs #define PMMU_BE 0x8000
266 1.1 briggs #define PMMU_FAULT (PMMU_WP|PMMU_INV)
267 1.1 briggs
268 1.1 briggs /* 680X0 function codes */
269 1.1 briggs #define FC_USERD 1 /* user data space */
270 1.1 briggs #define FC_USERP 2 /* user program space */
271 1.1 briggs #define FC_SUPERD 5 /* supervisor data space */
272 1.1 briggs #define FC_SUPERP 6 /* supervisor program space */
273 1.1 briggs #define FC_CPU 7 /* CPU space */
274 1.1 briggs
275 1.1 briggs /* fields in the 68020 cache control register */
276 1.1 briggs #define IC_ENABLE 0x0001 /* enable instruction cache */
277 1.1 briggs #define IC_FREEZE 0x0002 /* freeze instruction cache */
278 1.1 briggs #define IC_CE 0x0004 /* clear instruction cache entry */
279 1.1 briggs #define IC_CLR 0x0008 /* clear entire instruction cache */
280 1.1 briggs
281 1.1 briggs /* additional fields in the 68030 cache control register */
282 1.1 briggs #define IC_BE 0x0010 /* instruction burst enable */
283 1.1 briggs #define DC_ENABLE 0x0100 /* data cache enable */
284 1.1 briggs #define DC_FREEZE 0x0200 /* data cache freeze */
285 1.1 briggs #define DC_CE 0x0400 /* clear data cache entry */
286 1.1 briggs #define DC_CLR 0x0800 /* clear entire data cache */
287 1.1 briggs #define DC_BE 0x1000 /* data burst enable */
288 1.1 briggs #define DC_WA 0x2000 /* write allocate */
289 1.1 briggs
290 1.1 briggs #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
291 1.1 briggs #define CACHE_OFF (DC_CLR|IC_CLR)
292 1.1 briggs #define CACHE_CLR (CACHE_ON)
293 1.1 briggs #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
294 1.1 briggs #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
295