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cpu.h revision 1.11
      1 /*
      2  * Copyright (c) 1988 University of Utah.
      3  * Copyright (c) 1982, 1990 The Regents of the University of California.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to Berkeley by
      7  * the Systems Programming Group of the University of Utah Computer
      8  * Science Department.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by the University of
     21  *	California, Berkeley and its contributors.
     22  * 4. Neither the name of the University nor the names of its contributors
     23  *    may be used to endorse or promote products derived from this software
     24  *    without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36  * SUCH DAMAGE.
     37  */
     38 
     39 /*
     40  *	Copyright (c) 1992, 1993 BCDL Labs.  All rights reserved.
     41  *	Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot
     42 
     43  *	Redistribution of this source code or any part thereof is permitted,
     44  *	 provided that the following conditions are met:
     45  *	1) Utilized source contains the copyright message above, this list
     46  *	 of conditions, and the following disclaimer.
     47  *	2) Binary objects containing compiled source reproduce the
     48  *	 copyright notice above on startup.
     49  *
     50  *	CAVEAT: This source code is provided "as-is" by BCDL Labs, and any
     51  *	 warranties of ANY kind are disclaimed.  We don't even claim that it
     52  *	 won't crash your hard disk.  Basically, we want a little credit if
     53  *	 it works, but we don't want to get mail-bombed if it doesn't.
     54  */
     55 
     56 /*
     57  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
     58  *
     59  *	from: @(#)cpu.h	7.7 (Berkeley) 6/27/91
     60  *	$Id: cpu.h,v 1.11 1994/06/26 13:25:16 briggs Exp $
     61  */
     62 
     63 /*
     64    ALICE
     65 	BG -- Sat May 23 23:58:23 EDT 1992
     66 	Exported defines and stuff unique to mac68k.
     67    A lot of this stuff is really specific to the m68k, not just the macs,
     68    but there isn't time to do anything about that right now...
     69  */
     70 
     71 #ifndef _MACHINE_CPU_H_
     72 #define _MACHINE_CPU_H_	1
     73 
     74 /*
     75  * definitions of cpu-dependent requirements
     76  * referenced in generic code
     77  */
     78 #define	COPY_SIGCODE		/* copy sigcode above user stack in exec */
     79 
     80 #define	cpu_swapin(p)			/* nothing */
     81 #define	cpu_exec(p)			/* nothing */
     82 #define	cpu_wait(p)			/* nothing */
     83 #define cpu_setstack(p, ap)		(p)->p_md.md_regs[SP] = ap
     84 #define cpu_set_init_frame(p, fp)	(p)->p_md.md_regs = fp
     85 
     86 /*
     87  * Arguments to hardclock, softclock and gatherstats
     88  * encapsulate the previous machine state in an opaque
     89  * clockframe; for hp300, use just what the hardware
     90  * leaves on the stack.
     91  */
     92 
     93 struct clockframe {
     94 	u_short	sr;
     95 	u_long	pc;
     96 	u_short	vo;
     97 };
     98 
     99 #define	CLKF_USERMODE(framep)	(((framep)->sr & PSL_S) == 0)
    100 #define	CLKF_BASEPRI(framep)	(((framep)->sr & PSL_IPL) == 0)
    101 #define	CLKF_PC(framep)		((framep)->pc)
    102 #define	CLKF_INTR(framep)	(0) /* XXX should use PSL_M (see hp300) */
    103 
    104 /*
    105  * Preempt the current process if in interrupt from user mode,
    106  * or after the current trap/syscall if in system mode.
    107  */
    108 #define	need_resched()	{ want_resched++; aston(); }
    109 
    110 /*
    111  * Give a profiling tick to the current process from the softclock
    112  * interrupt.  Request an ast to send us through trap(),
    113  * marking the proc as needing a profiling tick.
    114  */
    115 #define	profile_tick(p, framep)	( (p)->p_flag |= P_OWEUPC, aston() )
    116 #define	need_proftick(p)	( (p)->p_flag |= P_OWEUPC, aston() )
    117 
    118 /*
    119  * Notify the current process (p) that it has a signal pending,
    120  * process as soon as possible.
    121  */
    122 #define	signotify(p)	aston()
    123 
    124 #define aston() (astpending++)
    125 
    126 int	astpending;		/* need to trap before returning to user mode */
    127 int	want_resched;		/* resched() was called */
    128 
    129 /*
    130  * simulated software interrupt register
    131  */
    132 extern unsigned char ssir;
    133 
    134 #define SIR_NET		0x1
    135 #define SIR_CLOCK	0x2
    136 #define SIR_SERIAL	0x4
    137 
    138 #define siroff(x)	ssir &= ~(x)
    139 #define setsoftnet()	ssir |= SIR_NET
    140 #define setsoftclock()	ssir |= SIR_CLOCK
    141 #define setsoftserial()	ssir |= SIR_SERIAL
    142 
    143 #define CPU_CONSDEV	1
    144 #define CPU_MAXID	2
    145 
    146 #define CTL_MACHDEP_NAMES { \
    147 	{ 0, 0 }, \
    148 	{ "console_device", CTLTYPE_STRUCT }, \
    149 }
    150 
    151 /* values for machineid --
    152  * 	These are equivalent to the MacOS Gestalt values. */
    153 #define MACH_MACII		6
    154 #define MACH_MACIIX		7
    155 #define MACH_MACIICX		8
    156 #define MACH_MACSE30		9
    157 #define MACH_MACIICI		11
    158 #define MACH_MACIIFX		13
    159 #define MACH_MACIISI		18
    160 #define MACH_MACQ900		20
    161 #define MACH_MACPB170		21
    162 #define MACH_MACQ700		22
    163 #define MACH_MACCLASSICII	23
    164 #define MACH_MACPB100		24
    165 #define MACH_MACPB140		25
    166 #define MACH_MACQ950		26
    167 #define MACH_MACLCIII		27
    168 #define MACH_MACPB210		29
    169 #define MACH_MACC650		30
    170 #define MACH_MACPB230		32
    171 #define MACH_MACPB180		33
    172 #define MACH_MACPB160		34
    173 #define MACH_MACQ800		35
    174 #define MACH_MACQ650		36
    175 #define MACH_MACLCII		37
    176 #define MACH_MACPB250		38
    177 #define MACH_MACIIVI		44
    178 #define MACH_MACP600		45
    179 #define MACH_MACIIVX		48
    180 #define MACH_MACCCLASSIC	49
    181 #define MACH_MACPB165C		50
    182 #define MACH_MACC610		52
    183 #define MACH_MACQ610		53
    184 #define MACH_MACPB145		54
    185 #define MACH_MACLC520		56
    186 #define MACH_MACC660AV		60
    187 #define MACH_MACP460		62
    188 #define MACH_MACPB180C		71
    189 #define MACH_MACPB270		77
    190 #define MACH_MACQ840AV		78
    191 #define MACH_MACP550		80
    192 #define MACH_MACPB165		84
    193 #define MACH_MACTV		88
    194 #define MACH_MACLC475		89
    195 #define MACH_MACLC575		92
    196 #define MACH_MACQ605		94
    197 
    198 /* MF processor passed in */
    199 #define MACH_68020	0
    200 #define MACH_68030	1
    201 #define MACH_68040	2
    202 #define MACH_PENTIUM	3	/* 66 and 99 MHz versions *only* */
    203 
    204 /* Defines for mmutype */
    205 #define MMU_68851	-1
    206 #define MMU_68030	0
    207 #define MMU_68040	1
    208 
    209 /* values for cpuspeed (not really related to clock speed due to caches) */
    210 #define	MHZ_8		1
    211 #define	MHZ_16		2
    212 #define	MHZ_25		3
    213 #define	MHZ_33		4
    214 #define	MHZ_40		5
    215 
    216 #ifdef KERNEL
    217 extern	unsigned long	IOBase, NuBusBase;
    218 extern	int		machineid;
    219 
    220 extern	int		mach_processor, mach_memsize;
    221 extern	int		do_graybars,    serial_boot_echo;
    222 extern	int		booter_version;
    223 extern	int		mmutype,	cpu040;
    224 extern	unsigned long	load_addr;
    225 #endif
    226 
    227 /* physical memory sections */
    228 #define	ROMBASE		(0x40000000)
    229 #define INTIOBASE	(0x50f00000)
    230 #define INTIOTOP	(0x51000000)	/* ~ 128 K */
    231 #define IIOMAPSIZE	btoc(INTIOTOP - INTIOBASE)
    232 
    233 /* XXX -- Need to do something about superspace. */
    234 #ifdef NO_SUPER_SPACE_YET
    235 #define	NBSBASE		0x60000000	/* NUBUS Super space */
    236 #define	NBSTOP		0xF0000000
    237 #endif
    238 #define NBBASE		0xF9000000	/* NUBUS space */
    239 #define NBTOP		0xFF000000	/* NUBUS space */
    240 #define NBMAPSIZE	btoc(NBTOP-NBBASE)	/* ~ 96 megs */
    241 #define NBMEMSIZE	0x01000000	/* 16 megs per card */
    242 #define NBROMOFFSET	0x00FF0000	/* Last 64K == ROM */
    243 
    244 /*
    245  * 68851 and 68030 MMU
    246  */
    247 #define	PMMU_LVLMASK	0x0007
    248 #define	PMMU_INV	0x0400
    249 #define	PMMU_WP		0x0800
    250 #define	PMMU_ALV	0x1000
    251 #define	PMMU_SO		0x2000
    252 #define	PMMU_LV		0x4000
    253 #define	PMMU_BE		0x8000
    254 #define	PMMU_FAULT	(PMMU_WP|PMMU_INV)
    255 
    256 /* 680X0 function codes */
    257 #define	FC_USERD	1	/* user data space */
    258 #define	FC_USERP	2	/* user program space */
    259 #define	FC_SUPERD	5	/* supervisor data space */
    260 #define	FC_SUPERP	6	/* supervisor program space */
    261 #define	FC_CPU		7	/* CPU space */
    262 
    263 /* fields in the 68020 cache control register */
    264 #define	IC_ENABLE	0x0001	/* enable instruction cache */
    265 #define	IC_FREEZE	0x0002	/* freeze instruction cache */
    266 #define	IC_CE		0x0004	/* clear instruction cache entry */
    267 #define	IC_CLR		0x0008	/* clear entire instruction cache */
    268 
    269 /* additional fields in the 68030 cache control register */
    270 #define	IC_BE		0x0010	/* instruction burst enable */
    271 #define	DC_ENABLE	0x0100	/* data cache enable */
    272 #define	DC_FREEZE	0x0200	/* data cache freeze */
    273 #define	DC_CE		0x0400	/* clear data cache entry */
    274 #define	DC_CLR		0x0800	/* clear entire data cache */
    275 #define	DC_BE		0x1000	/* data burst enable */
    276 #define	DC_WA		0x2000	/* write allocate */
    277 
    278 /* fields in the 68040 cache control register */
    279 #define IC40_ENABLE	0x00008000	/* enable instruction cache */
    280 #define DC40_ENABLE	0x80000000	/* enable data cache */
    281 
    282 #define	CACHE_ON	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    283 #define	CACHE_OFF	(DC_CLR|IC_CLR)
    284 #define	CACHE_CLR	(CACHE_ON)
    285 #define	IC_CLEAR	(DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    286 #define	DC_CLEAR	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
    287 
    288 /* 68040 cache control */
    289 #define CACHE40_ON	(IC40_ENABLE|DC40_ENABLE)
    290 #define CACHE40_OFF	0x00000000
    291 
    292 #endif	/* !_MACHINE_CPU_H_ */
    293