cpu.h revision 1.29 1 /* $NetBSD: cpu.h,v 1.29 1996/05/05 06:17:36 briggs Exp $ */
2
3 /*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1982, 1990 The Regents of the University of California.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 */
40
41 /*
42 * Copyright (c) 1992, 1993 BCDL Labs. All rights reserved.
43 * Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot
44
45 * Redistribution of this source code or any part thereof is permitted,
46 * provided that the following conditions are met:
47 * 1) Utilized source contains the copyright message above, this list
48 * of conditions, and the following disclaimer.
49 * 2) Binary objects containing compiled source reproduce the
50 * copyright notice above on startup.
51 *
52 * CAVEAT: This source code is provided "as-is" by BCDL Labs, and any
53 * warranties of ANY kind are disclaimed. We don't even claim that it
54 * won't crash your hard disk. Basically, we want a little credit if
55 * it works, but we don't want to get mail-bombed if it doesn't.
56 */
57
58 /*
59 * from: Utah $Hdr: cpu.h 1.16 91/03/25$
60 *
61 * @(#)cpu.h 7.7 (Berkeley) 6/27/91
62 */
63
64 /*
65 ALICE
66 BG -- Sat May 23 23:58:23 EDT 1992
67 Exported defines and stuff unique to mac68k.
68 A lot of this stuff is really specific to the m68k, not just the macs,
69 but there isn't time to do anything about that right now...
70 */
71
72 #ifndef _CPU_MACHINE_
73 #define _CPU_MACHINE_
74
75 /*
76 * definitions of cpu-dependent requirements
77 * referenced in generic code
78 */
79 #define cpu_swapin(p) /* nothing */
80 #define cpu_wait(p) /* nothing */
81 #define cpu_swapout(p) /* nothing */
82 void cpu_set_kpc __P((struct proc *, void (*)(struct proc *)));
83
84 /*
85 * Arguments to hardclock, softclock and gatherstats
86 * encapsulate the previous machine state in an opaque
87 * clockframe; for hp300, use just what the hardware
88 * leaves on the stack.
89 */
90
91 struct clockframe {
92 u_short sr;
93 u_long pc;
94 u_short vo;
95 };
96
97 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
98 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
99 #define CLKF_PC(framep) ((framep)->pc)
100 #define CLKF_INTR(framep) (0) /* XXX should use PSL_M (see hp300) */
101
102 /*
103 * Preempt the current process if in interrupt from user mode,
104 * or after the current trap/syscall if in system mode.
105 */
106 #define need_resched() { want_resched++; aston(); }
107
108 /*
109 * Give a profiling tick to the current process from the softclock
110 * interrupt. Request an ast to send us through trap(),
111 * marking the proc as needing a profiling tick.
112 */
113 #define need_proftick(p) ( (p)->p_flag |= P_OWEUPC, aston() )
114
115 /*
116 * Notify the current process (p) that it has a signal pending,
117 * process as soon as possible.
118 */
119 #define signotify(p) aston()
120
121 #define aston() (astpending++)
122
123 int astpending; /* need to trap before returning to user mode */
124 int want_resched; /* resched() was called */
125
126 /*
127 * simulated software interrupt register
128 */
129 extern unsigned char ssir;
130
131 #define SIR_NET 0x1
132 #define SIR_CLOCK 0x2
133 #define SIR_SERIAL 0x4
134
135 #define siroff(x) ssir &= ~(x)
136 #define setsoftnet() ssir |= SIR_NET
137 #define setsoftclock() ssir |= SIR_CLOCK
138 #define setsoftserial() ssir |= SIR_SERIAL
139
140 #define CPU_CONSDEV 1
141 #define CPU_MAXID 2
142
143 #define CTL_MACHDEP_NAMES { \
144 { 0, 0 }, \
145 { "console_device", CTLTYPE_STRUCT }, \
146 }
147
148 /* values for machineid --
149 * These are equivalent to the MacOS Gestalt values. */
150 #define MACH_MACII 6
151 #define MACH_MACIIX 7
152 #define MACH_MACIICX 8
153 #define MACH_MACSE30 9
154 #define MACH_MACIICI 11
155 #define MACH_MACIIFX 13
156 #define MACH_MACIISI 18
157 #define MACH_MACQ900 20
158 #define MACH_MACPB170 21
159 #define MACH_MACQ700 22
160 #define MACH_MACCLASSICII 23
161 #define MACH_MACPB100 24
162 #define MACH_MACPB140 25
163 #define MACH_MACQ950 26
164 #define MACH_MACLCIII 27
165 #define MACH_MACPB210 29
166 #define MACH_MACC650 30
167 #define MACH_MACPB230 32
168 #define MACH_MACPB180 33
169 #define MACH_MACPB160 34
170 #define MACH_MACQ800 35
171 #define MACH_MACQ650 36
172 #define MACH_MACLCII 37
173 #define MACH_MACPB250 38
174 #define MACH_MACIIVI 44
175 #define MACH_MACP600 45
176 #define MACH_MACIIVX 48
177 #define MACH_MACCCLASSIC 49
178 #define MACH_MACPB165C 50
179 #define MACH_MACC610 52
180 #define MACH_MACQ610 53
181 #define MACH_MACPB145 54
182 #define MACH_MACLC520 56
183 #define MACH_MACC660AV 60
184 #define MACH_MACP460 62
185 #define MACH_MACPB180C 71
186 #define MACH_MACPB270 77
187 #define MACH_MACQ840AV 78
188 #define MACH_MACP550 80
189 #define MACH_MACPB165 84
190 #define MACH_MACTV 88
191 #define MACH_MACLC475 89
192 #define MACH_MACLC575 92
193 #define MACH_MACQ605 94
194 #define MACH_MACQ630 98
195 #define MACH_MACPB280 102
196 #define MACH_MACPB280C 103
197 #define MACH_MACPB150 115
198
199 /*
200 * Machine classes. These define subsets of the above machines.
201 */
202 #define MACH_CLASSH 0x0000 /* Hopeless cases... */
203 #define MACH_CLASSII 0x0001 /* MacII class */
204 #define MACH_CLASSIIci 0x0004 /* Have RBV, but no Egret */
205 #define MACH_CLASSIIsi 0x0005 /* Similar to IIci -- Have Egret. */
206 #define MACH_CLASSIIvx 0x0006 /* Similar to IIsi -- different via2 emul? */
207 #define MACH_CLASSLC 0x0007 /* Low-Cost/Performa/Wal-Mart Macs. */
208 #define MACH_CLASSPB 0x0008 /* Powerbooks. Power management. */
209 #define MACH_CLASSIIfx 0x0080 /* The IIfx is in a class by itself. */
210 #define MACH_CLASSQ 0x0100 /* Centris/Quadras. */
211
212 #define MACH_68020 0
213 #define MACH_68030 1
214 #define MACH_68040 2
215 #define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */
216
217 /* Defines for mmutype */
218 #define MMU_68040 -2
219 #define MMU_68030 -1
220 /* #define MMU_HP 0 Just a reminder as to where this came from. */
221 #define MMU_68851 1
222
223 #ifdef _KERNEL
224 struct mac68k_machine_S {
225 int cpu_model_index;
226 /*
227 * Misc. info from booter.
228 */
229 int machineid;
230 int mach_processor;
231 int mach_memsize;
232 int booter_version;
233 /*
234 * Debugging flags.
235 */
236 int do_graybars;
237 int serial_boot_echo;
238 int serial_console;
239 /*
240 * Misc. hardware info.
241 */
242 int scsi80; /* Has NCR 5380 */
243 int scsi96; /* Has NCR 53C96 */
244 int scsi96_2; /* Has 2nd 53C96 */
245 int sonic; /* Has SONIC e-net */
246
247 int sccClkConst; /* "Constant" for SCC bps */
248 };
249
250 /* What kind of model is this */
251 struct cpu_model_info {
252 int machineid; /* MacOS Gestalt value. */
253 char *model_major; /* Make this distinction to save a few */
254 char *model_minor; /* bytes--might be useful, too. */
255 int class; /* Rough class of machine. */
256 /* forwarded romvec_s is defined in mac68k/macrom.h */
257 struct romvec_s *rom_vectors; /* Pointer to our known rom vectors */
258 };
259 extern struct cpu_model_info *current_mac_model;
260
261 extern unsigned long IOBase; /* Base address of I/O */
262 extern unsigned long NuBusBase; /* Base address of NuBus */
263
264 extern struct mac68k_machine_S mac68k_machine;
265 extern int mmutype ;
266 extern unsigned long load_addr;
267 #endif /* _KERNEL */
268
269 /* physical memory sections */
270 #define ROMBASE (0x40800000)
271 #define ROMLEN (0x00100000) /* 1MB will work for all 68k */
272 #define ROMMAPSIZE btoc(ROMLEN) /* 16k of page tables. */
273
274 #define IIOMAPSIZE btoc(0x00100000) /* 1MB should be enough */
275
276 /* XXX -- Need to do something about superspace.
277 * Technically, NuBus superspace starts at 0x60000000, but no
278 * known Macintosh has used any slot lower numbered than 9, and
279 * the super space is defined as 0xS000 0000 through 0xSFFF FFFF
280 * where S is the slot number--ranging from 0x9 - 0xE.
281 */
282 #define NBSBASE 0x90000000
283 #define NBSTOP 0xF0000000
284 #define NBBASE 0xF9000000 /* NUBUS space */
285 #define NBTOP 0xFF000000 /* NUBUS space */
286 #define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */
287 #define NBMEMSIZE 0x01000000 /* 16 megs per card */
288 #define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */
289
290 /*
291 * 68851 and 68030 MMU
292 */
293 #define PMMU_LVLMASK 0x0007
294 #define PMMU_INV 0x0400
295 #define PMMU_WP 0x0800
296 #define PMMU_ALV 0x1000
297 #define PMMU_SO 0x2000
298 #define PMMU_LV 0x4000
299 #define PMMU_BE 0x8000
300 #define PMMU_FAULT (PMMU_WP|PMMU_INV)
301
302 /*
303 * 68040 MMU
304 */
305 #define MMU4_RES 0x001
306 #define MMU4_TTR 0x002
307 #define MMU4_WP 0x004
308 #define MMU4_MOD 0x010
309 #define MMU4_CMMASK 0x060
310 #define MMU4_SUP 0x080
311 #define MMU4_U0 0x100
312 #define MMU4_U1 0x200
313 #define MMU4_GLB 0x400
314 #define MMU4_BE 0x800
315
316 /* 680X0 function codes */
317 #define FC_USERD 1 /* user data space */
318 #define FC_USERP 2 /* user program space */
319 #define FC_SUPERD 5 /* supervisor data space */
320 #define FC_SUPERP 6 /* supervisor program space */
321 #define FC_CPU 7 /* CPU space */
322
323 /* fields in the 68020 cache control register */
324 #define IC_ENABLE 0x0001 /* enable instruction cache */
325 #define IC_FREEZE 0x0002 /* freeze instruction cache */
326 #define IC_CE 0x0004 /* clear instruction cache entry */
327 #define IC_CLR 0x0008 /* clear entire instruction cache */
328
329 /* additional fields in the 68030 cache control register */
330 #define IC_BE 0x0010 /* instruction burst enable */
331 #define DC_ENABLE 0x0100 /* data cache enable */
332 #define DC_FREEZE 0x0200 /* data cache freeze */
333 #define DC_CE 0x0400 /* clear data cache entry */
334 #define DC_CLR 0x0800 /* clear entire data cache */
335 #define DC_BE 0x1000 /* data burst enable */
336 #define DC_WA 0x2000 /* write allocate */
337
338 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
339 #define CACHE_OFF (DC_CLR|IC_CLR)
340 #define CACHE_CLR (CACHE_ON)
341 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
342 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
343
344 /* 68040 cache control register */
345 #define IC4_ENABLE 0x00008000 /* enable instruction cache */
346 #define DC4_ENABLE 0x80000000 /* enable data cache */
347
348 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE)
349 #define CACHE4_OFF 0x00000000
350
351 #endif /* _CPU_MACHINE_ */
352