cpu.h revision 1.34.4.4
1 /* $NetBSD: cpu.h,v 1.34.4.4 1996/07/10 18:09:51 scottr Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 */ 40 41 /* 42 * Copyright (c) 1992, 1993 BCDL Labs. All rights reserved. 43 * Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot 44 45 * Redistribution of this source code or any part thereof is permitted, 46 * provided that the following conditions are met: 47 * 1) Utilized source contains the copyright message above, this list 48 * of conditions, and the following disclaimer. 49 * 2) Binary objects containing compiled source reproduce the 50 * copyright notice above on startup. 51 * 52 * CAVEAT: This source code is provided "as-is" by BCDL Labs, and any 53 * warranties of ANY kind are disclaimed. We don't even claim that it 54 * won't crash your hard disk. Basically, we want a little credit if 55 * it works, but we don't want to get mail-bombed if it doesn't. 56 */ 57 58 /* 59 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 60 * 61 * @(#)cpu.h 7.7 (Berkeley) 6/27/91 62 */ 63 64 /* 65 ALICE 66 BG -- Sat May 23 23:58:23 EDT 1992 67 Exported defines and stuff unique to mac68k. 68 A lot of this stuff is really specific to the m68k, not just the macs, 69 but there isn't time to do anything about that right now... 70 */ 71 72 #ifndef _CPU_MACHINE_ 73 #define _CPU_MACHINE_ 74 75 #include <machine/pcb.h> 76 77 /* 78 * definitions of cpu-dependent requirements 79 * referenced in generic code 80 */ 81 #define cpu_swapin(p) /* nothing */ 82 #define cpu_wait(p) /* nothing */ 83 #define cpu_swapout(p) /* nothing */ 84 void cpu_set_kpc __P((struct proc *, void (*)(struct proc *))); 85 86 /* 87 * Arguments to hardclock, softclock and gatherstats 88 * encapsulate the previous machine state in an opaque 89 * clockframe; for hp300, use just what the hardware 90 * leaves on the stack. 91 */ 92 93 struct clockframe { 94 u_short sr; 95 u_long pc; 96 u_short vo; 97 }; 98 99 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 100 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 101 #define CLKF_PC(framep) ((framep)->pc) 102 #define CLKF_INTR(framep) (0) /* XXX should use PSL_M (see hp300) */ 103 104 /* 105 * Preempt the current process if in interrupt from user mode, 106 * or after the current trap/syscall if in system mode. 107 */ 108 #define need_resched() { want_resched++; aston(); } 109 110 /* 111 * Give a profiling tick to the current process from the softclock 112 * interrupt. Request an ast to send us through trap(), 113 * marking the proc as needing a profiling tick. 114 */ 115 #define need_proftick(p) ( (p)->p_flag |= P_OWEUPC, aston() ) 116 117 /* 118 * Notify the current process (p) that it has a signal pending, 119 * process as soon as possible. 120 */ 121 #define signotify(p) aston() 122 123 #define aston() (astpending++) 124 125 int astpending; /* need to trap before returning to user mode */ 126 int want_resched; /* resched() was called */ 127 128 /* 129 * simulated software interrupt register 130 */ 131 extern volatile unsigned char ssir; 132 133 #define SIR_NET 0x1 134 #define SIR_CLOCK 0x2 135 #define SIR_SERIAL 0x4 136 137 #define siroff(x) \ 138 { asm volatile ("andb %0,%1" : : "di" ((u_char)~(x)), "g" (ssir)); } 139 140 #define setsoftnet() \ 141 asm volatile ("orb %0,%1" : : "di" ((u_char)SIR_NET), "g" (ssir)) 142 #define setsoftclock() \ 143 asm volatile ("orb %0,%1" : : "di" ((u_char)SIR_CLOCK), "g" (ssir)) 144 #define setsoftserial() \ 145 asm volatile ("orb %0,%1" : : "di" ((u_char)SIR_SERIAL), "g" (ssir)) 146 147 #define CPU_CONSDEV 1 148 #define CPU_MAXID 2 149 150 #define CTL_MACHDEP_NAMES { \ 151 { 0, 0 }, \ 152 { "console_device", CTLTYPE_STRUCT }, \ 153 } 154 155 /* values for machineid -- 156 * These are equivalent to the MacOS Gestalt values. */ 157 #define MACH_MACII 6 158 #define MACH_MACIIX 7 159 #define MACH_MACIICX 8 160 #define MACH_MACSE30 9 161 #define MACH_MACIICI 11 162 #define MACH_MACIIFX 13 163 #define MACH_MACIISI 18 164 #define MACH_MACQ900 20 165 #define MACH_MACPB170 21 166 #define MACH_MACQ700 22 167 #define MACH_MACCLASSICII 23 168 #define MACH_MACPB100 24 169 #define MACH_MACPB140 25 170 #define MACH_MACQ950 26 171 #define MACH_MACLCIII 27 172 #define MACH_MACPB210 29 173 #define MACH_MACC650 30 174 #define MACH_MACPB230 32 175 #define MACH_MACPB180 33 176 #define MACH_MACPB160 34 177 #define MACH_MACQ800 35 178 #define MACH_MACQ650 36 179 #define MACH_MACLCII 37 180 #define MACH_MACPB250 38 181 #define MACH_MACIIVI 44 182 #define MACH_MACP600 45 183 #define MACH_MACIIVX 48 184 #define MACH_MACCCLASSIC 49 185 #define MACH_MACPB165C 50 186 #define MACH_MACC610 52 187 #define MACH_MACQ610 53 188 #define MACH_MACPB145 54 189 #define MACH_MACLC520 56 190 #define MACH_MACC660AV 60 191 #define MACH_MACP460 62 192 #define MACH_MACPB180C 71 193 #define MACH_MACPB500 72 194 #define MACH_MACPB270 77 195 #define MACH_MACQ840AV 78 196 #define MACH_MACP550 80 197 #define MACH_MACPB165 84 198 #define MACH_MACTV 88 199 #define MACH_MACLC475 89 200 #define MACH_MACLC575 92 201 #define MACH_MACQ605 94 202 #define MACH_MACQ630 98 203 #define MACH_MACPB280 102 204 #define MACH_MACPB280C 103 205 #define MACH_MACPB150 115 206 207 /* 208 * Machine classes. These define subsets of the above machines. 209 */ 210 #define MACH_CLASSH 0x0000 /* Hopeless cases... */ 211 #define MACH_CLASSII 0x0001 /* MacII class */ 212 #define MACH_CLASSIIci 0x0004 /* Have RBV, but no Egret */ 213 #define MACH_CLASSIIsi 0x0005 /* Similar to IIci -- Have Egret. */ 214 #define MACH_CLASSIIvx 0x0006 /* Similar to IIsi -- different via2 emul? */ 215 #define MACH_CLASSLC 0x0007 /* Low-Cost/Performa/Wal-Mart Macs. */ 216 #define MACH_CLASSPB 0x0008 /* Powerbooks. Power management. */ 217 #define MACH_CLASSDUO 0x0009 /* Powerbooks Duos. More integration/Docks. */ 218 #define MACH_CLASSIIfx 0x0080 /* The IIfx is in a class by itself. */ 219 #define MACH_CLASSQ 0x0100 /* non-A/V Centris/Quadras. */ 220 #define MACH_CLASSAV 0x0101 /* A/V Centris/Quadras. */ 221 222 #define MACH_68020 0 223 #define MACH_68030 1 224 #define MACH_68040 2 225 #define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */ 226 227 /* Defines for mmutype */ 228 #define MMU_68040 -2 229 #define MMU_68030 -1 230 /* #define MMU_HP 0 Just a reminder as to where this came from. */ 231 #define MMU_68851 1 232 233 #ifdef _KERNEL 234 struct mac68k_machine_S { 235 int cpu_model_index; 236 /* 237 * Misc. info from booter. 238 */ 239 int machineid; 240 int mach_processor; 241 int mach_memsize; 242 int booter_version; 243 /* 244 * Debugging flags. 245 */ 246 int do_graybars; 247 int serial_boot_echo; 248 int serial_console; 249 int modem_flags; 250 int modem_cts_clk; 251 int modem_dcd_clk; 252 int print_flags; 253 int print_cts_clk; 254 int print_dcd_clk; 255 /* 256 * Misc. hardware info. 257 */ 258 int scsi80; /* Has NCR 5380 */ 259 int scsi96; /* Has NCR 53C96 */ 260 int scsi96_2; /* Has 2nd 53C96 */ 261 int sonic; /* Has SONIC e-net */ 262 263 int sccClkConst; /* "Constant" for SCC bps */ 264 }; 265 266 /* What kind of model is this */ 267 struct cpu_model_info { 268 int machineid; /* MacOS Gestalt value. */ 269 char *model_major; /* Make this distinction to save a few */ 270 char *model_minor; /* bytes--might be useful, too. */ 271 int class; /* Rough class of machine. */ 272 /* forwarded romvec_s is defined in mac68k/macrom.h */ 273 struct romvec_s *rom_vectors; /* Pointer to our known rom vectors */ 274 }; 275 extern struct cpu_model_info *current_mac_model; 276 277 extern unsigned long IOBase; /* Base address of I/O */ 278 extern unsigned long NuBusBase; /* Base address of NuBus */ 279 280 extern struct mac68k_machine_S mac68k_machine; 281 extern int mmutype ; 282 extern unsigned long load_addr; 283 #endif /* _KERNEL */ 284 285 /* physical memory sections */ 286 #define ROMBASE (0x40800000) 287 #define ROMLEN (0x00200000) /* 2MB will work for all 68k */ 288 #define ROMMAPSIZE btoc(ROMLEN) /* 32k of page tables. */ 289 290 #define IIOMAPSIZE btoc(0x00100000) /* 1MB should be enough */ 291 292 /* XXX -- Need to do something about superspace. 293 * Technically, NuBus superspace starts at 0x60000000, but no 294 * known Macintosh has used any slot lower numbered than 9, and 295 * the super space is defined as 0xS000 0000 through 0xSFFF FFFF 296 * where S is the slot number--ranging from 0x9 - 0xE. 297 */ 298 #define NBSBASE 0x90000000 299 #define NBSTOP 0xF0000000 300 #define NBBASE 0xF9000000 /* NUBUS space */ 301 #define NBTOP 0xFF000000 /* NUBUS space */ 302 #define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */ 303 #define NBMEMSIZE 0x01000000 /* 16 megs per card */ 304 #define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */ 305 306 /* 307 * 68851 and 68030 MMU 308 */ 309 #define PMMU_LVLMASK 0x0007 310 #define PMMU_INV 0x0400 311 #define PMMU_WP 0x0800 312 #define PMMU_ALV 0x1000 313 #define PMMU_SO 0x2000 314 #define PMMU_LV 0x4000 315 #define PMMU_BE 0x8000 316 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 317 318 /* 319 * 68040 MMU 320 */ 321 #define MMU4_RES 0x001 322 #define MMU4_TTR 0x002 323 #define MMU4_WP 0x004 324 #define MMU4_MOD 0x010 325 #define MMU4_CMMASK 0x060 326 #define MMU4_SUP 0x080 327 #define MMU4_U0 0x100 328 #define MMU4_U1 0x200 329 #define MMU4_GLB 0x400 330 #define MMU4_BE 0x800 331 332 /* 680X0 function codes */ 333 #define FC_USERD 1 /* user data space */ 334 #define FC_USERP 2 /* user program space */ 335 #define FC_SUPERD 5 /* supervisor data space */ 336 #define FC_SUPERP 6 /* supervisor program space */ 337 #define FC_CPU 7 /* CPU space */ 338 339 /* fields in the 68020 cache control register */ 340 #define IC_ENABLE 0x0001 /* enable instruction cache */ 341 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 342 #define IC_CE 0x0004 /* clear instruction cache entry */ 343 #define IC_CLR 0x0008 /* clear entire instruction cache */ 344 345 /* additional fields in the 68030 cache control register */ 346 #define IC_BE 0x0010 /* instruction burst enable */ 347 #define DC_ENABLE 0x0100 /* data cache enable */ 348 #define DC_FREEZE 0x0200 /* data cache freeze */ 349 #define DC_CE 0x0400 /* clear data cache entry */ 350 #define DC_CLR 0x0800 /* clear entire data cache */ 351 #define DC_BE 0x1000 /* data burst enable */ 352 #define DC_WA 0x2000 /* write allocate */ 353 354 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 355 #define CACHE_OFF (DC_CLR|IC_CLR) 356 #define CACHE_CLR (CACHE_ON) 357 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 358 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 359 360 /* 68040 cache control register */ 361 #define IC4_ENABLE 0x00008000 /* enable instruction cache */ 362 #define DC4_ENABLE 0x80000000 /* enable data cache */ 363 364 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 365 #define CACHE4_OFF 0x00000000 366 367 __BEGIN_DECLS 368 /* machdep.c */ 369 u_int get_mapping __P((void)); 370 371 /* locore.s */ 372 void m68881_restore __P((struct fpframe *)); 373 void m68881_save __P((struct fpframe *)); 374 u_int getsfc __P((void)); 375 u_int getdfc __P((void)); 376 void TBIA __P((void)); 377 void TBIAS __P((void)); 378 void TBIS __P((vm_offset_t)); 379 void DCFP __P((vm_offset_t)); 380 void ICPP __P((vm_offset_t)); 381 void DCIU __P((void)); 382 void ICIA __P((void)); 383 void DCFL __P((vm_offset_t)); 384 int suline __P((caddr_t, caddr_t)); 385 int susword __P((caddr_t, u_int)); 386 void savectx __P((struct pcb *)); 387 void proc_trampoline __P((void)); 388 389 /* trap.c */ 390 void child_return __P((struct proc *, struct frame)); 391 392 __END_DECLS 393 394 #endif /* _CPU_MACHINE_ */ 395
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