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cpu.h revision 1.8
      1 /*
      2  * Copyright (c) 1988 University of Utah.
      3  * Copyright (c) 1982, 1990 The Regents of the University of California.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to Berkeley by
      7  * the Systems Programming Group of the University of Utah Computer
      8  * Science Department.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by the University of
     21  *	California, Berkeley and its contributors.
     22  * 4. Neither the name of the University nor the names of its contributors
     23  *    may be used to endorse or promote products derived from this software
     24  *    without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36  * SUCH DAMAGE.
     37  */
     38 
     39 /*
     40  *	Copyright (c) 1992, 1993 BCDL Labs.  All rights reserved.
     41  *	Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot
     42 
     43  *	Redistribution of this source code or any part thereof is permitted,
     44  *	 provided that the following conditions are met:
     45  *	1) Utilized source contains the copyright message above, this list
     46  *	 of conditions, and the following disclaimer.
     47  *	2) Binary objects containing compiled source reproduce the
     48  *	 copyright notice above on startup.
     49  *
     50  *	CAVEAT: This source code is provided "as-is" by BCDL Labs, and any
     51  *	 warranties of ANY kind are disclaimed.  We don't even claim that it
     52  *	 won't crash your hard disk.  Basically, we want a little credit if
     53  *	 it works, but we don't want to get mail-bombed if it doesn't.
     54  */
     55 
     56 /*
     57  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
     58  *
     59  *	from: @(#)cpu.h	7.7 (Berkeley) 6/27/91
     60  *	$Id: cpu.h,v 1.8 1994/04/21 23:18:55 briggs Exp $
     61  */
     62 
     63 /*
     64    ALICE
     65 	BG -- Sat May 23 23:58:23 EDT 1992
     66 	Exported defines and stuff unique to mac68k.
     67    A lot of this stuff is really specific to the m68k, not just the macs,
     68    but there isn't time to do anything about that right now...
     69  */
     70 
     71 #ifndef _MACHINE_CPU_H_
     72 #define _MACHINE_CPU_H_	1
     73 
     74 /*
     75  * definitions of cpu-dependent requirements
     76  * referenced in generic code
     77  */
     78 #define	COPY_SIGCODE		/* copy sigcode above user stack in exec */
     79 
     80 /*
     81  * function vs. inline configuration;
     82  * these are defined to get generic functions
     83  * rather than inline or machine-dependent implementations
     84  */
     85 #define	NEED_MINMAX		/* need {,i,l,ul}{min,max} functions */
     86 #undef	NEED_FFS		/* don't need ffs function */
     87 #undef	NEED_BCMP		/* don't need bcmp function */
     88 #undef	NEED_STRLEN		/* don't need strlen function */
     89 
     90 #define	cpu_exec(p)	/* nothing */
     91 #define	cpu_wait(p)	/* nothing */
     92 
     93 /*
     94  * Arguments to hardclock, softclock and gatherstats
     95  * encapsulate the previous machine state in an opaque
     96  * clockframe; for hp300, use just what the hardware
     97  * leaves on the stack.
     98  */
     99 
    100 typedef struct intrframe {
    101 	int	ps;
    102 	int	pc;
    103 } clockframe;
    104 
    105 #define	CLKF_USERMODE(framep)	(((framep)->ps & PSL_S) == 0)
    106 #define	CLKF_BASEPRI(framep)	(((framep)->ps & PSL_IPL7) == 0)
    107 #define	CLKF_PC(framep)		((framep)->pc)
    108 
    109 /*
    110  * Preempt the current process if in interrupt from user mode,
    111  * or after the current trap/syscall if in system mode.
    112  */
    113 #define	need_resched()	{ want_resched++; aston(); }
    114 
    115 /*
    116  * Give a profiling tick to the current process from the softclock
    117  * interrupt.  Request an ast to send us through trap(),
    118  * marking the proc as needing a profiling tick.
    119  */
    120 #define	profile_tick(p, framep)	{ (p)->p_flag |= SOWEUPC; aston(); }
    121 
    122 /*
    123  * Notify the current process (p) that it has a signal pending,
    124  * process as soon as possible.
    125  */
    126 #define	signotify(p)	aston()
    127 
    128 #define aston() (astpending++)
    129 
    130 int	astpending;		/* need to trap before returning to user mode */
    131 int	want_resched;		/* resched() was called */
    132 
    133 /*
    134  * simulated software interrupt register
    135  */
    136 extern unsigned char ssir;
    137 
    138 #define SIR_NET		0x1
    139 #define SIR_CLOCK	0x2
    140 #define SIR_SERIAL	0x4
    141 
    142 #define siroff(x)	ssir &= ~(x)
    143 #define setsoftnet()	ssir |= SIR_NET
    144 #define setsoftclock()	ssir |= SIR_CLOCK
    145 #define setsoftserial()	ssir |= SIR_SERIAL
    146 
    147 
    148 /* values for machineid --
    149  * 	These are equivalent to the MacOS Gestalt values. */
    150 #define MACH_MACII		6
    151 #define MACH_MACIIX		7
    152 #define MACH_MACIICX		8
    153 #define MACH_MACSE30		9
    154 #define MACH_MACIICI		11
    155 #define MACH_MACIIFX		13
    156 #define MACH_MACIISI		18
    157 #define MACH_MACQ900		20
    158 #define MACH_MACPB170		21
    159 #define MACH_MACQ700		22
    160 #define MACH_MACCLASSICII	23
    161 #define MACH_MACPB100		24
    162 #define MACH_MACPB140		25
    163 #define MACH_MACQ950		26
    164 #define MACH_MACLCIII		27
    165 #define MACH_MACPB210		29
    166 #define MACH_MACC650		30
    167 #define MACH_MACPB230		32
    168 #define MACH_MACPB180		33
    169 #define MACH_MACPB160		34
    170 #define MACH_MACQ800		35
    171 #define MACH_MACQ650		36
    172 #define MACH_MACLCII		37
    173 #define MACH_MACPB250		38
    174 #define MACH_MACIIVI		44
    175 #define MACH_MACP600		45
    176 #define MACH_MACIIVX		48
    177 #define MACH_MACCCLASSIC	49
    178 #define MACH_MACPB165C		50
    179 #define MACH_MACC610		52
    180 #define MACH_MACQ610		53
    181 #define MACH_MACPB145		54
    182 #define MACH_MACLC520		56
    183 #define MACH_MACC660AV		60
    184 #define MACH_MACP460		62
    185 #define MACH_MACPB180C		71
    186 #define MACH_MACPB270		77
    187 #define MACH_MACQ840AV		78
    188 #define MACH_MACP550		80
    189 #define MACH_MACPB165		84
    190 #define MACH_MACTV		88
    191 #define MACH_MACLC475		89
    192 #define MACH_MACLC575		92
    193 #define MACH_MACQ605		94
    194 
    195 /* MF processor passed in */
    196 #define MACH_68020	0
    197 #define MACH_68030	1
    198 #define MACH_68040	2
    199 #define MACH_PENTIUM	3	/* 66 and 99 MHz versions *only* */
    200 
    201 /* Defines for mmutype */
    202 #define MMU_68851	-1
    203 #define MMU_68030	0
    204 #define MMU_68040	1
    205 
    206 /* values for cpuspeed (not really related to clock speed due to caches) */
    207 #define	MHZ_8		1
    208 #define	MHZ_16		2
    209 #define	MHZ_25		3
    210 #define	MHZ_33		4
    211 #define	MHZ_40		5
    212 
    213 #ifdef KERNEL
    214 extern	int	machineid,  ectype;
    215 extern	char	*intiobase, *intiolimit;
    216 extern	char	*extiobase, *extiolimit;
    217 
    218 extern	int	mach_processor, mach_memsize;
    219 extern	int	do_graybars,    serial_boot_echo;
    220 extern	int	booter_version;
    221 #endif
    222 
    223 /* physical memory sections */
    224 #define	ROMBASE		(0x40000000)
    225 #define INTIOBASE	(0x50000000)
    226 #define INTIOTOP	(0x51000000)	/* ~ 128 K */
    227 #define IIOMAPSIZE	btoc(INTIOTOP - INTIOBASE)
    228 
    229 /* ALICE 05/23/92 BG -- These need to be changed. */
    230 #ifdef NO_SUPER_SPACE_YET
    231 #define	NBSBASE		0x60000000	/* NUBUS Super space */
    232 #define	NBSTOP		0xF0000000
    233 #endif
    234 #define NBBASE		0xF9000000	/* NUBUS space */
    235 #define NBTOP		0xFF000000	/* NUBUS space */
    236 #define NBMAPSIZE	btoc(NBTOP-NBBASE)	/* ~ 96 megs */
    237 #define NBMEMSIZE	0x01000000	/* 16 megs per card */
    238 #define NBROMOFFSET	0x00FF0000	/* Last 64K == ROM */
    239 
    240 /*
    241  * IO space:
    242  *
    243  * Internal IO space is mapped in the kernel from ``intiobase'' to
    244  * ``intiolimit'' (defined in locore.s).  Since it is always mapped,
    245  * conversion between physical and kernel virtual addresses is easy.
    246  */
    247 #define	ISIIOVA(va) \
    248 	((char *)(va) >= intiobase && (char *)(va) < intiolimit)
    249 #define	IIOV(pa)	((int)(pa)-INTIOBASE+(int)intiobase)
    250 #define	IIOP(va)	((int)(va)-(int)intiobase+INTIOBASE)
    251 #define	IIOPOFF(pa)	((int)(pa)-INTIOBASE)
    252 
    253 /*
    254    ALICE 05/24/92,13:25:19 BG -- We need to make sure to map NuBus memory in
    255     the kernel, too.
    256    ALICE 06/29/92,20:40:00 LK -- I did that, thank you very much.  Been there.
    257  */
    258 
    259 
    260 /*
    261  * 68851 and 68030 MMU
    262  */
    263 #define	PMMU_LVLMASK	0x0007
    264 #define	PMMU_INV	0x0400
    265 #define	PMMU_WP		0x0800
    266 #define	PMMU_ALV	0x1000
    267 #define	PMMU_SO		0x2000
    268 #define	PMMU_LV		0x4000
    269 #define	PMMU_BE		0x8000
    270 #define	PMMU_FAULT	(PMMU_WP|PMMU_INV)
    271 
    272 /* 680X0 function codes */
    273 #define	FC_USERD	1	/* user data space */
    274 #define	FC_USERP	2	/* user program space */
    275 #define	FC_SUPERD	5	/* supervisor data space */
    276 #define	FC_SUPERP	6	/* supervisor program space */
    277 #define	FC_CPU		7	/* CPU space */
    278 
    279 /* fields in the 68020 cache control register */
    280 #define	IC_ENABLE	0x0001	/* enable instruction cache */
    281 #define	IC_FREEZE	0x0002	/* freeze instruction cache */
    282 #define	IC_CE		0x0004	/* clear instruction cache entry */
    283 #define	IC_CLR		0x0008	/* clear entire instruction cache */
    284 
    285 /* additional fields in the 68030 cache control register */
    286 #define	IC_BE		0x0010	/* instruction burst enable */
    287 #define	DC_ENABLE	0x0100	/* data cache enable */
    288 #define	DC_FREEZE	0x0200	/* data cache freeze */
    289 #define	DC_CE		0x0400	/* clear data cache entry */
    290 #define	DC_CLR		0x0800	/* clear entire data cache */
    291 #define	DC_BE		0x1000	/* data burst enable */
    292 #define	DC_WA		0x2000	/* write allocate */
    293 
    294 /* fields in the 68040 cache control register */
    295 #define IC40_ENABLE	0x00008000	/* enable instruction cache */
    296 #define DC40_ENABLE	0x80000000	/* enable data cache */
    297 
    298 #define	CACHE_ON	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    299 #define	CACHE_OFF	(DC_CLR|IC_CLR)
    300 #define	CACHE_CLR	(CACHE_ON)
    301 #define	IC_CLEAR	(DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    302 #define	DC_CLEAR	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
    303 
    304 /* 68040 cache control */
    305 #define CACHE40_ON	(IC40_ENABLE|DC40_ENABLE)
    306 #define CACHE40_OFF	0x00000000
    307 
    308 #endif	/* !_MACHINE_CPU_H_ */
    309