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esp.c revision 1.52
      1  1.52    rmind /*	$NetBSD: esp.c,v 1.52 2009/11/23 00:11:44 rmind Exp $	*/
      2   1.1   briggs 
      3   1.1   briggs /*
      4  1.10   briggs  * Copyright (c) 1997 Jason R. Thorpe.
      5  1.10   briggs  * All rights reserved.
      6   1.1   briggs  *
      7   1.1   briggs  * Redistribution and use in source and binary forms, with or without
      8   1.1   briggs  * modification, are permitted provided that the following conditions
      9   1.1   briggs  * are met:
     10   1.1   briggs  * 1. Redistributions of source code must retain the above copyright
     11   1.1   briggs  *    notice, this list of conditions and the following disclaimer.
     12   1.1   briggs  * 2. Redistributions in binary form must reproduce the above copyright
     13   1.1   briggs  *    notice, this list of conditions and the following disclaimer in the
     14   1.1   briggs  *    documentation and/or other materials provided with the distribution.
     15   1.1   briggs  * 3. All advertising materials mentioning features or use of this software
     16   1.1   briggs  *    must display the following acknowledgement:
     17  1.10   briggs  *	This product includes software developed for the NetBSD Project
     18  1.10   briggs  *	by Jason R. Thorpe.
     19   1.1   briggs  * 4. The name of the author may not be used to endorse or promote products
     20   1.1   briggs  *    derived from this software without specific prior written permission.
     21   1.1   briggs  *
     22   1.1   briggs  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     23   1.1   briggs  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24   1.1   briggs  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25   1.1   briggs  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     26   1.1   briggs  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     27   1.1   briggs  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     28   1.1   briggs  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     29   1.1   briggs  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     30   1.1   briggs  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     31   1.1   briggs  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32   1.1   briggs  */
     33   1.1   briggs 
     34   1.1   briggs /*
     35   1.1   briggs  * Copyright (c) 1994 Peter Galbavy
     36   1.1   briggs  * All rights reserved.
     37   1.1   briggs  *
     38   1.1   briggs  * Redistribution and use in source and binary forms, with or without
     39   1.1   briggs  * modification, are permitted provided that the following conditions
     40   1.1   briggs  * are met:
     41   1.1   briggs  * 1. Redistributions of source code must retain the above copyright
     42   1.1   briggs  *    notice, this list of conditions and the following disclaimer.
     43   1.1   briggs  * 2. Redistributions in binary form must reproduce the above copyright
     44   1.1   briggs  *    notice, this list of conditions and the following disclaimer in the
     45   1.1   briggs  *    documentation and/or other materials provided with the distribution.
     46   1.1   briggs  * 3. All advertising materials mentioning features or use of this software
     47   1.1   briggs  *    must display the following acknowledgement:
     48   1.1   briggs  *	This product includes software developed by Peter Galbavy
     49   1.1   briggs  * 4. The name of the author may not be used to endorse or promote products
     50   1.1   briggs  *    derived from this software without specific prior written permission.
     51   1.1   briggs  *
     52   1.1   briggs  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     53   1.1   briggs  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     54   1.1   briggs  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     55   1.1   briggs  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     56   1.1   briggs  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     57   1.1   briggs  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     58   1.1   briggs  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     59   1.1   briggs  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     60   1.1   briggs  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     61   1.1   briggs  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     62   1.1   briggs  * POSSIBILITY OF SUCH DAMAGE.
     63   1.1   briggs  */
     64   1.1   briggs 
     65   1.1   briggs /*
     66   1.1   briggs  * Based on aic6360 by Jarle Greipsland
     67   1.1   briggs  *
     68   1.1   briggs  * Acknowledgements: Many of the algorithms used in this driver are
     69   1.1   briggs  * inspired by the work of Julian Elischer (julian (at) tfs.com) and
     70   1.1   briggs  * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu).  Thanks a million!
     71  1.10   briggs  */
     72  1.10   briggs 
     73  1.10   briggs /*
     74  1.10   briggs  * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com>
     75  1.10   briggs  * (basically consisting of the match, a bit of the attach, and the
     76  1.10   briggs  *  "DMA" glue functions).
     77   1.1   briggs  */
     78  1.35    lukem 
     79  1.35    lukem #include <sys/cdefs.h>
     80  1.52    rmind __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.52 2009/11/23 00:11:44 rmind Exp $");
     81   1.1   briggs 
     82   1.1   briggs #include <sys/types.h>
     83   1.1   briggs #include <sys/param.h>
     84   1.1   briggs #include <sys/systm.h>
     85   1.1   briggs #include <sys/kernel.h>
     86   1.1   briggs #include <sys/errno.h>
     87   1.1   briggs #include <sys/ioctl.h>
     88   1.1   briggs #include <sys/device.h>
     89   1.1   briggs #include <sys/buf.h>
     90   1.1   briggs #include <sys/proc.h>
     91   1.1   briggs #include <sys/queue.h>
     92   1.1   briggs 
     93  1.11   bouyer #include <dev/scsipi/scsi_all.h>
     94  1.11   bouyer #include <dev/scsipi/scsipi_all.h>
     95  1.11   bouyer #include <dev/scsipi/scsiconf.h>
     96  1.11   bouyer #include <dev/scsipi/scsi_message.h>
     97   1.1   briggs 
     98   1.1   briggs #include <machine/cpu.h>
     99  1.12   briggs #include <machine/bus.h>
    100   1.1   briggs #include <machine/param.h>
    101   1.1   briggs 
    102   1.7   briggs #include <dev/ic/ncr53c9xreg.h>
    103   1.7   briggs #include <dev/ic/ncr53c9xvar.h>
    104   1.7   briggs 
    105   1.1   briggs #include <machine/viareg.h>
    106   1.1   briggs 
    107  1.15   scottr #include <mac68k/obio/espvar.h>
    108  1.15   scottr #include <mac68k/obio/obiovar.h>
    109   1.3   briggs 
    110  1.50  tsutsui int	espmatch(device_t, cfdata_t, void *);
    111  1.50  tsutsui void	espattach(device_t, device_t, void *);
    112   1.1   briggs 
    113   1.1   briggs /* Linkup to the rest of the kernel */
    114  1.50  tsutsui CFATTACH_DECL_NEW(esp, sizeof(struct esp_softc),
    115  1.34  thorpej     espmatch, espattach, NULL, NULL);
    116   1.1   briggs 
    117   1.7   briggs /*
    118   1.7   briggs  * Functions and the switch for the MI code.
    119   1.7   briggs  */
    120  1.50  tsutsui uint8_t	esp_read_reg(struct ncr53c9x_softc *, int);
    121  1.50  tsutsui void	esp_write_reg(struct ncr53c9x_softc *, int, uint8_t);
    122  1.36      chs int	esp_dma_isintr(struct ncr53c9x_softc *);
    123  1.36      chs void	esp_dma_reset(struct ncr53c9x_softc *);
    124  1.36      chs int	esp_dma_intr(struct ncr53c9x_softc *);
    125  1.50  tsutsui int	esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *, int,
    126  1.36      chs 	    size_t *);
    127  1.36      chs void	esp_dma_go(struct ncr53c9x_softc *);
    128  1.36      chs void	esp_dma_stop(struct ncr53c9x_softc *);
    129  1.36      chs int	esp_dma_isactive(struct ncr53c9x_softc *);
    130  1.36      chs void	esp_quick_write_reg(struct ncr53c9x_softc *, int, u_char);
    131  1.36      chs int	esp_quick_dma_intr(struct ncr53c9x_softc *);
    132  1.50  tsutsui int	esp_quick_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *, int,
    133  1.36      chs 	     size_t *);
    134  1.36      chs void	esp_quick_dma_go(struct ncr53c9x_softc *);
    135  1.36      chs 
    136  1.36      chs void	esp_intr(void *);
    137  1.36      chs void	esp_dualbus_intr(void *);
    138  1.36      chs static struct esp_softc		*esp0, *esp1;
    139  1.36      chs 
    140  1.43    perry static inline int esp_dafb_have_dreq(struct esp_softc *);
    141  1.43    perry static inline int esp_iosb_have_dreq(struct esp_softc *);
    142  1.36      chs int (*esp_have_dreq)(struct esp_softc *);
    143   1.7   briggs 
    144   1.7   briggs struct ncr53c9x_glue esp_glue = {
    145   1.7   briggs 	esp_read_reg,
    146   1.7   briggs 	esp_write_reg,
    147   1.7   briggs 	esp_dma_isintr,
    148   1.7   briggs 	esp_dma_reset,
    149   1.7   briggs 	esp_dma_intr,
    150   1.7   briggs 	esp_dma_setup,
    151   1.7   briggs 	esp_dma_go,
    152   1.7   briggs 	esp_dma_stop,
    153   1.7   briggs 	esp_dma_isactive,
    154   1.7   briggs 	NULL,			/* gl_clear_latched_intr */
    155   1.7   briggs };
    156   1.7   briggs 
    157   1.1   briggs int
    158  1.50  tsutsui espmatch(device_t parent, cfdata_t cf, void *aux)
    159   1.1   briggs {
    160  1.50  tsutsui 	struct obio_attach_args *oa = aux;
    161  1.12   briggs 
    162  1.38      chs 	if (oa->oa_addr == 0 && mac68k_machine.scsi96) {
    163  1.38      chs 		return 1;
    164  1.12   briggs 	}
    165  1.38      chs 	if (oa->oa_addr == 1 && mac68k_machine.scsi96_2) {
    166  1.38      chs 		return 1;
    167  1.12   briggs 	}
    168  1.38      chs 	return 0;
    169   1.1   briggs }
    170   1.1   briggs 
    171   1.1   briggs /*
    172   1.1   briggs  * Attach this instance, and then all the sub-devices
    173   1.1   briggs  */
    174   1.1   briggs void
    175  1.50  tsutsui espattach(device_t parent, device_t self, void *aux)
    176   1.1   briggs {
    177  1.50  tsutsui 	struct esp_softc	*esc = device_private(self);
    178  1.12   briggs 	struct ncr53c9x_softc	*sc = &esc->sc_ncr53c9x;
    179  1.50  tsutsui 	struct obio_attach_args *oa = aux;
    180  1.12   briggs 	int			quick = 0;
    181  1.12   briggs 	unsigned long		reg_offset;
    182  1.50  tsutsui 	extern vaddr_t		SCSIBase;
    183  1.50  tsutsui 
    184  1.50  tsutsui 	sc->sc_dev = self;
    185  1.12   briggs 
    186  1.12   briggs 	reg_offset = SCSIBase - IOBase;
    187  1.12   briggs 	esc->sc_tag = oa->oa_tag;
    188  1.37      chs 
    189  1.12   briggs 	/*
    190  1.12   briggs 	 * For Wombat, Primus and Optimus motherboards, DREQ is
    191  1.12   briggs 	 * visible on bit 0 of the IOSB's emulated VIA2 vIFR (and
    192  1.12   briggs 	 * the scsi registers are offset 0x1000 bytes from IOBase).
    193  1.12   briggs 	 *
    194  1.12   briggs 	 * For the Q700/900/950 it's at f9800024 for bus 0 and
    195  1.12   briggs 	 * f9800028 for bus 1 (900/950).  For these machines, that is also
    196  1.12   briggs 	 * a (12-bit) configuration register for DAFB's control of the
    197  1.12   briggs 	 * pseudo-DMA timing.  The default value is 0x1d1.
    198  1.12   briggs 	 */
    199  1.12   briggs 	esp_have_dreq = esp_dafb_have_dreq;
    200  1.39      chs 	if (oa->oa_addr == 0) {
    201  1.12   briggs 		if (reg_offset == 0x10000) {
    202  1.12   briggs 			quick = 1;
    203  1.12   briggs 			esp_have_dreq = esp_iosb_have_dreq;
    204  1.12   briggs 		} else if (reg_offset == 0x18000) {
    205  1.12   briggs 			quick = 0;
    206  1.12   briggs 		} else {
    207  1.12   briggs 			if (bus_space_map(esc->sc_tag, 0xf9800024,
    208  1.12   briggs 					  4, 0, &esc->sc_bsh)) {
    209  1.50  tsutsui 				aprint_error(": failed to map 4"
    210  1.50  tsutsui 				    " at 0xf9800024.\n");
    211  1.12   briggs 			} else {
    212  1.12   briggs 				quick = 1;
    213  1.12   briggs 				bus_space_write_4(esc->sc_tag,
    214  1.12   briggs 						  esc->sc_bsh, 0, 0x1d1);
    215  1.12   briggs 			}
    216  1.12   briggs 		}
    217  1.12   briggs 	} else {
    218  1.12   briggs 		if (bus_space_map(esc->sc_tag, 0xf9800028,
    219  1.12   briggs 				  4, 0, &esc->sc_bsh)) {
    220  1.50  tsutsui 			aprint_error(": failed to map 4 at 0xf9800028.\n");
    221  1.12   briggs 		} else {
    222  1.12   briggs 			quick = 1;
    223  1.12   briggs 			bus_space_write_4(esc->sc_tag, esc->sc_bsh, 0, 0x1d1);
    224  1.12   briggs 		}
    225  1.12   briggs 	}
    226  1.12   briggs 	if (quick) {
    227  1.12   briggs 		esp_glue.gl_write_reg = esp_quick_write_reg;
    228  1.12   briggs 		esp_glue.gl_dma_intr = esp_quick_dma_intr;
    229  1.12   briggs 		esp_glue.gl_dma_setup = esp_quick_dma_setup;
    230  1.12   briggs 		esp_glue.gl_dma_go = esp_quick_dma_go;
    231  1.12   briggs 	}
    232   1.1   briggs 
    233   1.1   briggs 	/*
    234   1.7   briggs 	 * Set up the glue for MI code early; we use some of it here.
    235   1.1   briggs 	 */
    236   1.7   briggs 	sc->sc_glue = &esp_glue;
    237   1.1   briggs 
    238   1.1   briggs 	/*
    239   1.7   briggs 	 * Save the regs
    240   1.1   briggs 	 */
    241  1.39      chs 	if (oa->oa_addr == 0) {
    242  1.16   briggs 		esp0 = esc;
    243   1.2   briggs 
    244  1.50  tsutsui 		esc->sc_reg = (volatile uint8_t *)SCSIBase;
    245  1.23   briggs 		via2_register_irq(VIA2_SCSIIRQ, esp_intr, esc);
    246   1.7   briggs 		esc->irq_mask = V2IF_SCSIIRQ;
    247   1.2   briggs 		if (reg_offset == 0x10000) {
    248  1.26   briggs 			/* From the Q650 developer's note */
    249   1.2   briggs 			sc->sc_freq = 16500000;
    250   1.2   briggs 		} else {
    251   1.2   briggs 			sc->sc_freq = 25000000;
    252   1.2   briggs 		}
    253  1.12   briggs 
    254  1.12   briggs 		if (esp_glue.gl_dma_go == esp_quick_dma_go) {
    255  1.50  tsutsui 			aprint_normal(" (quick)");
    256  1.12   briggs 		}
    257   1.1   briggs 	} else {
    258  1.16   briggs 		esp1 = esc;
    259  1.16   briggs 
    260  1.50  tsutsui 		esc->sc_reg = (volatile uint8_t *)SCSIBase + 0x402;
    261  1.23   briggs 		via2_register_irq(VIA2_SCSIIRQ, esp_dualbus_intr, NULL);
    262  1.16   briggs 		esc->irq_mask = 0;
    263   1.2   briggs 		sc->sc_freq = 25000000;
    264  1.12   briggs 
    265  1.12   briggs 		if (esp_glue.gl_dma_go == esp_quick_dma_go) {
    266  1.12   briggs 			printf(" (quick)");
    267  1.12   briggs 		}
    268   1.1   briggs 	}
    269   1.7   briggs 
    270  1.50  tsutsui 	aprint_normal(": address %p", esc->sc_reg);
    271   1.1   briggs 
    272   1.1   briggs 	sc->sc_id = 7;
    273   1.1   briggs 
    274  1.44    lukem 	/* gimme MHz */
    275   1.1   briggs 	sc->sc_freq /= 1000000;
    276   1.1   briggs 
    277   1.1   briggs 	/*
    278   1.1   briggs 	 * It is necessary to try to load the 2nd config register here,
    279   1.1   briggs 	 * to find out what rev the esp chip is, else the esp_reset
    280   1.1   briggs 	 * will not set up the defaults correctly.
    281   1.1   briggs 	 */
    282  1.13   briggs 	sc->sc_cfg1 = sc->sc_id; /* | NCRCFG1_PARENB; */
    283   1.7   briggs 	sc->sc_cfg2 = NCRCFG2_SCSI2;
    284   1.3   briggs 	sc->sc_cfg3 = 0;
    285   1.7   briggs 	sc->sc_rev = NCR_VARIANT_NCR53C96;
    286   1.1   briggs 
    287   1.1   briggs 	/*
    288   1.1   briggs 	 * This is the value used to start sync negotiations
    289   1.7   briggs 	 * Note that the NCR register "SYNCTP" is programmed
    290   1.1   briggs 	 * in "clocks per byte", and has a minimum value of 4.
    291   1.1   briggs 	 * The SCSI period used in negotiation is one-fourth
    292   1.1   briggs 	 * of the time (in nanoseconds) needed to transfer one byte.
    293   1.1   briggs 	 * Since the chip's clock is given in MHz, we have the following
    294   1.1   briggs 	 * formula: 4 * period = (1000 / freq) * 4
    295   1.1   briggs 	 */
    296   1.1   briggs 	sc->sc_minsync = 1000 / sc->sc_freq;
    297   1.1   briggs 
    298  1.26   briggs 	/* We need this to fit into the TCR... */
    299  1.26   briggs 	sc->sc_maxxfer = 64 * 1024;
    300  1.26   briggs 
    301  1.48  tsutsui         switch (current_mac_model->machineid) {
    302  1.48  tsutsui         case MACH_MACQ630:
    303  1.48  tsutsui 		/* XXX on LC630 64k xfer causes timeout error */
    304  1.48  tsutsui 		sc->sc_maxxfer = 63 * 1024;
    305  1.48  tsutsui 		break;
    306  1.48  tsutsui 	}
    307  1.48  tsutsui 
    308  1.26   briggs 	if (!quick) {
    309  1.26   briggs 		sc->sc_minsync = 0;	/* No synchronous xfers w/o DMA */
    310  1.26   briggs 		sc->sc_maxxfer = 8 * 1024;
    311  1.26   briggs 	}
    312   1.1   briggs 
    313   1.1   briggs 	/*
    314   1.7   briggs 	 * Configure interrupts.
    315   1.1   briggs 	 */
    316  1.16   briggs 	if (esc->irq_mask) {
    317  1.16   briggs 		via2_reg(vPCR) = 0x22;
    318  1.16   briggs 		via2_reg(vIFR) = esc->irq_mask;
    319  1.16   briggs 		via2_reg(vIER) = 0x80 | esc->irq_mask;
    320  1.16   briggs 	}
    321  1.24  thorpej 
    322  1.24  thorpej 	/*
    323  1.24  thorpej 	 * Now try to attach all the sub-devices
    324  1.24  thorpej 	 */
    325  1.29   bouyer 	sc->sc_adapter.adapt_minphys = minphys;
    326  1.29   bouyer 	sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
    327  1.29   bouyer 	ncr53c9x_attach(sc);
    328   1.1   briggs }
    329   1.1   briggs 
    330   1.1   briggs /*
    331   1.7   briggs  * Glue functions.
    332   1.1   briggs  */
    333   1.1   briggs 
    334  1.50  tsutsui uint8_t
    335  1.37      chs esp_read_reg(struct ncr53c9x_softc *sc, int reg)
    336   1.1   briggs {
    337   1.7   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    338   1.1   briggs 
    339  1.23   briggs 	return esc->sc_reg[reg * 16];
    340   1.1   briggs }
    341   1.1   briggs 
    342   1.1   briggs void
    343  1.50  tsutsui esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
    344   1.1   briggs {
    345   1.7   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    346  1.50  tsutsui 	uint8_t	v = val;
    347   1.1   briggs 
    348   1.7   briggs 	if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) {
    349   1.7   briggs 		v = NCRCMD_TRANS;
    350   1.1   briggs 	}
    351   1.7   briggs 	esc->sc_reg[reg * 16] = v;
    352   1.1   briggs }
    353   1.1   briggs 
    354  1.12   briggs void
    355  1.37      chs esp_dma_stop(struct ncr53c9x_softc *sc)
    356  1.12   briggs {
    357  1.12   briggs }
    358  1.12   briggs 
    359  1.12   briggs int
    360  1.37      chs esp_dma_isactive(struct ncr53c9x_softc *sc)
    361  1.12   briggs {
    362  1.12   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    363  1.12   briggs 
    364  1.12   briggs 	return esc->sc_active;
    365  1.12   briggs }
    366  1.12   briggs 
    367   1.7   briggs int
    368  1.37      chs esp_dma_isintr(struct ncr53c9x_softc *sc)
    369   1.1   briggs {
    370   1.7   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    371   1.1   briggs 
    372   1.7   briggs 	return esc->sc_reg[NCR_STAT * 16] & 0x80;
    373   1.1   briggs }
    374   1.1   briggs 
    375   1.1   briggs void
    376  1.37      chs esp_dma_reset(struct ncr53c9x_softc *sc)
    377   1.1   briggs {
    378   1.7   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    379   1.1   briggs 
    380   1.7   briggs 	esc->sc_active = 0;
    381   1.7   briggs 	esc->sc_tc = 0;
    382   1.1   briggs }
    383   1.1   briggs 
    384   1.7   briggs int
    385  1.37      chs esp_dma_intr(struct ncr53c9x_softc *sc)
    386   1.1   briggs {
    387  1.22   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    388   1.7   briggs 	volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg;
    389  1.50  tsutsui 	uint8_t	*p;
    390  1.22   briggs 	u_int	espphase, espstat, espintr;
    391  1.22   briggs 	int	cnt, s;
    392   1.1   briggs 
    393   1.7   briggs 	if (esc->sc_active == 0) {
    394   1.7   briggs 		printf("dma_intr--inactive DMA\n");
    395   1.7   briggs 		return -1;
    396   1.1   briggs 	}
    397   1.1   briggs 
    398   1.7   briggs 	if ((sc->sc_espintr & NCRINTR_BS) == 0) {
    399   1.7   briggs 		esc->sc_active = 0;
    400   1.7   briggs 		return 0;
    401   1.1   briggs 	}
    402   1.1   briggs 
    403  1.30   briggs 	cnt = *esc->sc_dmalen;
    404  1.30   briggs 	if (*esc->sc_dmalen == 0) {
    405   1.7   briggs 		printf("data interrupt, but no count left.");
    406   1.1   briggs 	}
    407   1.1   briggs 
    408   1.7   briggs 	p = *esc->sc_dmaaddr;
    409   1.7   briggs 	espphase = sc->sc_phase;
    410  1.50  tsutsui 	espstat = (u_int)sc->sc_espstat;
    411  1.50  tsutsui 	espintr = (u_int)sc->sc_espintr;
    412   1.7   briggs 	cmdreg = esc->sc_reg + NCR_CMD * 16;
    413   1.7   briggs 	fiforeg = esc->sc_reg + NCR_FIFO * 16;
    414   1.7   briggs 	statreg = esc->sc_reg + NCR_STAT * 16;
    415   1.7   briggs 	intrreg = esc->sc_reg + NCR_INTR * 16;
    416   1.7   briggs 	do {
    417   1.7   briggs 		if (esc->sc_datain) {
    418   1.7   briggs 			*p++ = *fiforeg;
    419   1.7   briggs 			cnt--;
    420   1.7   briggs 			if (espphase == DATA_IN_PHASE) {
    421   1.7   briggs 				*cmdreg = NCRCMD_TRANS;
    422   1.7   briggs 			} else {
    423   1.7   briggs 				esc->sc_active = 0;
    424   1.7   briggs 			}
    425   1.7   briggs 	 	} else {
    426   1.7   briggs 			if (   (espphase == DATA_OUT_PHASE)
    427   1.7   briggs 			    || (espphase == MESSAGE_OUT_PHASE)) {
    428   1.7   briggs 				*fiforeg = *p++;
    429   1.7   briggs 				cnt--;
    430   1.7   briggs 				*cmdreg = NCRCMD_TRANS;
    431   1.7   briggs 			} else {
    432   1.7   briggs 				esc->sc_active = 0;
    433   1.7   briggs 			}
    434   1.1   briggs 		}
    435   1.1   briggs 
    436   1.7   briggs 		if (esc->sc_active) {
    437   1.7   briggs 			while (!(*statreg & 0x80));
    438  1.22   briggs 			s = splhigh();
    439   1.7   briggs 			espstat = *statreg;
    440   1.7   briggs 			espintr = *intrreg;
    441   1.7   briggs 			espphase = (espintr & NCRINTR_DIS)
    442   1.7   briggs 				    ? /* Disconnected */ BUSFREE_PHASE
    443   1.7   briggs 				    : espstat & PHASE_MASK;
    444  1.22   briggs 			splx(s);
    445   1.1   briggs 		}
    446   1.7   briggs 	} while (esc->sc_active && (espintr & NCRINTR_BS));
    447   1.7   briggs 	sc->sc_phase = espphase;
    448  1.50  tsutsui 	sc->sc_espstat = (u_char)espstat;
    449  1.50  tsutsui 	sc->sc_espintr = (u_char)espintr;
    450   1.7   briggs 	*esc->sc_dmaaddr = p;
    451  1.30   briggs 	*esc->sc_dmalen = cnt;
    452   1.1   briggs 
    453  1.30   briggs 	if (*esc->sc_dmalen == 0) {
    454   1.7   briggs 		esc->sc_tc = NCRSTAT_TC;
    455   1.1   briggs 	}
    456   1.7   briggs 	sc->sc_espstat |= esc->sc_tc;
    457   1.7   briggs 	return 0;
    458   1.1   briggs }
    459   1.1   briggs 
    460   1.1   briggs int
    461  1.50  tsutsui esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
    462  1.50  tsutsui     int datain, size_t *dmasize)
    463   1.1   briggs {
    464   1.7   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    465   1.1   briggs 
    466  1.50  tsutsui 	esc->sc_dmaaddr = addr;
    467  1.12   briggs 	esc->sc_dmalen = len;
    468   1.7   briggs 	esc->sc_datain = datain;
    469   1.7   briggs 	esc->sc_dmasize = *dmasize;
    470   1.7   briggs 	esc->sc_tc = 0;
    471   1.1   briggs 
    472   1.7   briggs 	return 0;
    473   1.1   briggs }
    474   1.1   briggs 
    475   1.1   briggs void
    476  1.37      chs esp_dma_go(struct ncr53c9x_softc *sc)
    477   1.1   briggs {
    478   1.7   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    479   1.1   briggs 
    480   1.7   briggs 	if (esc->sc_datain == 0) {
    481   1.7   briggs 		esc->sc_reg[NCR_FIFO * 16] = **esc->sc_dmaaddr;
    482  1.12   briggs 		(*esc->sc_dmalen)--;
    483   1.7   briggs 		(*esc->sc_dmaaddr)++;
    484   1.1   briggs 	}
    485   1.7   briggs 	esc->sc_active = 1;
    486   1.1   briggs }
    487   1.1   briggs 
    488   1.1   briggs void
    489  1.37      chs esp_quick_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
    490   1.1   briggs {
    491  1.12   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    492  1.12   briggs 
    493  1.23   briggs 	esc->sc_reg[reg * 16] = val;
    494   1.1   briggs }
    495   1.1   briggs 
    496  1.26   briggs #if DEBUG
    497  1.26   briggs int mac68k_esp_debug=0;
    498  1.26   briggs #endif
    499  1.26   briggs 
    500   1.1   briggs int
    501  1.37      chs esp_quick_dma_intr(struct ncr53c9x_softc *sc)
    502  1.12   briggs {
    503  1.12   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    504  1.12   briggs 	int trans=0, resid=0;
    505  1.12   briggs 
    506  1.12   briggs 	if (esc->sc_active == 0)
    507  1.32   provos 		panic("dma_intr--inactive DMA");
    508  1.12   briggs 
    509  1.12   briggs 	esc->sc_active = 0;
    510  1.12   briggs 
    511  1.12   briggs 	if (esc->sc_dmasize == 0) {
    512  1.12   briggs 		int	res;
    513  1.12   briggs 
    514  1.26   briggs 		res = NCR_READ_REG(sc, NCR_TCL);
    515  1.26   briggs 		res += NCR_READ_REG(sc, NCR_TCM) << 8;
    516  1.28   briggs 		/* This can happen in the case of a TRPAD operation */
    517  1.28   briggs 		/* Pretend that it was complete */
    518  1.28   briggs 		sc->sc_espstat |= NCRSTAT_TC;
    519  1.28   briggs #if DEBUG
    520  1.28   briggs 		if (mac68k_esp_debug) {
    521  1.28   briggs 			printf("dmaintr: DMA xfer of zero xferred %d\n",
    522  1.28   briggs 			    65536 - res);
    523  1.28   briggs 		}
    524  1.28   briggs #endif
    525  1.12   briggs 		return 0;
    526  1.12   briggs 	}
    527  1.12   briggs 
    528  1.12   briggs 	if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
    529  1.28   briggs 		if (esc->sc_datain == 0) {
    530  1.28   briggs 			resid = NCR_READ_REG(sc, NCR_FFLAG) & 0x1f;
    531  1.28   briggs #if DEBUG
    532  1.28   briggs 			if (mac68k_esp_debug) {
    533  1.28   briggs 				printf("Write FIFO residual %d bytes\n", resid);
    534  1.28   briggs 			}
    535  1.28   briggs #endif
    536  1.28   briggs 		}
    537  1.12   briggs 		resid += NCR_READ_REG(sc, NCR_TCL);
    538  1.12   briggs 		resid += NCR_READ_REG(sc, NCR_TCM) << 8;
    539  1.12   briggs 		if (resid == 0)
    540  1.12   briggs 			resid = 65536;
    541  1.12   briggs 	}
    542  1.12   briggs 
    543  1.12   briggs 	trans = esc->sc_dmasize - resid;
    544  1.12   briggs 	if (trans < 0) {
    545  1.12   briggs 		printf("dmaintr: trans < 0????");
    546  1.26   briggs 		trans = *esc->sc_dmalen;
    547  1.12   briggs 	}
    548  1.12   briggs 
    549  1.12   briggs 	NCR_DMA(("dmaintr: trans %d, resid %d.\n", trans, resid));
    550  1.26   briggs #if DEBUG
    551  1.26   briggs 	if (mac68k_esp_debug) {
    552  1.26   briggs 		printf("eqd_intr: trans %d, resid %d.\n", trans, resid);
    553  1.26   briggs 	}
    554  1.26   briggs #endif
    555  1.12   briggs 	*esc->sc_dmaaddr += trans;
    556  1.12   briggs 	*esc->sc_dmalen -= trans;
    557  1.12   briggs 
    558  1.12   briggs 	return 0;
    559  1.12   briggs }
    560  1.12   briggs 
    561  1.12   briggs int
    562  1.50  tsutsui esp_quick_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
    563  1.37      chs     int datain, size_t *dmasize)
    564  1.12   briggs {
    565  1.12   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    566  1.12   briggs 
    567  1.50  tsutsui 	esc->sc_dmaaddr = addr;
    568  1.12   briggs 	esc->sc_dmalen = len;
    569  1.12   briggs 
    570  1.26   briggs 	if (*len & 1) {
    571  1.13   briggs 		esc->sc_pad = 1;
    572  1.13   briggs 	} else {
    573  1.13   briggs 		esc->sc_pad = 0;
    574  1.13   briggs 	}
    575  1.12   briggs 
    576  1.12   briggs 	esc->sc_datain = datain;
    577  1.12   briggs 	esc->sc_dmasize = *dmasize;
    578  1.12   briggs 
    579  1.26   briggs #if DIAGNOSTIC
    580  1.26   briggs 	if (esc->sc_dmasize == 0) {
    581  1.28   briggs 		/* This can happen in the case of a TRPAD operation */
    582  1.26   briggs 	}
    583  1.26   briggs #endif
    584  1.26   briggs #if DEBUG
    585  1.26   briggs 	if (mac68k_esp_debug) {
    586  1.26   briggs 	printf("eqd_setup: addr %lx, len %lx, in? %d, dmasize %lx\n",
    587  1.26   briggs 	    (long) *addr, (long) *len, datain, (long) esc->sc_dmasize);
    588  1.26   briggs 	}
    589  1.26   briggs #endif
    590  1.26   briggs 
    591  1.12   briggs 	return 0;
    592  1.12   briggs }
    593  1.12   briggs 
    594  1.43    perry static inline int
    595  1.37      chs esp_dafb_have_dreq(struct esp_softc *esc)
    596  1.12   briggs {
    597  1.50  tsutsui 
    598  1.50  tsutsui 	return *(volatile uint32_t *)(esc->sc_bsh.base) & 0x200;
    599  1.12   briggs }
    600  1.12   briggs 
    601  1.43    perry static inline int
    602  1.37      chs esp_iosb_have_dreq(struct esp_softc *esc)
    603  1.12   briggs {
    604  1.50  tsutsui 
    605  1.50  tsutsui 	return via2_reg(vIFR) & V2IF_SCSIDRQ;
    606  1.12   briggs }
    607  1.12   briggs 
    608  1.50  tsutsui static volatile int espspl = -1;
    609  1.12   briggs 
    610  1.26   briggs /*
    611  1.26   briggs  * Apple "DMA" is weird.
    612  1.26   briggs  *
    613  1.26   briggs  * Basically, the CPU acts like the DMA controller.  The DREQ/ off the
    614  1.26   briggs  * chip goes to a register that we've mapped at attach time (on the
    615  1.26   briggs  * IOSB or DAFB, depending on the machine).  Apple also provides some
    616  1.26   briggs  * space for which the memory controller handshakes data to/from the
    617  1.26   briggs  * NCR chip with the DACK/ line.  This space appears to be mapped over
    618  1.26   briggs  * and over, every 4 bytes, but only the lower 16 bits are valid (but
    619  1.26   briggs  * reading the upper 16 bits will handshake DACK/ just fine, so if you
    620  1.26   briggs  * read *u_int16_t++ = *u_int16_t++ in a loop, you'll get
    621  1.26   briggs  * <databyte><databyte>0xff0xff<databyte><databyte>0xff0xff...
    622  1.26   briggs  *
    623  1.26   briggs  * When you're attempting to read or write memory to this DACK/ed space,
    624  1.26   briggs  * and the NCR is not ready for some timeout period, the system will
    625  1.26   briggs  * generate a bus error.  This might be for one of several reasons:
    626  1.26   briggs  *
    627  1.26   briggs  *	1) (on write) The FIFO is full and is not draining.
    628  1.26   briggs  *	2) (on read) The FIFO is empty and is not filling.
    629  1.26   briggs  *	3) An interrupt condition has occurred.
    630  1.26   briggs  *	4) Anything else?
    631  1.26   briggs  *
    632  1.26   briggs  * So if a bus error occurs, we first turn off the nofault bus error handler,
    633  1.26   briggs  * then we check for an interrupt (which would render the first two
    634  1.26   briggs  * possibilities moot).  If there's no interrupt, check for a DREQ/.  If we
    635  1.26   briggs  * have that, then attempt to resume stuffing (or unstuffing) the FIFO.  If
    636  1.26   briggs  * neither condition holds, pause briefly and check again.
    637  1.26   briggs  *
    638  1.26   briggs  * NOTE!!!  In order to make allowances for the hardware structure of
    639  1.26   briggs  *          the mac, spl values in here are hardcoded!!!!!!!!!
    640  1.26   briggs  *          This is done to allow serial interrupts to get in during
    641  1.26   briggs  *          scsi transfers.  This is ugly.
    642  1.26   briggs  */
    643  1.12   briggs void
    644  1.37      chs esp_quick_dma_go(struct ncr53c9x_softc *sc)
    645   1.1   briggs {
    646   1.7   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    647  1.26   briggs 	extern long mac68k_a2_fromfault;
    648  1.12   briggs 	extern int *nofault;
    649  1.12   briggs 	label_t faultbuf;
    650  1.50  tsutsui 	uint16_t volatile *pdma;
    651  1.50  tsutsui 	uint16_t *addr;
    652  1.26   briggs 	int		len, res;
    653  1.50  tsutsui 	uint16_t	cnt32, cnt2;
    654  1.50  tsutsui 	volatile uint8_t *statreg;
    655  1.12   briggs 
    656  1.12   briggs 	esc->sc_active = 1;
    657  1.12   briggs 
    658  1.26   briggs 	espspl = splhigh();
    659  1.26   briggs 
    660  1.50  tsutsui 	addr = (uint16_t *)*esc->sc_dmaaddr;
    661  1.26   briggs 	len  = esc->sc_dmasize;
    662  1.12   briggs 
    663  1.12   briggs restart_dmago:
    664  1.26   briggs #if DEBUG
    665  1.26   briggs 	if (mac68k_esp_debug) {
    666  1.26   briggs 		printf("eqdg: a %lx, l %lx, in? %d ... ",
    667  1.26   briggs 		    (long) addr, (long) len, esc->sc_datain);
    668  1.26   briggs 	}
    669  1.26   briggs #endif
    670  1.50  tsutsui 	nofault = (int *)&faultbuf;
    671  1.50  tsutsui 	if (setjmp((label_t *)nofault)) {
    672  1.50  tsutsui 		int	i = 0;
    673  1.12   briggs 
    674  1.50  tsutsui 		nofault = NULL;
    675  1.26   briggs #if DEBUG
    676  1.26   briggs 		if (mac68k_esp_debug) {
    677  1.26   briggs 			printf("be\n");
    678  1.26   briggs 		}
    679  1.26   briggs #endif
    680  1.26   briggs 		/*
    681  1.26   briggs 		 * Bus error...
    682  1.26   briggs 		 * So, we first check for an interrupt.  If we have
    683  1.26   briggs 		 * one, go handle it.  Next we check for DREQ/.  If
    684  1.26   briggs 		 * we have it, then we restart the transfer.  If
    685  1.26   briggs 		 * neither, then loop until we get one or the other.
    686  1.26   briggs 		 */
    687  1.12   briggs 		statreg = esc->sc_reg + NCR_STAT * 16;
    688  1.12   briggs 		for (;;) {
    689  1.26   briggs 			spl2();		/* Give serial a chance... */
    690  1.26   briggs 			splhigh();	/* That's enough... */
    691  1.26   briggs 
    692  1.12   briggs 			if (*statreg & 0x80) {
    693  1.12   briggs 				goto gotintr;
    694  1.12   briggs 			}
    695  1.12   briggs 
    696  1.12   briggs 			if (esp_have_dreq(esc)) {
    697  1.26   briggs 				/*
    698  1.28   briggs 				 * Get the remaining length from the address
    699  1.26   briggs 				 * differential.
    700  1.26   briggs 				 */
    701  1.50  tsutsui 				addr = (uint16_t *)mac68k_a2_fromfault;
    702  1.26   briggs 				len = esc->sc_dmasize -
    703  1.50  tsutsui 				    ((long)addr - (long)*esc->sc_dmaaddr);
    704  1.26   briggs 
    705  1.26   briggs 				if (esc->sc_datain == 0) {
    706  1.26   briggs 					/*
    707  1.26   briggs 					 * Let the FIFO drain before we read
    708  1.26   briggs 					 * the transfer count.
    709  1.26   briggs 					 * Do we need to do this?
    710  1.26   briggs 					 * Can we do this?
    711  1.26   briggs 					 */
    712  1.26   briggs 					while (NCR_READ_REG(sc, NCR_FFLAG)
    713  1.26   briggs 					    & 0x1f);
    714  1.26   briggs 					/*
    715  1.26   briggs 					 * Get the length from the transfer
    716  1.26   briggs 					 * counters.
    717  1.26   briggs 					 */
    718  1.26   briggs 					res = NCR_READ_REG(sc, NCR_TCL);
    719  1.26   briggs 					res += NCR_READ_REG(sc, NCR_TCM) << 8;
    720  1.26   briggs 					/*
    721  1.26   briggs 					 * If they don't agree,
    722  1.26   briggs 					 * adjust accordingly.
    723  1.26   briggs 					 */
    724  1.26   briggs 					while (res > len) {
    725  1.26   briggs 						len+=2; addr--;
    726  1.26   briggs 					}
    727  1.26   briggs 					if (res != len) {
    728  1.50  tsutsui 						panic("%s: res %d != len %d",
    729  1.50  tsutsui 						    __func__, res, len);
    730  1.26   briggs 					}
    731  1.26   briggs 				}
    732  1.12   briggs 				break;
    733  1.12   briggs 			}
    734  1.12   briggs 
    735  1.12   briggs 			DELAY(1);
    736  1.26   briggs 			if (i++ > 1000000)
    737  1.50  tsutsui 				panic("%s: Bus error, but no condition!  Argh!",
    738  1.50  tsutsui 				    __func__);
    739  1.12   briggs 		}
    740  1.12   briggs 		goto restart_dmago;
    741  1.12   briggs 	}
    742  1.12   briggs 
    743  1.26   briggs 	len &= ~1;
    744  1.26   briggs 
    745  1.12   briggs 	statreg = esc->sc_reg + NCR_STAT * 16;
    746  1.50  tsutsui 	pdma = (volatile uint16_t *)(esc->sc_reg + 0x100);
    747   1.1   briggs 
    748  1.26   briggs 	/*
    749  1.26   briggs 	 * These loops are unrolled into assembly for two reasons:
    750  1.26   briggs 	 * 1) We can make sure that they are as efficient as possible, and
    751  1.26   briggs 	 * 2) (more importantly) we need the address that we are reading
    752  1.26   briggs 	 *    from or writing to to be in a2.
    753  1.26   briggs 	 */
    754  1.26   briggs 	cnt32 = len / 32;
    755  1.26   briggs 	cnt2 = (len % 32) / 2;
    756  1.12   briggs 	if (esc->sc_datain == 0) {
    757  1.26   briggs 		/* while (cnt32--) { 16 instances of *pdma = *addr++; } */
    758  1.26   briggs 		/* while (cnt2--) { *pdma = *addr++; } */
    759  1.42    perry 		__asm volatile (
    760  1.31  thorpej 			"	movl %1, %%a2	\n"
    761  1.31  thorpej 			"	movl %2, %%a3	\n"
    762  1.31  thorpej 			"	movw %3, %%d2	\n"
    763  1.31  thorpej 			"	cmpw #0, %%d2	\n"
    764  1.31  thorpej 			"	beq  2f		\n"
    765  1.31  thorpej 			"	subql #1, %%d2	\n"
    766  1.31  thorpej 			"1:	movw %%a2@+,%%a3@; movw %%a2@+,%%a3@	\n"
    767  1.31  thorpej 			"	movw %%a2@+,%%a3@; movw %%a2@+,%%a3@	\n"
    768  1.31  thorpej 			"	movw %%a2@+,%%a3@; movw %%a2@+,%%a3@	\n"
    769  1.31  thorpej 			"	movw %%a2@+,%%a3@; movw %%a2@+,%%a3@	\n"
    770  1.31  thorpej 			"	movw %%a2@+,%%a3@; movw %%a2@+,%%a3@	\n"
    771  1.31  thorpej 			"	movw %%a2@+,%%a3@; movw %%a2@+,%%a3@	\n"
    772  1.31  thorpej 			"	movw %%a2@+,%%a3@; movw %%a2@+,%%a3@	\n"
    773  1.31  thorpej 			"	movw %%a2@+,%%a3@; movw %%a2@+,%%a3@	\n"
    774  1.31  thorpej 			"	movw #8704,%%sr	\n"
    775  1.31  thorpej 			"	movw #9728,%%sr	\n"
    776  1.31  thorpej 			"	dbra %%d2, 1b	\n"
    777  1.31  thorpej 			"2:	movw %4, %%d2	\n"
    778  1.31  thorpej 			"	cmpw #0, %%d2	\n"
    779  1.31  thorpej 			"	beq  4f		\n"
    780  1.31  thorpej 			"	subql #1, %%d2	\n"
    781  1.31  thorpej 			"3:	movw %%a2@+,%%a3@ \n"
    782  1.31  thorpej 			"	dbra %%d2, 3b	\n"
    783  1.31  thorpej 			"4:	movl %%a2, %0"
    784  1.26   briggs 			: "=g" (addr)
    785  1.26   briggs 			: "0" (addr), "g" (pdma), "g" (cnt32), "g" (cnt2)
    786  1.26   briggs 			: "a2", "a3", "d2");
    787  1.13   briggs 		if (esc->sc_pad) {
    788  1.50  tsutsui 			volatile uint8_t *c;
    789  1.50  tsutsui 			c = (volatile uint8_t *) addr;
    790  1.26   briggs 			/* Wait for DREQ */
    791  1.26   briggs 			while (!esp_have_dreq(esc)) {
    792  1.26   briggs 				if (*statreg & 0x80) {
    793  1.50  tsutsui 					nofault = NULL;
    794  1.26   briggs 					goto gotintr;
    795  1.26   briggs 				}
    796  1.26   briggs 			}
    797  1.50  tsutsui 			*(volatile int8_t *)pdma = *c;
    798  1.13   briggs 		}
    799  1.12   briggs 	} else {
    800  1.26   briggs 		/* while (cnt32--) { 16 instances of *addr++ = *pdma; } */
    801  1.26   briggs 		/* while (cnt2--) { *addr++ = *pdma; } */
    802  1.42    perry 		__asm volatile (
    803  1.31  thorpej 			"	movl %1, %%a2	\n"
    804  1.31  thorpej 			"	movl %2, %%a3	\n"
    805  1.31  thorpej 			"	movw %3, %%d2	\n"
    806  1.31  thorpej 			"	cmpw #0, %%d2	\n"
    807  1.31  thorpej 			"	beq  6f		\n"
    808  1.31  thorpej 			"	subql #1, %%d2	\n"
    809  1.31  thorpej 			"5:	movw %%a3@,%%a2@+; movw %%a3@,%%a2@+	\n"
    810  1.31  thorpej 			"	movw %%a3@,%%a2@+; movw %%a3@,%%a2@+	\n"
    811  1.31  thorpej 			"	movw %%a3@,%%a2@+; movw %%a3@,%%a2@+	\n"
    812  1.31  thorpej 			"	movw %%a3@,%%a2@+; movw %%a3@,%%a2@+	\n"
    813  1.31  thorpej 			"	movw %%a3@,%%a2@+; movw %%a3@,%%a2@+	\n"
    814  1.31  thorpej 			"	movw %%a3@,%%a2@+; movw %%a3@,%%a2@+	\n"
    815  1.31  thorpej 			"	movw %%a3@,%%a2@+; movw %%a3@,%%a2@+	\n"
    816  1.31  thorpej 			"	movw %%a3@,%%a2@+; movw %%a3@,%%a2@+	\n"
    817  1.31  thorpej 			"	movw #8704,%%sr	\n"
    818  1.31  thorpej 			"	movw #9728,%%sr	\n"
    819  1.31  thorpej 			"	dbra %%d2, 5b	\n"
    820  1.31  thorpej 			"6:	movw %4, %%d2	\n"
    821  1.31  thorpej 			"	cmpw #0, %%d2	\n"
    822  1.31  thorpej 			"	beq  8f		\n"
    823  1.31  thorpej 			"	subql #1, %%d2	\n"
    824  1.31  thorpej 			"7:	movw %%a3@,%%a2@+ \n"
    825  1.31  thorpej 			"	dbra %%d2, 7b	\n"
    826  1.31  thorpej 			"8:	movl %%a2, %0"
    827  1.26   briggs 			: "=g" (addr)
    828  1.26   briggs 			: "0" (addr), "g" (pdma), "g" (cnt32), "g" (cnt2)
    829  1.26   briggs 			: "a2", "a3", "d2");
    830  1.13   briggs 		if (esc->sc_pad) {
    831  1.50  tsutsui 			volatile uint8_t *c;
    832  1.50  tsutsui 			c = (volatile int8_t *)addr;
    833  1.26   briggs 			/* Wait for DREQ */
    834  1.26   briggs 			while (!esp_have_dreq(esc)) {
    835  1.26   briggs 				if (*statreg & 0x80) {
    836  1.50  tsutsui 					nofault = NULL;
    837  1.26   briggs 					goto gotintr;
    838  1.26   briggs 				}
    839  1.26   briggs 			}
    840  1.50  tsutsui 			*c = *(volatile uint8_t *)pdma;
    841  1.12   briggs 		}
    842  1.12   briggs 	}
    843  1.12   briggs 
    844  1.50  tsutsui 	nofault = NULL;
    845  1.12   briggs 
    846  1.26   briggs 	/*
    847  1.26   briggs 	 * If we have not received an interrupt yet, we should shortly,
    848  1.26   briggs 	 * and we can't prevent it, so return and wait for it.
    849  1.26   briggs 	 */
    850  1.12   briggs 	if ((*statreg & 0x80) == 0) {
    851  1.26   briggs #if DEBUG
    852  1.26   briggs 		if (mac68k_esp_debug) {
    853  1.26   briggs 			printf("g.\n");
    854  1.26   briggs 		}
    855  1.26   briggs #endif
    856  1.50  tsutsui 		if (espspl != -1)
    857  1.50  tsutsui 			splx(espspl);
    858  1.50  tsutsui 		espspl = -1;
    859  1.12   briggs 		return;
    860  1.12   briggs 	}
    861  1.12   briggs 
    862  1.12   briggs gotintr:
    863  1.26   briggs #if DEBUG
    864  1.26   briggs 	if (mac68k_esp_debug) {
    865  1.26   briggs 		printf("g!\n");
    866  1.26   briggs 	}
    867  1.26   briggs #endif
    868  1.51    hauke 	/*
    869  1.51    hauke 	 * We have been called from the MI ncr53c9x_intr() handler,
    870  1.51    hauke 	 * which protects itself against multiple invocation with a
    871  1.51    hauke 	 * simple_lock. Follow the example of ncr53c9x_poll().
    872  1.51    hauke 	 */
    873  1.51    hauke 	simple_unlock(&sc->sc_lock);
    874  1.12   briggs 	ncr53c9x_intr(sc);
    875  1.51    hauke 	simple_lock(&sc->sc_lock);
    876  1.50  tsutsui 	if (espspl != -1)
    877  1.50  tsutsui 		splx(espspl);
    878  1.50  tsutsui 	espspl = -1;
    879  1.16   briggs }
    880  1.16   briggs 
    881  1.23   briggs void
    882  1.37      chs esp_intr(void *sc)
    883  1.23   briggs {
    884  1.23   briggs 	struct esp_softc *esc = (struct esp_softc *)sc;
    885  1.23   briggs 
    886  1.26   briggs 	if (esc->sc_reg[NCR_STAT * 16] & 0x80) {
    887  1.50  tsutsui 		ncr53c9x_intr((struct ncr53c9x_softc *)esp0);
    888  1.26   briggs 	}
    889  1.23   briggs }
    890  1.23   briggs 
    891  1.23   briggs void
    892  1.37      chs esp_dualbus_intr(void *sc)
    893  1.16   briggs {
    894  1.26   briggs 	if (esp0 && (esp0->sc_reg[NCR_STAT * 16] & 0x80)) {
    895  1.50  tsutsui 		ncr53c9x_intr((struct ncr53c9x_softc *)esp0);
    896  1.26   briggs 	}
    897  1.22   briggs 
    898  1.26   briggs 	if (esp1 && (esp1->sc_reg[NCR_STAT * 16] & 0x80)) {
    899  1.50  tsutsui 		ncr53c9x_intr((struct ncr53c9x_softc *)esp1);
    900  1.26   briggs 	}
    901   1.1   briggs }
    902