esp.c revision 1.1
1 /* $NetBSD: esp.c,v 1.1 1996/10/29 06:08:58 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <scsi/scsi_all.h> 85 #include <scsi/scsiconf.h> 86 #include <scsi/scsi_message.h> 87 88 #include <machine/cpu.h> 89 #include <machine/param.h> 90 91 #if defined(__sparc__) 92 #define SPARC_DRIVER 93 #include <machine/autoconf.h> 94 #include <sparc/dev/sbusvar.h> 95 #include <sparc/dev/dmareg.h> 96 #include <sparc/dev/dmavar.h> 97 #include <sparc/dev/espreg.h> 98 #include <sparc/dev/espvar.h> 99 #else 100 #if (_MACHINE == mac68k) 101 #define MAC68K_DRIVER 102 #include <machine/viareg.h> 103 104 struct dma_softc { 105 struct esp_softc *sc_esp; 106 int sc_active; 107 int sc_datain; 108 size_t sc_dmasize; 109 size_t sc_dmatrans; 110 char **sc_dmaaddr; 111 size_t *sc_pdmalen; 112 }; 113 114 #include <mac68k/dev/espreg.h> 115 #include <mac68k/dev/espvar.h> 116 #undef ESPCMD_DMA 117 #define ESPCMD_DMA 0 /* No DMA */ 118 #undef ESPCMD_TRPAD 119 #define ESPCMD_TRPAD 0x98 /* TRPAD needs DMA flag*/ 120 121 static __inline__ void dma_intr __P((struct dma_softc *sc)); 122 123 static __inline__ void 124 dma_intr(sc) 125 struct dma_softc *sc; 126 { 127 u_char *p; 128 129 if (sc->sc_active == 0) { 130 printf("dma_intr--inactive\n"); 131 return; 132 } 133 134 p = *sc->sc_dmaaddr; 135 if (sc->sc_datain) { 136 if (ESP_READ_REG(sc->sc_esp, ESP_FFLAG) & ESPFIFO_FF) { 137 *p++ = ESP_READ_REG(sc->sc_esp, ESP_FIFO); 138 (*sc->sc_pdmalen)--; 139 } else { 140 printf("DMA, Data in, no data, pdmalen is %d\n", 141 *sc->sc_pdmalen); 142 } 143 *sc->sc_dmaaddr = p; 144 if (sc->sc_esp->sc_phase != DATA_IN_PHASE) { 145 if (*sc->sc_pdmalen == 0) { 146 /* 147 * Fake terminal count since this isn't 148 * a real DMA transaction and the chip 149 * will therefore not trip TC itself. 150 */ 151 sc->sc_esp->sc_espstat |= ESPSTAT_TC; 152 } 153 sc->sc_active = 0; 154 return; 155 } 156 ESPCMD(sc->sc_esp, ESPCMD_TRANS); 157 } else if (sc->sc_esp->sc_phase == DATA_OUT_PHASE) { 158 p++; 159 ESP_WRITE_REG(sc->sc_esp, ESP_FIFO, *p); 160 *sc->sc_dmaaddr = p; 161 (*sc->sc_pdmalen)--; 162 ESPCMD(sc->sc_esp, ESPCMD_TRANS); 163 } else { 164 if ( (sc->sc_esp->sc_prevphase == DATA_OUT_PHASE) 165 && (*sc->sc_pdmalen == 0)) { 166 sc->sc_esp->sc_espstat |= ESPSTAT_TC; 167 } 168 sc->sc_active = 0; 169 } 170 } 171 #else 172 #include <dev/tc/tcvar.h> 173 #include <alpha/tc/tcdsvar.h> 174 #include <alpha/tc/espreg.h> 175 #include <alpha/tc/espvar.h> 176 #endif 177 #endif 178 179 int esp_debug = 0; /*ESP_SHOWPHASE|ESP_SHOWMISC|ESP_SHOWTRAC|ESP_SHOWCMDS;*/ 180 181 /*static*/ void espattach __P((struct device *, struct device *, void *)); 182 /*static*/ int espmatch __P((struct device *, void *, void *)); 183 /*static*/ u_int esp_adapter_info __P((struct esp_softc *)); 184 /*static*/ void espreadregs __P((struct esp_softc *)); 185 /*static*/ void esp_select __P((struct esp_softc *, struct esp_ecb *)); 186 /*static*/ int esp_reselect __P((struct esp_softc *, int)); 187 /*static*/ void esp_scsi_reset __P((struct esp_softc *)); 188 /*static*/ void esp_reset __P((struct esp_softc *)); 189 /*static*/ void esp_init __P((struct esp_softc *, int)); 190 /*static*/ int esp_scsi_cmd __P((struct scsi_xfer *)); 191 /*static*/ int esp_poll __P((struct esp_softc *, struct scsi_xfer *, int)); 192 /*static*/ void esp_sched __P((struct esp_softc *)); 193 /*static*/ void esp_done __P((struct esp_softc *, struct esp_ecb *)); 194 /*static*/ void esp_msgin __P((struct esp_softc *)); 195 /*static*/ void esp_msgout __P((struct esp_softc *)); 196 /*static*/ int espintr __P((struct esp_softc *)); 197 /*static*/ void esp_timeout __P((void *arg)); 198 /*static*/ void esp_abort __P((struct esp_softc *, struct esp_ecb *)); 199 /*static*/ void esp_dequeue __P((struct esp_softc *, struct esp_ecb *)); 200 void esp_sense __P((struct esp_softc *, struct esp_ecb *)); 201 void esp_free_ecb __P((struct esp_softc *, struct esp_ecb *, int)); 202 struct esp_ecb *esp_get_ecb __P((struct esp_softc *, int)); 203 static inline int esp_stp2cpb __P((struct esp_softc *, int)); 204 static inline int esp_cpb2stp __P((struct esp_softc *, int)); 205 static inline void esp_setsync __P((struct esp_softc *, struct esp_tinfo *)); 206 207 /* Linkup to the rest of the kernel */ 208 struct cfattach esp_ca = { 209 sizeof(struct esp_softc), espmatch, espattach 210 }; 211 212 struct cfdriver esp_cd = { 213 NULL, "esp", DV_DULL 214 }; 215 216 struct scsi_adapter esp_switch = { 217 esp_scsi_cmd, 218 minphys, /* no max at this level; handled by DMA code */ 219 NULL, 220 NULL, 221 }; 222 223 struct scsi_device esp_dev = { 224 NULL, /* Use default error handler */ 225 NULL, /* have a queue, served by this */ 226 NULL, /* have no async handler */ 227 NULL, /* Use default 'done' routine */ 228 }; 229 230 int 231 espmatch(parent, vcf, aux) 232 struct device *parent; 233 void *vcf, *aux; 234 { 235 struct cfdata *cf = vcf; 236 #ifdef SPARC_DRIVER 237 register struct confargs *ca = aux; 238 register struct romaux *ra = &ca->ca_ra; 239 240 if (strcmp(cf->cf_driver->cd_name, ra->ra_name)) 241 return (0); 242 if (ca->ca_bustype == BUS_SBUS) 243 return (1); 244 ra->ra_len = NBPG; 245 return (probeget(ra->ra_vaddr, 1) != -1); 246 #else 247 #ifdef MAC68K_DRIVER 248 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) 249 return (1); 250 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) 251 return (1); 252 return (0); 253 #else 254 struct tcdsdev_attach_args *tcdsdev = aux; 255 256 if (strncmp(tcdsdev->tcdsda_modname, "PMAZ-AA ", TC_ROM_LLEN)) 257 return (0); 258 return (!tc_badaddr(tcdsdev->tcdsda_addr)); 259 #endif 260 #endif 261 } 262 263 /* 264 * Attach this instance, and then all the sub-devices 265 */ 266 void 267 espattach(parent, self, aux) 268 struct device *parent, *self; 269 void *aux; 270 { 271 #ifdef SPARC_DRIVER 272 register struct confargs *ca = aux; 273 #else 274 #ifdef MAC68K_DRIVER 275 extern vm_offset_t SCSIBase; 276 #else 277 register struct tcdsdev_attach_args *tcdsdev = aux; 278 #endif 279 #endif 280 struct esp_softc *sc = (void *)self; 281 #ifdef SPARC_DRIVER 282 struct bootpath *bp; 283 int dmachild = strncmp(parent->dv_xname, "dma", 3) == 0; 284 #endif 285 286 #ifdef SPARC_DRIVER 287 /* 288 * Make sure things are sane. I don't know if this is ever 289 * necessary, but it seem to be in all of Torek's code. 290 */ 291 if (ca->ca_ra.ra_nintr != 1) { 292 printf(": expected 1 interrupt, got %d\n", ca->ca_ra.ra_nintr); 293 return; 294 } 295 296 sc->sc_pri = ca->ca_ra.ra_intr[0].int_pri; 297 printf(" pri %d", sc->sc_pri); 298 299 /* 300 * Map my registers in, if they aren't already in virtual 301 * address space. 302 */ 303 if (ca->ca_ra.ra_vaddr) 304 sc->sc_reg = (volatile u_char *) ca->ca_ra.ra_vaddr; 305 else { 306 sc->sc_reg = (volatile u_char *) 307 mapiodev(ca->ca_ra.ra_reg, 0, ca->ca_ra.ra_len, ca->ca_bustype); 308 } 309 #else 310 #ifdef MAC68K_DRIVER 311 if (sc->sc_dev.dv_unit == 0) { 312 sc->sc_reg = (volatile u_char *) SCSIBase; 313 mac68k_register_scsi_irq((void (*)(void *)) espintr, sc); 314 sc->irq_mask = V2IF_SCSIIRQ; 315 } else { 316 sc->sc_reg = (volatile u_char *) SCSIBase + 0x400; 317 mac68k_register_scsi_b_irq((void (*)(void *)) espintr, sc); 318 sc->irq_mask = V2IF_SCSIDRQ; /* V2IF_T1? If so, fix ^^, too */ 319 } 320 sc->sc_dma = &sc->_sc_dma; 321 printf(": address %p", sc->sc_reg); 322 323 sc->sc_id = 7; 324 sc->sc_freq = 25000000; 325 #else 326 sc->sc_reg = (volatile u_int32_t *)tcdsdev->tcdsda_addr; 327 sc->sc_cookie = tcdsdev->tcdsda_cookie; 328 sc->sc_dma = tcdsdev->tcdsda_sc; 329 330 printf(": address %x", sc->sc_reg); 331 tcds_intr_establish(parent, sc->sc_cookie, TC_IPL_BIO, 332 (int (*)(void *))espintr, sc); 333 #endif 334 #endif 335 336 #ifdef SPARC_DRIVER 337 /* Other settings */ 338 sc->sc_node = ca->ca_ra.ra_node; 339 if (ca->ca_bustype == BUS_SBUS) { 340 sc->sc_id = getpropint(sc->sc_node, "initiator-id", 7); 341 sc->sc_freq = getpropint(sc->sc_node, "clock-frequency", -1); 342 } else { 343 sc->sc_id = 7; 344 sc->sc_freq = 24000000; 345 } 346 if (sc->sc_freq < 0) 347 sc->sc_freq = ((struct sbus_softc *) 348 sc->sc_dev.dv_parent)->sc_clockfreq; 349 #else 350 #ifdef MAC68K_DRIVER 351 #else 352 if (parent->dv_cfdata->cf_driver == &tcds_cd) { 353 sc->sc_id = tcdsdev->tcdsda_id; 354 sc->sc_freq = tcdsdev->tcdsda_freq; 355 } else { 356 /* XXX */ 357 sc->sc_id = 7; 358 sc->sc_freq = 24000000; 359 } 360 #endif 361 #endif 362 363 /* gimme Mhz */ 364 sc->sc_freq /= 1000000; 365 366 #ifdef SPARC_DRIVER 367 if (dmachild) { 368 sc->sc_dma = (struct dma_softc *)parent; 369 sc->sc_dma->sc_esp = sc; 370 } else { 371 /* 372 * find the DMA by poking around the dma device structures 373 * 374 * What happens here is that if the dma driver has not been 375 * configured, then this returns a NULL pointer. Then when the 376 * dma actually gets configured, it does the opposing test, and 377 * if the sc->sc_esp field in it's softc is NULL, then tries to 378 * find the matching esp driver. 379 * 380 */ 381 sc->sc_dma = (struct dma_softc *) 382 getdevunit("dma", sc->sc_dev.dv_unit); 383 384 /* 385 * and a back pointer to us, for DMA 386 */ 387 if (sc->sc_dma) 388 sc->sc_dma->sc_esp = sc; 389 else 390 panic("espattach: no dma found"); 391 } 392 #else 393 sc->sc_dma->sc_esp = sc; /* XXX */ 394 #endif 395 396 /* 397 * It is necessary to try to load the 2nd config register here, 398 * to find out what rev the esp chip is, else the esp_reset 399 * will not set up the defaults correctly. 400 */ 401 sc->sc_cfg1 = sc->sc_id | ESPCFG1_PARENB; 402 #ifdef SPARC_DRIVER 403 sc->sc_cfg2 = ESPCFG2_SCSI2 | ESPCFG2_RPE; 404 sc->sc_cfg3 = ESPCFG3_CDB; 405 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 406 407 if ((ESP_READ_REG(sc, ESP_CFG2) & ~ESPCFG2_RSVD) != (ESPCFG2_SCSI2 | ESPCFG2_RPE)) { 408 printf(": ESP100"); 409 sc->sc_rev = ESP100; 410 } else { 411 sc->sc_cfg2 = ESPCFG2_SCSI2; 412 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 413 sc->sc_cfg3 = 0; 414 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 415 sc->sc_cfg3 = (ESPCFG3_CDB | ESPCFG3_FCLK); 416 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 417 if (ESP_READ_REG(sc, ESP_CFG3) != (ESPCFG3_CDB | ESPCFG3_FCLK)) { 418 printf(": ESP100A"); 419 sc->sc_rev = ESP100A; 420 } else { 421 /* ESPCFG2_FE enables > 64K transfers */ 422 sc->sc_cfg2 |= ESPCFG2_FE; 423 sc->sc_cfg3 = 0; 424 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 425 printf(": ESP200"); 426 sc->sc_rev = ESP200; 427 } 428 } 429 #else 430 #ifdef MAC68K_DRIVER 431 sc->sc_cfg2 = ESPCFG2_SCSI2; 432 sc->sc_cfg3 = 0x4; 433 printf(": NCR53C96"); 434 sc->sc_rev = NCR53C96; 435 #else 436 sc->sc_cfg2 = ESPCFG2_SCSI2; 437 sc->sc_cfg3 = 0x4; /* Save residual byte. XXX??? */ 438 printf(": NCR53C94"); 439 sc->sc_rev = NCR53C94; 440 #endif 441 #endif 442 443 /* 444 * This is the value used to start sync negotiations 445 * Note that the ESP register "SYNCTP" is programmed 446 * in "clocks per byte", and has a minimum value of 4. 447 * The SCSI period used in negotiation is one-fourth 448 * of the time (in nanoseconds) needed to transfer one byte. 449 * Since the chip's clock is given in MHz, we have the following 450 * formula: 4 * period = (1000 / freq) * 4 451 */ 452 sc->sc_minsync = 1000 / sc->sc_freq; 453 454 #ifdef SPARC_DRIVER 455 /* 456 * Alas, we must now modify the value a bit, because it's 457 * only valid when can switch on FASTCLK and FASTSCSI bits 458 * in config register 3... 459 */ 460 switch (sc->sc_rev) { 461 case ESP100: 462 sc->sc_maxxfer = 64 * 1024; 463 sc->sc_minsync = 0; /* No synch on old chip? */ 464 break; 465 case ESP100A: 466 sc->sc_maxxfer = 64 * 1024; 467 sc->sc_minsync = esp_cpb2stp(sc, 5); /* Min clocks/byte is 5 */ 468 break; 469 case ESP200: 470 sc->sc_maxxfer = 16 * 1024 * 1024; 471 /* XXX - do actually set FAST* bits */ 472 } 473 #else 474 #ifdef MAC68K_DRIVER 475 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */ 476 /* Really no limit, but since we want to fit into the TCR... */ 477 sc->sc_maxxfer = 64 * 1024; 478 #else 479 sc->sc_maxxfer = 64 * 1024; 480 #endif 481 #endif 482 483 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 484 485 /* The value *must not* be == 1. Make it 2 */ 486 if (sc->sc_ccf == 1) 487 sc->sc_ccf = 2; 488 489 /* 490 * The recommended timeout is 250ms. This register is loaded 491 * with a value calculated as follows, from the docs: 492 * 493 * (timout period) x (CLK frequency) 494 * reg = ------------------------------------- 495 * 8192 x (Clock Conversion Factor) 496 * 497 * Since CCF has a linear relation to CLK, this generally computes 498 * to the constant of 153. 499 */ 500 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 501 502 /* CCF register only has 3 bits; 0 is actually 8 */ 503 sc->sc_ccf &= 7; 504 505 /* Reset state & bus */ 506 sc->sc_state = 0; 507 esp_init(sc, 1); 508 509 printf(" %dMhz, target %d\n", sc->sc_freq, sc->sc_id); 510 511 #ifdef SPARC_DRIVER 512 /* add me to the sbus structures */ 513 sc->sc_sd.sd_reset = (void *) esp_reset; 514 #if defined(SUN4C) || defined(SUN4M) 515 if (ca->ca_bustype == BUS_SBUS) { 516 if (dmachild) 517 sbus_establish(&sc->sc_sd, sc->sc_dev.dv_parent); 518 else 519 sbus_establish(&sc->sc_sd, &sc->sc_dev); 520 } 521 #endif /* SUN4C || SUN4M */ 522 #endif 523 524 #ifdef SPARC_DRIVER 525 /* and the interuppts */ 526 sc->sc_ih.ih_fun = (void *) espintr; 527 sc->sc_ih.ih_arg = sc; 528 intr_establish(sc->sc_pri, &sc->sc_ih); 529 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 530 #endif 531 532 /* 533 * fill in the prototype scsi_link. 534 */ 535 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 536 sc->sc_link.adapter_softc = sc; 537 sc->sc_link.adapter_target = sc->sc_id; 538 sc->sc_link.adapter = &esp_switch; 539 sc->sc_link.device = &esp_dev; 540 sc->sc_link.openings = 2; 541 542 /* 543 * If the boot path is "esp" at the moment and it's me, then 544 * walk our pointer to the sub-device, ready for the config 545 * below. 546 */ 547 #ifdef SPARC_DRIVER 548 bp = ca->ca_ra.ra_bp; 549 switch (ca->ca_bustype) { 550 case BUS_SBUS: 551 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 552 SAME_ESP(sc, bp, ca)) 553 bootpath_store(1, bp + 1); 554 break; 555 default: 556 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 557 bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit) 558 bootpath_store(1, bp + 1); 559 break; 560 } 561 #endif 562 563 /* 564 * Now try to attach all the sub-devices 565 */ 566 config_found(self, &sc->sc_link, scsiprint); 567 568 #ifdef MAC68K_DRIVER 569 via2_reg(vPCR) = 0x22; 570 via2_reg(vIFR) = sc->irq_mask; 571 via2_reg(vIER) = 0x80 | sc->irq_mask; 572 #endif 573 #ifdef SPARC_DRIVER 574 bootpath_store(1, NULL); 575 #endif 576 } 577 578 /* 579 * This is the generic esp reset function. It does not reset the SCSI bus, 580 * only this controllers, but kills any on-going commands, and also stops 581 * and resets the DMA. 582 * 583 * After reset, registers are loaded with the defaults from the attach 584 * routine above. 585 */ 586 void 587 esp_reset(sc) 588 struct esp_softc *sc; 589 { 590 591 /* reset DMA first */ 592 DMA_RESET(sc->sc_dma); 593 594 /* reset SCSI chip */ 595 ESPCMD(sc, ESPCMD_RSTCHIP); 596 ESPCMD(sc, ESPCMD_NOP); 597 DELAY(500); 598 599 /* do these backwards, and fall through */ 600 switch (sc->sc_rev) { 601 #ifndef SPARC_DRIVER 602 case NCR53C96: 603 case NCR53C94: 604 #endif 605 case ESP200: 606 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 607 case ESP100A: 608 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 609 case ESP100: 610 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 611 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 612 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 613 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 614 break; 615 default: 616 printf("%s: unknown revision code, assuming ESP100\n", 617 sc->sc_dev.dv_xname); 618 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 619 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 620 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 621 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 622 } 623 } 624 625 /* 626 * Reset the SCSI bus, but not the chip 627 */ 628 void 629 esp_scsi_reset(sc) 630 struct esp_softc *sc; 631 { 632 #ifdef SPARC_DRIVER 633 /* stop DMA first, as the chip will return to Bus Free phase */ 634 DMACSR(sc->sc_dma) &= ~D_EN_DMA; 635 #else 636 /* 637 * XXX STOP DMA FIRST 638 */ 639 #endif 640 641 printf("esp: resetting SCSI bus\n"); 642 ESPCMD(sc, ESPCMD_RSTSCSI); 643 } 644 645 /* 646 * Initialize esp state machine 647 */ 648 void 649 esp_init(sc, doreset) 650 struct esp_softc *sc; 651 int doreset; 652 { 653 struct esp_ecb *ecb; 654 int r; 655 656 ESP_TRACE(("[ESP_INIT(%d)] ", doreset)); 657 658 if (sc->sc_state == 0) { 659 /* First time through; initialize. */ 660 TAILQ_INIT(&sc->ready_list); 661 TAILQ_INIT(&sc->nexus_list); 662 TAILQ_INIT(&sc->free_list); 663 sc->sc_nexus = NULL; 664 ecb = sc->sc_ecb; 665 bzero(ecb, sizeof(sc->sc_ecb)); 666 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 667 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 668 ecb++; 669 } 670 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 671 } else { 672 /* Cancel any active commands. */ 673 sc->sc_state = ESP_CLEANING; 674 if ((ecb = sc->sc_nexus) != NULL) { 675 ecb->xs->error = XS_DRIVER_STUFFUP; 676 untimeout(esp_timeout, ecb); 677 esp_done(sc, ecb); 678 } 679 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 680 ecb->xs->error = XS_DRIVER_STUFFUP; 681 untimeout(esp_timeout, ecb); 682 esp_done(sc, ecb); 683 } 684 } 685 686 /* 687 * reset the chip to a known state 688 */ 689 esp_reset(sc); 690 691 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 692 for (r = 0; r < 8; r++) { 693 struct esp_tinfo *ti = &sc->sc_tinfo[r]; 694 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 695 int fl = sc->sc_dev.dv_cfdata->cf_flags; 696 697 ti->flags = ((sc->sc_minsync && !(fl & (1<<(r+8)))) 698 ? T_NEGOTIATE : 0) | 699 ((fl & (1<<r)) ? T_RSELECTOFF : 0) | 700 T_NEED_TO_RESET; 701 ti->period = sc->sc_minsync; 702 ti->offset = 0; 703 } 704 705 if (doreset) { 706 sc->sc_state = ESP_SBR; 707 ESPCMD(sc, ESPCMD_RSTSCSI); 708 } else { 709 sc->sc_state = ESP_IDLE; 710 } 711 } 712 713 /* 714 * Read the ESP registers, and save their contents for later use. 715 * ESP_STAT, ESP_STEP & ESP_INTR are mostly zeroed out when reading 716 * ESP_INTR - so make sure it is the last read. 717 * 718 * I think that (from reading the docs) most bits in these registers 719 * only make sense when he DMA CSR has an interrupt showing. Call only 720 * if an interrupt is pending. 721 */ 722 void 723 espreadregs(sc) 724 struct esp_softc *sc; 725 { 726 727 sc->sc_espstat = ESP_READ_REG(sc, ESP_STAT); 728 /* Only the stepo bits are of interest */ 729 sc->sc_espstep = ESP_READ_REG(sc, ESP_STEP) & ESPSTEP_MASK; 730 sc->sc_espintr = ESP_READ_REG(sc, ESP_INTR); 731 732 #if !defined(SPARC_DRIVER) && !defined(MAC68K_DRIVER) 733 /* Clear the TCDS interrupt bit. */ 734 (void)tcds_scsi_isintr(sc->sc_dma, 1); 735 #endif 736 737 /* 738 * Determine the SCSI bus phase, return either a real SCSI bus phase 739 * or some pseudo phase we use to detect certain exceptions. 740 */ 741 742 sc->sc_phase = (sc->sc_espintr & ESPINTR_DIS) 743 ? /* Disconnected */ BUSFREE_PHASE 744 : sc->sc_espstat & ESPSTAT_PHASE; 745 746 ESP_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 747 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 748 } 749 750 /* 751 * Convert chip register Clock Per Byte value to Synchronous Transfer Period. 752 */ 753 static inline int 754 esp_cpb2stp(sc, cpb) 755 struct esp_softc *sc; 756 int cpb; 757 { 758 return ((250 * cpb) / sc->sc_freq); 759 } 760 761 /* 762 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 763 */ 764 static inline int 765 esp_stp2cpb(sc, period) 766 struct esp_softc *sc; 767 int period; 768 { 769 int v; 770 v = (sc->sc_freq * period) / 250; 771 if (esp_cpb2stp(sc, v) < period) 772 /* Correct round-down error */ 773 v++; 774 return v; 775 } 776 777 static inline void 778 esp_setsync(sc, ti) 779 struct esp_softc *sc; 780 struct esp_tinfo *ti; 781 { 782 783 if (ti->flags & T_SYNCMODE) { 784 ESP_WRITE_REG(sc, ESP_SYNCOFF, ti->offset); 785 ESP_WRITE_REG(sc, ESP_SYNCTP, esp_stp2cpb(sc, ti->period)); 786 } else { 787 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 788 ESP_WRITE_REG(sc, ESP_SYNCTP, 0); 789 } 790 } 791 792 /* 793 * Send a command to a target, set the driver state to ESP_SELECTING 794 * and let the caller take care of the rest. 795 * 796 * Keeping this as a function allows me to say that this may be done 797 * by DMA instead of programmed I/O soon. 798 */ 799 void 800 esp_select(sc, ecb) 801 struct esp_softc *sc; 802 struct esp_ecb *ecb; 803 { 804 struct scsi_link *sc_link = ecb->xs->sc_link; 805 int target = sc_link->target; 806 struct esp_tinfo *ti = &sc->sc_tinfo[target]; 807 u_char *cmd; 808 int clen; 809 810 ESP_TRACE(("[esp_select(t%d,l%d,cmd:%x)] ", sc_link->target, sc_link->lun, ecb->cmd.opcode)); 811 812 /* new state ESP_SELECTING */ 813 sc->sc_state = ESP_SELECTING; 814 815 ESPCMD(sc, ESPCMD_FLUSH); 816 817 /* 818 * The docs say the target register is never reset, and I 819 * can't think of a better place to set it 820 */ 821 ESP_WRITE_REG(sc, ESP_SELID, target); 822 esp_setsync(sc, ti); 823 824 /* 825 * Who am I. This is where we tell the target that we are 826 * happy for it to disconnect etc. 827 */ 828 ESP_WRITE_REG(sc, ESP_FIFO, 829 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 830 831 if (ti->flags & T_NEGOTIATE) { 832 /* Arbitrate, select and stop after IDENTIFY message */ 833 ESPCMD(sc, ESPCMD_SELATNS); 834 return; 835 } 836 837 /* Now the command into the FIFO */ 838 cmd = (u_char *)&ecb->cmd; 839 clen = ecb->clen; 840 while (clen--) 841 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 842 843 /* And get the targets attention */ 844 ESPCMD(sc, ESPCMD_SELATN); 845 } 846 847 void 848 esp_free_ecb(sc, ecb, flags) 849 struct esp_softc *sc; 850 struct esp_ecb *ecb; 851 int flags; 852 { 853 int s; 854 855 s = splbio(); 856 857 ecb->flags = 0; 858 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 859 860 /* 861 * If there were none, wake anybody waiting for one to come free, 862 * starting with queued entries. 863 */ 864 if (ecb->chain.tqe_next == 0) 865 wakeup(&sc->free_list); 866 867 splx(s); 868 } 869 870 struct esp_ecb * 871 esp_get_ecb(sc, flags) 872 struct esp_softc *sc; 873 int flags; 874 { 875 struct esp_ecb *ecb; 876 int s; 877 878 s = splbio(); 879 880 while ((ecb = sc->free_list.tqh_first) == NULL && 881 (flags & SCSI_NOSLEEP) == 0) 882 tsleep(&sc->free_list, PRIBIO, "especb", 0); 883 if (ecb) { 884 TAILQ_REMOVE(&sc->free_list, ecb, chain); 885 ecb->flags |= ECB_ALLOC; 886 } 887 888 splx(s); 889 return ecb; 890 } 891 892 /* 893 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 894 */ 895 896 /* 897 * Start a SCSI-command 898 * This function is called by the higher level SCSI-driver to queue/run 899 * SCSI-commands. 900 */ 901 int 902 esp_scsi_cmd(xs) 903 struct scsi_xfer *xs; 904 { 905 struct scsi_link *sc_link = xs->sc_link; 906 struct esp_softc *sc = sc_link->adapter_softc; 907 struct esp_ecb *ecb; 908 int s, flags; 909 910 ESP_TRACE(("[esp_scsi_cmd] ")); 911 ESP_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 912 sc_link->target)); 913 914 flags = xs->flags; 915 if ((ecb = esp_get_ecb(sc, flags)) == NULL) { 916 xs->error = XS_DRIVER_STUFFUP; 917 return TRY_AGAIN_LATER; 918 } 919 920 /* Initialize ecb */ 921 ecb->xs = xs; 922 ecb->timeout = xs->timeout; 923 924 if (xs->flags & SCSI_RESET) { 925 ecb->flags |= ECB_RESET; 926 ecb->clen = 0; 927 ecb->dleft = 0; 928 } else { 929 bcopy(xs->cmd, &ecb->cmd, xs->cmdlen); 930 ecb->clen = xs->cmdlen; 931 ecb->daddr = xs->data; 932 ecb->dleft = xs->datalen; 933 } 934 ecb->stat = 0; 935 936 s = splbio(); 937 938 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 939 if (sc->sc_state == ESP_IDLE) 940 esp_sched(sc); 941 942 splx(s); 943 944 if ((flags & SCSI_POLL) == 0) 945 return SUCCESSFULLY_QUEUED; 946 947 /* Not allowed to use interrupts, use polling instead */ 948 if (esp_poll(sc, xs, ecb->timeout)) { 949 esp_timeout(ecb); 950 if (esp_poll(sc, xs, ecb->timeout)) 951 esp_timeout(ecb); 952 } 953 return COMPLETE; 954 } 955 956 /* 957 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 958 */ 959 int 960 esp_poll(sc, xs, count) 961 struct esp_softc *sc; 962 struct scsi_xfer *xs; 963 int count; 964 { 965 966 ESP_TRACE(("[esp_poll] ")); 967 while (count) { 968 if (DMA_ISINTR(sc->sc_dma)) { 969 espintr(sc); 970 } 971 #if alternatively 972 if (ESP_READ_REG(sc, ESP_STAT) & ESPSTAT_INT) 973 espintr(sc); 974 #endif 975 if ((xs->flags & ITSDONE) != 0) 976 return 0; 977 if (sc->sc_state == ESP_IDLE) { 978 ESP_TRACE(("[esp_poll: rescheduling] ")); 979 esp_sched(sc); 980 } 981 DELAY(1000); 982 count--; 983 } 984 return 1; 985 } 986 987 988 /* 989 * LOW LEVEL SCSI UTILITIES 990 */ 991 992 /* 993 * Schedule a scsi operation. This has now been pulled out of the interrupt 994 * handler so that we may call it from esp_scsi_cmd and esp_done. This may 995 * save us an unecessary interrupt just to get things going. Should only be 996 * called when state == ESP_IDLE and at bio pl. 997 */ 998 void 999 esp_sched(sc) 1000 struct esp_softc *sc; 1001 { 1002 struct esp_ecb *ecb; 1003 struct scsi_link *sc_link; 1004 struct esp_tinfo *ti; 1005 1006 ESP_TRACE(("[esp_sched] ")); 1007 if (sc->sc_state != ESP_IDLE) 1008 panic("esp_sched: not IDLE (state=%d)", sc->sc_state); 1009 1010 /* 1011 * Find first ecb in ready queue that is for a target/lunit 1012 * combinations that is not busy. 1013 */ 1014 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 1015 sc_link = ecb->xs->sc_link; 1016 ti = &sc->sc_tinfo[sc_link->target]; 1017 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 1018 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1019 sc->sc_nexus = ecb; 1020 esp_select(sc, ecb); 1021 break; 1022 } else 1023 ESP_MISC(("%d:%d busy\n", 1024 sc_link->target, sc_link->lun)); 1025 } 1026 } 1027 1028 void 1029 esp_sense(sc, ecb) 1030 struct esp_softc *sc; 1031 struct esp_ecb *ecb; 1032 { 1033 struct scsi_xfer *xs = ecb->xs; 1034 struct scsi_link *sc_link = xs->sc_link; 1035 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1036 struct scsi_sense *ss = (void *)&ecb->cmd; 1037 1038 ESP_MISC(("requesting sense ")); 1039 /* Next, setup a request sense command block */ 1040 bzero(ss, sizeof(*ss)); 1041 ss->opcode = REQUEST_SENSE; 1042 ss->byte2 = sc_link->lun << 5; 1043 ss->length = sizeof(struct scsi_sense_data); 1044 ecb->clen = sizeof(*ss); 1045 ecb->daddr = (char *)&xs->sense; 1046 ecb->dleft = sizeof(struct scsi_sense_data); 1047 ecb->flags |= ECB_SENSE; 1048 ti->senses++; 1049 if (ecb->flags & ECB_NEXUS) 1050 ti->lubusy &= ~(1 << sc_link->lun); 1051 if (ecb == sc->sc_nexus) { 1052 esp_select(sc, ecb); 1053 } else { 1054 esp_dequeue(sc, ecb); 1055 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1056 if (sc->sc_state == ESP_IDLE) 1057 esp_sched(sc); 1058 } 1059 } 1060 1061 /* 1062 * POST PROCESSING OF SCSI_CMD (usually current) 1063 */ 1064 void 1065 esp_done(sc, ecb) 1066 struct esp_softc *sc; 1067 struct esp_ecb *ecb; 1068 { 1069 struct scsi_xfer *xs = ecb->xs; 1070 struct scsi_link *sc_link = xs->sc_link; 1071 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1072 1073 ESP_TRACE(("[esp_done(error:%x)] ", xs->error)); 1074 1075 /* 1076 * Now, if we've come here with no error code, i.e. we've kept the 1077 * initial XS_NOERROR, and the status code signals that we should 1078 * check sense, we'll need to set up a request sense cmd block and 1079 * push the command back into the ready queue *before* any other 1080 * commands for this target/lunit, else we lose the sense info. 1081 * We don't support chk sense conditions for the request sense cmd. 1082 */ 1083 if (xs->error == XS_NOERROR) { 1084 if ((ecb->flags & ECB_ABORT) != 0) { 1085 xs->error = XS_DRIVER_STUFFUP; 1086 } else if ((ecb->flags & ECB_SENSE) != 0) { 1087 xs->error = XS_SENSE; 1088 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 1089 /* First, save the return values */ 1090 xs->resid = ecb->dleft; 1091 xs->status = ecb->stat; 1092 esp_sense(sc, ecb); 1093 return; 1094 } else { 1095 xs->resid = ecb->dleft; 1096 } 1097 } 1098 1099 xs->flags |= ITSDONE; 1100 1101 #ifdef ESP_DEBUG 1102 if (esp_debug & ESP_SHOWMISC) { 1103 if (xs->resid != 0) 1104 printf("resid=%d ", xs->resid); 1105 if (xs->error == XS_SENSE) 1106 printf("sense=0x%02x\n", xs->sense.error_code); 1107 else 1108 printf("error=%d\n", xs->error); 1109 } 1110 #endif 1111 1112 /* 1113 * Remove the ECB from whatever queue it's on. 1114 */ 1115 if (ecb->flags & ECB_NEXUS) 1116 ti->lubusy &= ~(1 << sc_link->lun); 1117 if (ecb == sc->sc_nexus) { 1118 sc->sc_nexus = NULL; 1119 sc->sc_state = ESP_IDLE; 1120 esp_sched(sc); 1121 } else 1122 esp_dequeue(sc, ecb); 1123 1124 esp_free_ecb(sc, ecb, xs->flags); 1125 ti->cmds++; 1126 scsi_done(xs); 1127 } 1128 1129 void 1130 esp_dequeue(sc, ecb) 1131 struct esp_softc *sc; 1132 struct esp_ecb *ecb; 1133 { 1134 1135 if (ecb->flags & ECB_NEXUS) { 1136 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1137 } else { 1138 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1139 } 1140 } 1141 1142 /* 1143 * INTERRUPT/PROTOCOL ENGINE 1144 */ 1145 1146 /* 1147 * Schedule an outgoing message by prioritizing it, and asserting 1148 * attention on the bus. We can only do this when we are the initiator 1149 * else there will be an illegal command interrupt. 1150 */ 1151 #define esp_sched_msgout(m) \ 1152 do { \ 1153 ESP_MISC(("esp_sched_msgout %d ", m)); \ 1154 ESPCMD(sc, ESPCMD_SETATN); \ 1155 sc->sc_flags |= ESP_ATN; \ 1156 sc->sc_msgpriq |= (m); \ 1157 } while (0) 1158 1159 int 1160 esp_reselect(sc, message) 1161 struct esp_softc *sc; 1162 int message; 1163 { 1164 u_char selid, target, lun; 1165 struct esp_ecb *ecb; 1166 struct scsi_link *sc_link; 1167 struct esp_tinfo *ti; 1168 1169 /* 1170 * The SCSI chip made a snapshot of the data bus while the reselection 1171 * was being negotiated. This enables us to determine which target did 1172 * the reselect. 1173 */ 1174 selid = sc->sc_selid & ~(1 << sc->sc_id); 1175 if (selid & (selid - 1)) { 1176 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 1177 sc->sc_dev.dv_xname, selid); 1178 goto reset; 1179 } 1180 1181 /* 1182 * Search wait queue for disconnected cmd 1183 * The list should be short, so I haven't bothered with 1184 * any more sophisticated structures than a simple 1185 * singly linked list. 1186 */ 1187 target = ffs(selid) - 1; 1188 lun = message & 0x07; 1189 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 1190 ecb = ecb->chain.tqe_next) { 1191 sc_link = ecb->xs->sc_link; 1192 if (sc_link->target == target && sc_link->lun == lun) 1193 break; 1194 } 1195 if (ecb == NULL) { 1196 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 1197 sc->sc_dev.dv_xname, target, lun); 1198 goto abort; 1199 } 1200 1201 /* Make this nexus active again. */ 1202 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1203 sc->sc_state = ESP_CONNECTED; 1204 sc->sc_nexus = ecb; 1205 ti = &sc->sc_tinfo[target]; 1206 ti->lubusy |= (1 << lun); 1207 esp_setsync(sc, ti); 1208 1209 if (ecb->flags & ECB_RESET) 1210 esp_sched_msgout(SEND_DEV_RESET); 1211 else if (ecb->flags & ECB_ABORT) 1212 esp_sched_msgout(SEND_ABORT); 1213 1214 /* Do an implicit RESTORE POINTERS. */ 1215 sc->sc_dp = ecb->daddr; 1216 sc->sc_dleft = ecb->dleft; 1217 1218 return (0); 1219 1220 reset: 1221 esp_sched_msgout(SEND_DEV_RESET); 1222 return (1); 1223 1224 abort: 1225 esp_sched_msgout(SEND_ABORT); 1226 return (1); 1227 } 1228 1229 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 1230 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1231 #define ISEXTMSG(m) ((m) == 1) 1232 1233 /* 1234 * Get an incoming message as initiator. 1235 * 1236 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1237 * byte in the FIFO 1238 */ 1239 void 1240 esp_msgin(sc) 1241 register struct esp_softc *sc; 1242 { 1243 register int v; 1244 1245 ESP_TRACE(("[esp_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1246 1247 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) == 0) { 1248 printf("%s: msgin: no msg byte available\n", 1249 sc->sc_dev.dv_xname); 1250 return; 1251 } 1252 1253 /* 1254 * Prepare for a new message. A message should (according 1255 * to the SCSI standard) be transmitted in one single 1256 * MESSAGE_IN_PHASE. If we have been in some other phase, 1257 * then this is a new message. 1258 */ 1259 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1260 sc->sc_flags &= ~ESP_DROP_MSGI; 1261 sc->sc_imlen = 0; 1262 } 1263 1264 v = ESP_READ_REG(sc, ESP_FIFO); 1265 ESP_MISC(("<msgbyte:0x%02x>", v)); 1266 1267 #if 0 1268 if (sc->sc_state == ESP_RESELECTED && sc->sc_imlen == 0) { 1269 /* 1270 * Which target is reselecting us? (The ID bit really) 1271 */ 1272 sc->sc_selid = v; 1273 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1274 return; 1275 } 1276 #endif 1277 1278 sc->sc_imess[sc->sc_imlen] = v; 1279 1280 /* 1281 * If we're going to reject the message, don't bother storing 1282 * the incoming bytes. But still, we need to ACK them. 1283 */ 1284 1285 if ((sc->sc_flags & ESP_DROP_MSGI)) { 1286 ESPCMD(sc, ESPCMD_MSGOK); 1287 printf("<dropping msg byte %x>", 1288 sc->sc_imess[sc->sc_imlen]); 1289 return; 1290 } 1291 1292 if (sc->sc_imlen >= ESP_MAX_MSG_LEN) { 1293 esp_sched_msgout(SEND_REJECT); 1294 sc->sc_flags |= ESP_DROP_MSGI; 1295 } else { 1296 sc->sc_imlen++; 1297 /* 1298 * This testing is suboptimal, but most 1299 * messages will be of the one byte variety, so 1300 * it should not effect performance 1301 * significantly. 1302 */ 1303 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1304 goto gotit; 1305 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1306 goto gotit; 1307 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1308 sc->sc_imlen == sc->sc_imess[1] + 2) 1309 goto gotit; 1310 } 1311 /* Ack what we have so far */ 1312 ESPCMD(sc, ESPCMD_MSGOK); 1313 return; 1314 1315 gotit: 1316 ESP_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1317 /* 1318 * Now we should have a complete message (1 byte, 2 byte 1319 * and moderately long extended messages). We only handle 1320 * extended messages which total length is shorter than 1321 * ESP_MAX_MSG_LEN. Longer messages will be amputated. 1322 */ 1323 switch (sc->sc_state) { 1324 struct esp_ecb *ecb; 1325 struct esp_tinfo *ti; 1326 1327 case ESP_CONNECTED: 1328 ecb = sc->sc_nexus; 1329 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1330 1331 switch (sc->sc_imess[0]) { 1332 case MSG_CMDCOMPLETE: 1333 ESP_MSGS(("cmdcomplete ")); 1334 if (sc->sc_dleft < 0) { 1335 struct scsi_link *sc_link = ecb->xs->sc_link; 1336 printf("%s: %d extra bytes from %d:%d\n", 1337 sc->sc_dev.dv_xname, -sc->sc_dleft, 1338 sc_link->target, sc_link->lun); 1339 sc->sc_dleft = 0; 1340 } 1341 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 1342 sc->sc_state = ESP_CMDCOMPLETE; 1343 break; 1344 1345 case MSG_MESSAGE_REJECT: 1346 if (esp_debug & ESP_SHOWMSGS) 1347 printf("%s: our msg rejected by target\n", 1348 sc->sc_dev.dv_xname); 1349 switch (sc->sc_msgout) { 1350 case SEND_SDTR: 1351 sc->sc_flags &= ~ESP_SYNCHNEGO; 1352 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1353 esp_setsync(sc, ti); 1354 break; 1355 case SEND_INIT_DET_ERR: 1356 goto abort; 1357 } 1358 break; 1359 1360 case MSG_NOOP: 1361 ESP_MSGS(("noop ")); 1362 break; 1363 1364 case MSG_DISCONNECT: 1365 ESP_MSGS(("disconnect ")); 1366 ti->dconns++; 1367 sc->sc_state = ESP_DISCONNECT; 1368 if ((ecb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1369 break; 1370 /*FALLTHROUGH*/ 1371 1372 case MSG_SAVEDATAPOINTER: 1373 ESP_MSGS(("save datapointer ")); 1374 ecb->daddr = sc->sc_dp; 1375 ecb->dleft = sc->sc_dleft; 1376 break; 1377 1378 case MSG_RESTOREPOINTERS: 1379 ESP_MSGS(("restore datapointer ")); 1380 sc->sc_dp = ecb->daddr; 1381 sc->sc_dleft = ecb->dleft; 1382 break; 1383 1384 case MSG_EXTENDED: 1385 ESP_MSGS(("extended(%x) ", sc->sc_imess[2])); 1386 switch (sc->sc_imess[2]) { 1387 case MSG_EXT_SDTR: 1388 ESP_MSGS(("SDTR period %d, offset %d ", 1389 sc->sc_imess[3], sc->sc_imess[4])); 1390 if (sc->sc_imess[1] != 3) 1391 goto reject; 1392 ti->period = sc->sc_imess[3]; 1393 ti->offset = sc->sc_imess[4]; 1394 ti->flags &= ~T_NEGOTIATE; 1395 if (sc->sc_minsync == 0 || 1396 ti->offset == 0 || 1397 ti->period > 124) { 1398 printf("%s:%d: async\n", "esp", 1399 ecb->xs->sc_link->target); 1400 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1401 /* target initiated negotiation */ 1402 ti->offset = 0; 1403 ti->flags &= ~T_SYNCMODE; 1404 esp_sched_msgout(SEND_SDTR); 1405 } else { 1406 /* we are async */ 1407 ti->flags &= ~T_SYNCMODE; 1408 } 1409 } else { 1410 int r = 250/ti->period; 1411 int s = (100*250)/ti->period - 100*r; 1412 int p; 1413 1414 p = esp_stp2cpb(sc, ti->period); 1415 ti->period = esp_cpb2stp(sc, p); 1416 #ifdef ESP_DEBUG 1417 sc_print_addr(ecb->xs->sc_link); 1418 printf("max sync rate %d.%02dMb/s\n", 1419 r, s); 1420 #endif 1421 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1422 /* target initiated negotiation */ 1423 if (ti->period < sc->sc_minsync) 1424 ti->period = sc->sc_minsync; 1425 if (ti->offset > 15) 1426 ti->offset = 15; 1427 ti->flags &= ~T_SYNCMODE; 1428 esp_sched_msgout(SEND_SDTR); 1429 } else { 1430 /* we are sync */ 1431 ti->flags |= T_SYNCMODE; 1432 } 1433 } 1434 sc->sc_flags &= ~ESP_SYNCHNEGO; 1435 esp_setsync(sc, ti); 1436 break; 1437 1438 default: 1439 printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n", 1440 sc->sc_dev.dv_xname); 1441 goto reject; 1442 } 1443 break; 1444 1445 default: 1446 ESP_MSGS(("ident ")); 1447 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1448 sc->sc_dev.dv_xname); 1449 reject: 1450 esp_sched_msgout(SEND_REJECT); 1451 break; 1452 } 1453 break; 1454 1455 case ESP_RESELECTED: 1456 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1457 printf("%s: reselect without IDENTIFY; sending DEVICE RESET\n", 1458 sc->sc_dev.dv_xname); 1459 goto reset; 1460 } 1461 1462 (void) esp_reselect(sc, sc->sc_imess[0]); 1463 break; 1464 1465 default: 1466 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1467 sc->sc_dev.dv_xname); 1468 reset: 1469 esp_sched_msgout(SEND_DEV_RESET); 1470 break; 1471 1472 abort: 1473 esp_sched_msgout(SEND_ABORT); 1474 break; 1475 } 1476 1477 /* Ack last message byte */ 1478 ESPCMD(sc, ESPCMD_MSGOK); 1479 1480 /* Done, reset message pointer. */ 1481 sc->sc_flags &= ~ESP_DROP_MSGI; 1482 sc->sc_imlen = 0; 1483 } 1484 1485 1486 /* 1487 * Send the highest priority, scheduled message 1488 */ 1489 void 1490 esp_msgout(sc) 1491 register struct esp_softc *sc; 1492 { 1493 struct esp_tinfo *ti; 1494 struct esp_ecb *ecb; 1495 size_t size; 1496 1497 ESP_TRACE(("[esp_msgout(priq:%x, prevphase:%x)]", sc->sc_msgpriq, sc->sc_prevphase)); 1498 1499 if (sc->sc_flags & ESP_ATN) { 1500 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1501 new: 1502 ESPCMD(sc, ESPCMD_FLUSH); 1503 DELAY(1); 1504 sc->sc_msgoutq = 0; 1505 sc->sc_omlen = 0; 1506 } 1507 } else { 1508 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1509 esp_sched_msgout(sc->sc_msgoutq); 1510 goto new; 1511 } else { 1512 printf("esp at line %d: unexpected MESSAGE OUT phase\n", __LINE__); 1513 } 1514 } 1515 1516 if (sc->sc_omlen == 0) { 1517 /* Pick up highest priority message */ 1518 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1519 sc->sc_msgoutq |= sc->sc_msgout; 1520 sc->sc_msgpriq &= ~sc->sc_msgout; 1521 sc->sc_omlen = 1; /* "Default" message len */ 1522 switch (sc->sc_msgout) { 1523 case SEND_SDTR: 1524 ecb = sc->sc_nexus; 1525 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1526 sc->sc_omess[0] = MSG_EXTENDED; 1527 sc->sc_omess[1] = 3; 1528 sc->sc_omess[2] = MSG_EXT_SDTR; 1529 sc->sc_omess[3] = ti->period; 1530 sc->sc_omess[4] = ti->offset; 1531 sc->sc_omlen = 5; 1532 if ((sc->sc_flags & ESP_SYNCHNEGO) == 0) { 1533 ti->flags |= T_SYNCMODE; 1534 esp_setsync(sc, ti); 1535 } 1536 break; 1537 case SEND_IDENTIFY: 1538 if (sc->sc_state != ESP_CONNECTED) { 1539 printf("esp at line %d: no nexus\n", __LINE__); 1540 } 1541 ecb = sc->sc_nexus; 1542 sc->sc_omess[0] = MSG_IDENTIFY(ecb->xs->sc_link->lun,0); 1543 break; 1544 case SEND_DEV_RESET: 1545 sc->sc_flags |= ESP_ABORTING; 1546 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1547 ecb = sc->sc_nexus; 1548 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1549 ti->flags &= ~T_SYNCMODE; 1550 ti->flags |= T_NEGOTIATE; 1551 break; 1552 case SEND_PARITY_ERROR: 1553 sc->sc_omess[0] = MSG_PARITY_ERROR; 1554 break; 1555 case SEND_ABORT: 1556 sc->sc_flags |= ESP_ABORTING; 1557 sc->sc_omess[0] = MSG_ABORT; 1558 break; 1559 case SEND_INIT_DET_ERR: 1560 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1561 break; 1562 case SEND_REJECT: 1563 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1564 break; 1565 default: 1566 ESPCMD(sc, ESPCMD_RSTATN); 1567 sc->sc_flags &= ~ESP_ATN; 1568 sc->sc_omess[0] = MSG_NOOP; 1569 break; 1570 } 1571 sc->sc_omp = sc->sc_omess; 1572 } 1573 1574 #if 1 1575 /* (re)send the message */ 1576 size = min(sc->sc_omlen, sc->sc_maxxfer); 1577 DMA_SETUP(sc->sc_dma, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1578 /* Program the SCSI counter */ 1579 ESP_WRITE_REG(sc, ESP_TCL, size); 1580 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 1581 if (sc->sc_cfg2 & ESPCFG2_FE) { 1582 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 1583 } 1584 /* load the count in */ 1585 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 1586 ESPCMD(sc, ESPCMD_TRANS|ESPCMD_DMA); 1587 DMA_GO(sc->sc_dma); 1588 #else 1589 { int i; 1590 for (i = 0; i < sc->sc_omlen; i++) 1591 ESP_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1592 ESPCMD(sc, ESPCMD_TRANS); 1593 sc->sc_omlen = 0; 1594 } 1595 #endif 1596 } 1597 1598 /* 1599 * This is the most critical part of the driver, and has to know 1600 * how to deal with *all* error conditions and phases from the SCSI 1601 * bus. If there are no errors and the DMA was active, then call the 1602 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1603 * and we can return from here without further processing. 1604 * 1605 * Most of this needs verifying. 1606 */ 1607 int 1608 espintr(sc) 1609 register struct esp_softc *sc; 1610 { 1611 register struct esp_ecb *ecb; 1612 register struct scsi_link *sc_link; 1613 struct esp_tinfo *ti; 1614 int loop; 1615 size_t size; 1616 1617 ESP_TRACE(("[espintr]")); 1618 1619 /* 1620 * I have made some (maybe seriously flawed) assumptions here, 1621 * but basic testing (uncomment the printf() below), show that 1622 * certainly something happens when this loop is here. 1623 * 1624 * The idea is that many of the SCSI operations take very little 1625 * time, and going away and getting interrupted is too high an 1626 * overhead to pay. For example, selecting, sending a message 1627 * and command and then doing some work can be done in one "pass". 1628 * 1629 * The DELAY is not variable because I do not understand that the 1630 * DELAY loop should be fixed-time regardless of CPU speed, but 1631 * I am *assuming* that the faster SCSI processors get things done 1632 * quicker (sending a command byte etc), and so there is no 1633 * need to be too slow. 1634 * 1635 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1636 * at 40Mhz. This needs testing. 1637 */ 1638 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1639 /* a feeling of deja-vu */ 1640 if (!DMA_ISINTR(sc->sc_dma)) 1641 return (loop != 0); 1642 #if 0 1643 if (loop) 1644 printf("*"); 1645 #endif 1646 1647 /* and what do the registers say... */ 1648 espreadregs(sc); 1649 1650 sc->sc_intrcnt.ev_count++; 1651 1652 /* 1653 * At the moment, only a SCSI Bus Reset or Illegal 1654 * Command are classed as errors. A disconnect is a 1655 * valid condition, and we let the code check is the 1656 * "ESP_BUSFREE_OK" flag was set before declaring it 1657 * and error. 1658 * 1659 * Also, the status register tells us about "Gross 1660 * Errors" and "Parity errors". Only the Gross Error 1661 * is really bad, and the parity errors are dealt 1662 * with later 1663 * 1664 * TODO 1665 * If there are too many parity error, go to slow 1666 * cable mode ? 1667 */ 1668 1669 /* SCSI Reset */ 1670 if (sc->sc_espintr & ESPINTR_SBR) { 1671 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1672 ESPCMD(sc, ESPCMD_FLUSH); 1673 DELAY(1); 1674 } 1675 if (sc->sc_state != ESP_SBR) { 1676 printf("%s: SCSI bus reset\n", 1677 sc->sc_dev.dv_xname); 1678 esp_init(sc, 0); /* Restart everything */ 1679 return 1; 1680 } 1681 #if 0 1682 /*XXX*/ printf("<expected bus reset: " 1683 "[intr %x, stat %x, step %d]>\n", 1684 sc->sc_espintr, sc->sc_espstat, 1685 sc->sc_espstep); 1686 #endif 1687 if (sc->sc_nexus) 1688 panic("%s: nexus in reset state", 1689 sc->sc_dev.dv_xname); 1690 goto sched; 1691 } 1692 1693 ecb = sc->sc_nexus; 1694 1695 #define ESPINTR_ERR (ESPINTR_SBR|ESPINTR_ILL) 1696 if (sc->sc_espintr & ESPINTR_ERR || 1697 sc->sc_espstat & ESPSTAT_GE) { 1698 1699 if (sc->sc_espstat & ESPSTAT_GE) { 1700 /* no target ? */ 1701 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1702 ESPCMD(sc, ESPCMD_FLUSH); 1703 DELAY(1); 1704 } 1705 if (sc->sc_state == ESP_CONNECTED || 1706 sc->sc_state == ESP_SELECTING) { 1707 ecb->xs->error = XS_DRIVER_STUFFUP; 1708 esp_done(sc, ecb); 1709 } 1710 return 1; 1711 } 1712 1713 if (sc->sc_espintr & ESPINTR_ILL) { 1714 /* illegal command, out of sync ? */ 1715 printf("%s: illegal command: 0x%x (state %d, phase %x, prevphase %x)\n", 1716 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1717 sc->sc_state, sc->sc_phase, 1718 sc->sc_prevphase); 1719 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1720 ESPCMD(sc, ESPCMD_FLUSH); 1721 DELAY(1); 1722 } 1723 esp_init(sc, 0); /* Restart everything */ 1724 return 1; 1725 } 1726 } 1727 1728 /* 1729 * Call if DMA is active. 1730 * 1731 * If DMA_INTR returns true, then maybe go 'round the loop 1732 * again in case there is no more DMA queued, but a phase 1733 * change is expected. 1734 */ 1735 if (DMA_ISACTIVE(sc->sc_dma)) { 1736 DMA_INTR(sc->sc_dma); 1737 /* If DMA active here, then go back to work... */ 1738 if (DMA_ISACTIVE(sc->sc_dma)) 1739 return 1; 1740 1741 if (sc->sc_dleft == 0 && 1742 (sc->sc_espstat & ESPSTAT_TC) == 0) 1743 printf("%s: !TC [intr %x, stat %x, step %d]" 1744 " prevphase %x, resid %x\n", 1745 sc->sc_dev.dv_xname, 1746 sc->sc_espintr, 1747 sc->sc_espstat, 1748 sc->sc_espstep, 1749 sc->sc_prevphase, 1750 ecb?ecb->dleft:-1); 1751 } 1752 1753 #if 0 /* Unreliable on some ESP revisions? */ 1754 if ((sc->sc_espstat & ESPSTAT_INT) == 0) { 1755 printf("%s: spurious interrupt\n", sc->sc_dev.dv_xname); 1756 return 1; 1757 } 1758 #endif 1759 1760 /* 1761 * check for less serious errors 1762 */ 1763 if (sc->sc_espstat & ESPSTAT_PE) { 1764 printf("%s: SCSI bus parity error\n", 1765 sc->sc_dev.dv_xname); 1766 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1767 esp_sched_msgout(SEND_PARITY_ERROR); 1768 else 1769 esp_sched_msgout(SEND_INIT_DET_ERR); 1770 } 1771 1772 if (sc->sc_espintr & ESPINTR_DIS) { 1773 ESP_MISC(("<DISC [intr %x, stat %x, step %d]>", 1774 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1775 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1776 ESPCMD(sc, ESPCMD_FLUSH); 1777 DELAY(1); 1778 } 1779 /* 1780 * This command must (apparently) be issued within 1781 * 250mS of a disconnect. So here you are... 1782 */ 1783 ESPCMD(sc, ESPCMD_ENSEL); 1784 switch (sc->sc_state) { 1785 case ESP_RESELECTED: 1786 goto sched; 1787 1788 case ESP_SELECTING: 1789 ecb->xs->error = XS_SELTIMEOUT; 1790 goto finish; 1791 1792 case ESP_CONNECTED: 1793 if ((sc->sc_flags & ESP_SYNCHNEGO)) { 1794 #ifdef ESP_DEBUG 1795 if (ecb) 1796 sc_print_addr(ecb->xs->sc_link); 1797 printf("sync nego not completed!\n"); 1798 #endif 1799 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1800 sc->sc_flags &= ~ESP_SYNCHNEGO; 1801 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1802 } 1803 1804 /* it may be OK to disconnect */ 1805 if ((sc->sc_flags & ESP_ABORTING) == 0) { 1806 /* 1807 * Section 5.1.1 of the SCSI 2 spec 1808 * suggests issuing a REQUEST SENSE 1809 * following an unexpected disconnect. 1810 * Some devices go into a contingent 1811 * allegiance condition when 1812 * disconnecting, and this is necessary 1813 * to clean up their state. 1814 */ 1815 printf("%s: unexpected disconnect; ", 1816 sc->sc_dev.dv_xname); 1817 if (ecb->flags & ECB_SENSE) { 1818 printf("resetting\n"); 1819 goto reset; 1820 } 1821 printf("sending REQUEST SENSE\n"); 1822 esp_sense(sc, ecb); 1823 goto out; 1824 } 1825 1826 ecb->xs->error = XS_DRIVER_STUFFUP; 1827 goto finish; 1828 1829 case ESP_DISCONNECT: 1830 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1831 sc->sc_nexus = NULL; 1832 goto sched; 1833 1834 case ESP_CMDCOMPLETE: 1835 goto finish; 1836 } 1837 } 1838 1839 switch (sc->sc_state) { 1840 1841 case ESP_SBR: 1842 printf("%s: waiting for SCSI Bus Reset to happen\n", 1843 sc->sc_dev.dv_xname); 1844 return 1; 1845 1846 case ESP_RESELECTED: 1847 /* 1848 * we must be continuing a message ? 1849 */ 1850 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1851 printf("%s: target didn't identify\n", 1852 sc->sc_dev.dv_xname); 1853 esp_init(sc, 1); 1854 return 1; 1855 } 1856 printf("<<RESELECT CONT'd>>"); 1857 #if XXXX 1858 esp_msgin(sc); 1859 if (sc->sc_state != ESP_CONNECTED) { 1860 /* IDENTIFY fail?! */ 1861 printf("%s: identify failed\n", 1862 sc->sc_dev.dv_xname); 1863 esp_init(sc, 1); 1864 return 1; 1865 } 1866 #endif 1867 break; 1868 1869 case ESP_IDLE: 1870 if (sc->sc_flags & ESP_ICCS) printf("[[esp: BUMMER]]"); 1871 case ESP_SELECTING: 1872 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1873 sc->sc_flags = 0; 1874 1875 if (sc->sc_espintr & ESPINTR_RESEL) { 1876 /* 1877 * If we're trying to select a 1878 * target ourselves, push our command 1879 * back into the ready list. 1880 */ 1881 if (sc->sc_state == ESP_SELECTING) { 1882 ESP_MISC(("backoff selector ")); 1883 sc_link = sc->sc_nexus->xs->sc_link; 1884 ti = &sc->sc_tinfo[sc_link->target]; 1885 TAILQ_INSERT_HEAD(&sc->ready_list, 1886 sc->sc_nexus, chain); 1887 ecb = sc->sc_nexus = NULL; 1888 } 1889 sc->sc_state = ESP_RESELECTED; 1890 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1891 /* 1892 * Things are seriously fucked up. 1893 * Pull the brakes, i.e. reset 1894 */ 1895 printf("%s: target didn't identify\n", 1896 sc->sc_dev.dv_xname); 1897 esp_init(sc, 1); 1898 return 1; 1899 } 1900 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 1901 printf("%s: RESELECT: %d bytes in FIFO!\n", 1902 sc->sc_dev.dv_xname, 1903 ESP_READ_REG(sc, ESP_FFLAG) & 1904 ESPFIFO_FF); 1905 esp_init(sc, 1); 1906 return 1; 1907 } 1908 sc->sc_selid = ESP_READ_REG(sc, ESP_FIFO); 1909 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1910 esp_msgin(sc); /* Handle identify message */ 1911 if (sc->sc_state != ESP_CONNECTED) { 1912 /* IDENTIFY fail?! */ 1913 printf("%s: identify failed\n", 1914 sc->sc_dev.dv_xname); 1915 esp_init(sc, 1); 1916 return 1; 1917 } 1918 continue; /* ie. next phase expected soon */ 1919 } 1920 1921 #define ESPINTR_DONE (ESPINTR_FC|ESPINTR_BS) 1922 if ((sc->sc_espintr & ESPINTR_DONE) == ESPINTR_DONE) { 1923 ecb = sc->sc_nexus; 1924 if (!ecb) 1925 panic("esp: not nexus at sc->sc_nexus"); 1926 1927 sc_link = ecb->xs->sc_link; 1928 ti = &sc->sc_tinfo[sc_link->target]; 1929 1930 switch (sc->sc_espstep) { 1931 case 0: 1932 printf("%s: select timeout/no disconnect\n", 1933 sc->sc_dev.dv_xname); 1934 ecb->xs->error = XS_SELTIMEOUT; 1935 goto finish; 1936 case 1: 1937 if ((ti->flags & T_NEGOTIATE) == 0) { 1938 printf("%s: step 1 & !NEG\n", 1939 sc->sc_dev.dv_xname); 1940 goto reset; 1941 } 1942 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1943 printf("%s: !MSGOUT\n", 1944 sc->sc_dev.dv_xname); 1945 goto reset; 1946 } 1947 /* Start negotiating */ 1948 ti->period = sc->sc_minsync; 1949 ti->offset = 15; 1950 sc->sc_flags |= ESP_SYNCHNEGO; 1951 esp_sched_msgout(SEND_SDTR); 1952 break; 1953 case 3: 1954 /* 1955 * Grr, this is supposed to mean 1956 * "target left command phase 1957 * prematurely". It seems to happen 1958 * regularly when sync mode is on. 1959 * Look at FIFO to see if command 1960 * went out. 1961 * (Timing problems?) 1962 */ 1963 if ((ESP_READ_REG(sc, ESP_FFLAG)&ESPFIFO_FF) == 0) { 1964 /* Hope for the best.. */ 1965 break; 1966 } 1967 printf("(%s:%d:%d): selection failed;" 1968 " %d left in FIFO " 1969 "[intr %x, stat %x, step %d]\n", 1970 sc->sc_dev.dv_xname, 1971 sc_link->target, 1972 sc_link->lun, 1973 ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF, 1974 sc->sc_espintr, sc->sc_espstat, 1975 sc->sc_espstep); 1976 ESPCMD(sc, ESPCMD_FLUSH); 1977 esp_sched_msgout(SEND_ABORT); 1978 return 1; 1979 case 2: 1980 /* Select stuck at Command Phase */ 1981 ESPCMD(sc, ESPCMD_FLUSH); 1982 case 4: 1983 /* So far, everything went fine */ 1984 break; 1985 } 1986 #if 0 1987 if (ecb->xs->flags & SCSI_RESET) 1988 esp_sched_msgout(SEND_DEV_RESET); 1989 else if (ti->flags & T_NEGOTIATE) 1990 esp_sched_msgout( 1991 SEND_IDENTIFY | SEND_SDTR); 1992 else 1993 esp_sched_msgout(SEND_IDENTIFY); 1994 #endif 1995 1996 ecb->flags |= ECB_NEXUS; 1997 ti->lubusy |= (1 << sc_link->lun); 1998 1999 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 2000 /* Do an implicit RESTORE POINTERS. */ 2001 sc->sc_dp = ecb->daddr; 2002 sc->sc_dleft = ecb->dleft; 2003 2004 /* On our first connection, schedule a timeout. */ 2005 if ((ecb->xs->flags & SCSI_POLL) == 0) 2006 timeout(esp_timeout, ecb, (ecb->timeout * hz) / 1000); 2007 2008 sc->sc_state = ESP_CONNECTED; 2009 break; 2010 } else { 2011 printf("%s: unexpected status after select" 2012 ": [intr %x, stat %x, step %x]\n", 2013 sc->sc_dev.dv_xname, 2014 sc->sc_espintr, sc->sc_espstat, 2015 sc->sc_espstep); 2016 ESPCMD(sc, ESPCMD_FLUSH); 2017 DELAY(1); 2018 goto reset; 2019 } 2020 if (sc->sc_state == ESP_IDLE) { 2021 printf("%s: stray interrupt\n", sc->sc_dev.dv_xname); 2022 return 0; 2023 } 2024 break; 2025 2026 case ESP_CONNECTED: 2027 if (sc->sc_flags & ESP_ICCS) { 2028 u_char msg; 2029 2030 sc->sc_flags &= ~ESP_ICCS; 2031 2032 if (!(sc->sc_espintr & ESPINTR_DONE)) { 2033 printf("%s: ICCS: " 2034 ": [intr %x, stat %x, step %x]\n", 2035 sc->sc_dev.dv_xname, 2036 sc->sc_espintr, sc->sc_espstat, 2037 sc->sc_espstep); 2038 } 2039 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 2040 int i = (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) - 2; 2041 while (i--) 2042 (void) ESP_READ_REG(sc, ESP_FIFO); 2043 } 2044 ecb->stat = ESP_READ_REG(sc, ESP_FIFO); 2045 msg = ESP_READ_REG(sc, ESP_FIFO); 2046 ESP_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 2047 if (msg == MSG_CMDCOMPLETE) { 2048 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 2049 sc->sc_state = ESP_CMDCOMPLETE; 2050 } else 2051 printf("%s: STATUS_PHASE: msg %d\n", 2052 sc->sc_dev.dv_xname, msg); 2053 ESPCMD(sc, ESPCMD_MSGOK); 2054 continue; /* ie. wait for disconnect */ 2055 } 2056 break; 2057 default: 2058 panic("%s: invalid state: %d", 2059 sc->sc_dev.dv_xname, 2060 sc->sc_state); 2061 } 2062 2063 /* 2064 * Driver is now in state ESP_CONNECTED, i.e. we 2065 * have a current command working the SCSI bus. 2066 */ 2067 if (sc->sc_state != ESP_CONNECTED || ecb == NULL) { 2068 panic("esp no nexus"); 2069 } 2070 2071 switch (sc->sc_phase) { 2072 case MESSAGE_OUT_PHASE: 2073 ESP_PHASE(("MESSAGE_OUT_PHASE ")); 2074 esp_msgout(sc); 2075 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2076 break; 2077 case MESSAGE_IN_PHASE: 2078 ESP_PHASE(("MESSAGE_IN_PHASE ")); 2079 if (sc->sc_espintr & ESPINTR_BS) { 2080 ESPCMD(sc, ESPCMD_FLUSH); 2081 sc->sc_flags |= ESP_WAITI; 2082 ESPCMD(sc, ESPCMD_TRANS); 2083 } else if (sc->sc_espintr & ESPINTR_FC) { 2084 if ((sc->sc_flags & ESP_WAITI) == 0) { 2085 printf("%s: MSGIN: unexpected FC bit: " 2086 "[intr %x, stat %x, step %x]\n", 2087 sc->sc_dev.dv_xname, 2088 sc->sc_espintr, sc->sc_espstat, 2089 sc->sc_espstep); 2090 } 2091 sc->sc_flags &= ~ESP_WAITI; 2092 esp_msgin(sc); 2093 } else { 2094 printf("%s: MSGIN: weird bits: " 2095 "[intr %x, stat %x, step %x]\n", 2096 sc->sc_dev.dv_xname, 2097 sc->sc_espintr, sc->sc_espstat, 2098 sc->sc_espstep); 2099 } 2100 sc->sc_prevphase = MESSAGE_IN_PHASE; 2101 break; 2102 case COMMAND_PHASE: { 2103 /* well, this means send the command again */ 2104 u_char *cmd = (u_char *)&ecb->cmd; 2105 int i; 2106 2107 ESP_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2108 ecb->cmd.opcode, ecb->clen)); 2109 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 2110 ESPCMD(sc, ESPCMD_FLUSH); 2111 DELAY(1); 2112 } 2113 /* Now the command into the FIFO */ 2114 for (i = 0; i < ecb->clen; i++) 2115 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 2116 ESPCMD(sc, ESPCMD_TRANS); 2117 sc->sc_prevphase = COMMAND_PHASE; 2118 } 2119 break; 2120 case DATA_OUT_PHASE: 2121 ESP_PHASE(("DATA_OUT_PHASE [%d] ", sc->sc_dleft)); 2122 ESPCMD(sc, ESPCMD_FLUSH); 2123 size = min(sc->sc_dleft, sc->sc_maxxfer); 2124 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2125 0, &size); 2126 sc->sc_prevphase = DATA_OUT_PHASE; 2127 goto setup_xfer; 2128 case DATA_IN_PHASE: 2129 ESP_PHASE(("DATA_IN_PHASE ")); 2130 if (sc->sc_rev == ESP100) 2131 ESPCMD(sc, ESPCMD_FLUSH); 2132 size = min(sc->sc_dleft, sc->sc_maxxfer); 2133 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2134 1, &size); 2135 sc->sc_prevphase = DATA_IN_PHASE; 2136 setup_xfer: 2137 /* Program the SCSI counter */ 2138 ESP_WRITE_REG(sc, ESP_TCL, size); 2139 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 2140 if (sc->sc_cfg2 & ESPCFG2_FE) { 2141 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 2142 } 2143 /* load the count in */ 2144 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 2145 2146 /* 2147 * Note that if `size' is 0, we've already transceived 2148 * all the bytes we want but we're still in DATA PHASE. 2149 * Apparently, the device needs padding. Also, a 2150 * transfer size of 0 means "maximum" to the chip 2151 * DMA logic. 2152 */ 2153 ESPCMD(sc, 2154 (size==0?ESPCMD_TRPAD:ESPCMD_TRANS)|ESPCMD_DMA); 2155 DMA_GO(sc->sc_dma); 2156 return 1; 2157 case STATUS_PHASE: 2158 ESP_PHASE(("STATUS_PHASE ")); 2159 sc->sc_flags |= ESP_ICCS; 2160 ESPCMD(sc, ESPCMD_ICCS); 2161 sc->sc_prevphase = STATUS_PHASE; 2162 break; 2163 case INVALID_PHASE: 2164 break; 2165 default: 2166 printf("%s: unexpected bus phase; resetting\n", 2167 sc->sc_dev.dv_xname); 2168 goto reset; 2169 } 2170 } 2171 panic("esp: should not get here.."); 2172 2173 reset: 2174 esp_init(sc, 1); 2175 return 1; 2176 2177 finish: 2178 untimeout(esp_timeout, ecb); 2179 esp_done(sc, ecb); 2180 goto out; 2181 2182 sched: 2183 sc->sc_state = ESP_IDLE; 2184 esp_sched(sc); 2185 goto out; 2186 2187 out: 2188 return 1; 2189 } 2190 2191 void 2192 esp_abort(sc, ecb) 2193 struct esp_softc *sc; 2194 struct esp_ecb *ecb; 2195 { 2196 2197 /* 2 secs for the abort */ 2198 ecb->timeout = ESP_ABORT_TIMEOUT; 2199 ecb->flags |= ECB_ABORT; 2200 2201 if (ecb == sc->sc_nexus) { 2202 /* 2203 * If we're still selecting, the message will be scheduled 2204 * after selection is complete. 2205 */ 2206 if (sc->sc_state == ESP_CONNECTED) 2207 esp_sched_msgout(SEND_ABORT); 2208 } else { 2209 esp_dequeue(sc, ecb); 2210 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2211 if (sc->sc_state == ESP_IDLE) 2212 esp_sched(sc); 2213 } 2214 } 2215 2216 void 2217 esp_timeout(arg) 2218 void *arg; 2219 { 2220 struct esp_ecb *ecb = arg; 2221 struct scsi_xfer *xs = ecb->xs; 2222 struct scsi_link *sc_link = xs->sc_link; 2223 struct esp_softc *sc = sc_link->adapter_softc; 2224 int s; 2225 2226 sc_print_addr(sc_link); 2227 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2228 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) %s>", 2229 sc->sc_dev.dv_xname, 2230 ecb, ecb->flags, ecb->dleft, ecb->stat, 2231 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2232 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2233 DMA_ISACTIVE(sc->sc_dma) ? "DMA active" : ""); 2234 #if ESP_DEBUG > 0 2235 printf("TRACE: %s.", ecb->trace); 2236 #endif 2237 2238 s = splbio(); 2239 2240 if (ecb->flags & ECB_ABORT) { 2241 /* abort timed out */ 2242 printf(" AGAIN\n"); 2243 esp_init(sc, 1); 2244 } else { 2245 /* abort the operation that has timed out */ 2246 printf("\n"); 2247 xs->error = XS_TIMEOUT; 2248 esp_abort(sc, ecb); 2249 } 2250 2251 splx(s); 2252 } 2253
Indexes created Sat Oct 25 16:10:12 GMT 2025