esp.c revision 1.12
1 /* $NetBSD: esp.c,v 1.12 1997/11/05 03:33:35 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Jason R. Thorpe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project 18 * by Jason R. Thorpe. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1994 Peter Galbavy 36 * Copyright (c) 1995 Paul Kranenburg 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Peter Galbavy 50 * 4. The name of the author may not be used to endorse or promote products 51 * derived from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 55 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 56 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 61 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 62 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 63 * POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * Based on aic6360 by Jarle Greipsland 68 * 69 * Acknowledgements: Many of the algorithms used in this driver are 70 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 71 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 72 */ 73 74 /* 75 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 76 * (basically consisting of the match, a bit of the attach, and the 77 * "DMA" glue functions). 78 */ 79 80 #include <sys/types.h> 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/errno.h> 85 #include <sys/ioctl.h> 86 #include <sys/device.h> 87 #include <sys/buf.h> 88 #include <sys/proc.h> 89 #include <sys/user.h> 90 #include <sys/queue.h> 91 92 #include <dev/scsipi/scsi_all.h> 93 #include <dev/scsipi/scsipi_all.h> 94 #include <dev/scsipi/scsiconf.h> 95 #include <dev/scsipi/scsi_message.h> 96 97 #include <machine/cpu.h> 98 #include <machine/bus.h> 99 #include <machine/param.h> 100 101 #include <dev/ic/ncr53c9xreg.h> 102 #include <dev/ic/ncr53c9xvar.h> 103 104 #include <machine/viareg.h> 105 106 #include <mac68k/dev/espvar.h> 107 #include <mac68k/dev/obiovar.h> 108 109 void espattach __P((struct device *, struct device *, void *)); 110 int espmatch __P((struct device *, struct cfdata *, void *)); 111 112 /* Linkup to the rest of the kernel */ 113 struct cfattach esp_ca = { 114 sizeof(struct esp_softc), espmatch, espattach 115 }; 116 117 struct cfdriver esp_cd = { 118 NULL, "esp", DV_DULL 119 }; 120 121 struct scsipi_adapter esp_switch = { 122 ncr53c9x_scsi_cmd, 123 minphys, /* no max at this level; handled by DMA code */ 124 NULL, 125 NULL, 126 }; 127 128 struct scsipi_device esp_dev = { 129 NULL, /* Use default error handler */ 130 NULL, /* have a queue, served by this */ 131 NULL, /* have no async handler */ 132 NULL, /* Use default 'done' routine */ 133 }; 134 135 /* 136 * Functions and the switch for the MI code. 137 */ 138 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 139 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 140 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 141 void esp_dma_reset __P((struct ncr53c9x_softc *)); 142 int esp_dma_intr __P((struct ncr53c9x_softc *)); 143 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 144 size_t *, int, size_t *)); 145 void esp_dma_go __P((struct ncr53c9x_softc *)); 146 void esp_dma_stop __P((struct ncr53c9x_softc *)); 147 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 148 void esp_quick_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 149 int esp_quick_dma_intr __P((struct ncr53c9x_softc *)); 150 int esp_quick_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 151 size_t *, int, size_t *)); 152 void esp_quick_dma_go __P((struct ncr53c9x_softc *)); 153 154 static __inline__ int esp_dafb_have_dreq __P((struct esp_softc *esc)); 155 static __inline__ int esp_iosb_have_dreq __P((struct esp_softc *esc)); 156 int (*esp_have_dreq) __P((struct esp_softc *esc)); 157 158 struct ncr53c9x_glue esp_glue = { 159 esp_read_reg, 160 esp_write_reg, 161 esp_dma_isintr, 162 esp_dma_reset, 163 esp_dma_intr, 164 esp_dma_setup, 165 esp_dma_go, 166 esp_dma_stop, 167 esp_dma_isactive, 168 NULL, /* gl_clear_latched_intr */ 169 }; 170 171 int 172 espmatch(parent, cf, aux) 173 struct device *parent; 174 struct cfdata *cf; 175 void *aux; 176 { 177 int found = 0; 178 179 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) { 180 found = 1; 181 } 182 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) { 183 found = 1; 184 } 185 186 return found; 187 } 188 189 /* 190 * Attach this instance, and then all the sub-devices 191 */ 192 void 193 espattach(parent, self, aux) 194 struct device *parent, *self; 195 void *aux; 196 { 197 struct obio_attach_args *oa = (struct obio_attach_args *)aux; 198 extern vm_offset_t SCSIBase; 199 struct esp_softc *esc = (void *)self; 200 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 201 int quick = 0; 202 unsigned long reg_offset; 203 204 reg_offset = SCSIBase - IOBase; 205 esc->sc_tag = oa->oa_tag; 206 /* 207 * For Wombat, Primus and Optimus motherboards, DREQ is 208 * visible on bit 0 of the IOSB's emulated VIA2 vIFR (and 209 * the scsi registers are offset 0x1000 bytes from IOBase). 210 * 211 * For the Q700/900/950 it's at f9800024 for bus 0 and 212 * f9800028 for bus 1 (900/950). For these machines, that is also 213 * a (12-bit) configuration register for DAFB's control of the 214 * pseudo-DMA timing. The default value is 0x1d1. 215 */ 216 esp_have_dreq = esp_dafb_have_dreq; 217 if (sc->sc_dev.dv_unit == 0) { 218 if (reg_offset == 0x10000) { 219 quick = 1; 220 esp_have_dreq = esp_iosb_have_dreq; 221 } else if (reg_offset == 0x18000) { 222 quick = 0; 223 } else { 224 if (bus_space_map(esc->sc_tag, 0xf9800024, 225 4, 0, &esc->sc_bsh)) { 226 printf("failed to map 4 at 0xf9800024.\n"); 227 } else { 228 quick = 1; 229 bus_space_write_4(esc->sc_tag, 230 esc->sc_bsh, 0, 0x1d1); 231 } 232 } 233 } else { 234 if (bus_space_map(esc->sc_tag, 0xf9800028, 235 4, 0, &esc->sc_bsh)) { 236 printf("failed to map 4 at 0xf9800028.\n"); 237 } else { 238 quick = 1; 239 bus_space_write_4(esc->sc_tag, esc->sc_bsh, 0, 0x1d1); 240 } 241 } 242 if (quick) { 243 esp_glue.gl_write_reg = esp_quick_write_reg; 244 esp_glue.gl_dma_intr = esp_quick_dma_intr; 245 esp_glue.gl_dma_setup = esp_quick_dma_setup; 246 esp_glue.gl_dma_go = esp_quick_dma_go; 247 } 248 249 /* 250 * Set up the glue for MI code early; we use some of it here. 251 */ 252 sc->sc_glue = &esp_glue; 253 254 /* 255 * Save the regs 256 */ 257 if (sc->sc_dev.dv_unit == 0) { 258 259 esc->sc_reg = (volatile u_char *) SCSIBase; 260 via2_register_irq(VIA2_SCSIIRQ, 261 (void (*)(void *))ncr53c9x_intr, esc); 262 esc->irq_mask = V2IF_SCSIIRQ; 263 if (reg_offset == 0x10000) { 264 sc->sc_freq = 16500000; 265 } else { 266 sc->sc_freq = 25000000; 267 } 268 269 if (esp_glue.gl_dma_go == esp_quick_dma_go) { 270 printf(" (quick)"); 271 } 272 } else { 273 esc->sc_reg = (volatile u_char *) SCSIBase + 0x402; 274 via2_register_irq(VIA2_SCSIDRQ, 275 (void (*)(void *))ncr53c9x_intr, esc); 276 esc->irq_mask = V2IF_SCSIDRQ; /* V2IF_T1? */ 277 sc->sc_freq = 25000000; 278 279 if (esp_glue.gl_dma_go == esp_quick_dma_go) { 280 printf(" (quick)"); 281 } 282 } 283 284 printf(": address %p", esc->sc_reg); 285 286 sc->sc_id = 7; 287 288 /* gimme Mhz */ 289 sc->sc_freq /= 1000000; 290 291 /* 292 * It is necessary to try to load the 2nd config register here, 293 * to find out what rev the esp chip is, else the esp_reset 294 * will not set up the defaults correctly. 295 */ 296 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 297 sc->sc_cfg2 = NCRCFG2_SCSI2; 298 sc->sc_cfg3 = 0; 299 sc->sc_rev = NCR_VARIANT_NCR53C96; 300 301 /* 302 * This is the value used to start sync negotiations 303 * Note that the NCR register "SYNCTP" is programmed 304 * in "clocks per byte", and has a minimum value of 4. 305 * The SCSI period used in negotiation is one-fourth 306 * of the time (in nanoseconds) needed to transfer one byte. 307 * Since the chip's clock is given in MHz, we have the following 308 * formula: 4 * period = (1000 / freq) * 4 309 */ 310 sc->sc_minsync = 1000 / sc->sc_freq; 311 312 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */ 313 /* Really no limit, but since we want to fit into the TCR... */ 314 sc->sc_maxxfer = 8 * 1024; /*64 * 1024; XXX */ 315 316 /* 317 * Now try to attach all the sub-devices 318 */ 319 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 320 321 /* 322 * Configure interrupts. 323 */ 324 via2_reg(vPCR) = 0x22; 325 via2_reg(vIFR) = esc->irq_mask; 326 via2_reg(vIER) = 0x80 | esc->irq_mask; 327 } 328 329 /* 330 * Glue functions. 331 */ 332 333 u_char 334 esp_read_reg(sc, reg) 335 struct ncr53c9x_softc *sc; 336 int reg; 337 { 338 struct esp_softc *esc = (struct esp_softc *)sc; 339 340 return esc->sc_reg[reg * 16]; 341 } 342 343 void 344 esp_write_reg(sc, reg, val) 345 struct ncr53c9x_softc *sc; 346 int reg; 347 u_char val; 348 { 349 struct esp_softc *esc = (struct esp_softc *)sc; 350 u_char v = val; 351 352 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 353 v = NCRCMD_TRANS; 354 } 355 esc->sc_reg[reg * 16] = v; 356 } 357 358 void 359 esp_dma_stop(sc) 360 struct ncr53c9x_softc *sc; 361 { 362 } 363 364 int 365 esp_dma_isactive(sc) 366 struct ncr53c9x_softc *sc; 367 { 368 struct esp_softc *esc = (struct esp_softc *)sc; 369 370 return esc->sc_active; 371 } 372 373 int 374 esp_dma_isintr(sc) 375 struct ncr53c9x_softc *sc; 376 { 377 struct esp_softc *esc = (struct esp_softc *)sc; 378 379 return esc->sc_reg[NCR_STAT * 16] & 0x80; 380 } 381 382 void 383 esp_dma_reset(sc) 384 struct ncr53c9x_softc *sc; 385 { 386 struct esp_softc *esc = (struct esp_softc *)sc; 387 388 esc->sc_active = 0; 389 esc->sc_tc = 0; 390 } 391 392 int 393 esp_dma_intr(sc) 394 struct ncr53c9x_softc *sc; 395 { 396 register struct esp_softc *esc = (struct esp_softc *)sc; 397 register u_char *p; 398 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 399 register u_int espphase, espstat, espintr; 400 register int cnt; 401 402 if (esc->sc_active == 0) { 403 printf("dma_intr--inactive DMA\n"); 404 return -1; 405 } 406 407 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 408 esc->sc_active = 0; 409 return 0; 410 } 411 412 cnt = *esc->sc_dmalen; 413 if (*esc->sc_dmalen == 0) { 414 printf("data interrupt, but no count left."); 415 } 416 417 p = *esc->sc_dmaaddr; 418 espphase = sc->sc_phase; 419 espstat = (u_int) sc->sc_espstat; 420 espintr = (u_int) sc->sc_espintr; 421 cmdreg = esc->sc_reg + NCR_CMD * 16; 422 fiforeg = esc->sc_reg + NCR_FIFO * 16; 423 statreg = esc->sc_reg + NCR_STAT * 16; 424 intrreg = esc->sc_reg + NCR_INTR * 16; 425 do { 426 if (esc->sc_datain) { 427 *p++ = *fiforeg; 428 cnt--; 429 if (espphase == DATA_IN_PHASE) { 430 *cmdreg = NCRCMD_TRANS; 431 } else { 432 esc->sc_active = 0; 433 } 434 } else { 435 if ( (espphase == DATA_OUT_PHASE) 436 || (espphase == MESSAGE_OUT_PHASE)) { 437 *fiforeg = *p++; 438 cnt--; 439 *cmdreg = NCRCMD_TRANS; 440 } else { 441 esc->sc_active = 0; 442 } 443 } 444 445 if (esc->sc_active) { 446 while (!(*statreg & 0x80)); 447 espstat = *statreg; 448 espintr = *intrreg; 449 espphase = (espintr & NCRINTR_DIS) 450 ? /* Disconnected */ BUSFREE_PHASE 451 : espstat & PHASE_MASK; 452 } 453 } while (esc->sc_active && (espintr & NCRINTR_BS)); 454 sc->sc_phase = espphase; 455 sc->sc_espstat = (u_char) espstat; 456 sc->sc_espintr = (u_char) espintr; 457 *esc->sc_dmaaddr = p; 458 *esc->sc_dmalen = cnt; 459 460 if (*esc->sc_dmalen == 0) { 461 esc->sc_tc = NCRSTAT_TC; 462 } 463 sc->sc_espstat |= esc->sc_tc; 464 return 0; 465 } 466 467 int 468 esp_dma_setup(sc, addr, len, datain, dmasize) 469 struct ncr53c9x_softc *sc; 470 caddr_t *addr; 471 size_t *len; 472 int datain; 473 size_t *dmasize; 474 { 475 struct esp_softc *esc = (struct esp_softc *)sc; 476 477 esc->sc_dmaaddr = addr; 478 esc->sc_dmalen = len; 479 esc->sc_datain = datain; 480 esc->sc_dmasize = *dmasize; 481 esc->sc_tc = 0; 482 483 return 0; 484 } 485 486 void 487 esp_dma_go(sc) 488 struct ncr53c9x_softc *sc; 489 { 490 struct esp_softc *esc = (struct esp_softc *)sc; 491 492 if (esc->sc_datain == 0) { 493 esc->sc_reg[NCR_FIFO * 16] = **esc->sc_dmaaddr; 494 (*esc->sc_dmalen)--; 495 (*esc->sc_dmaaddr)++; 496 } 497 esc->sc_active = 1; 498 } 499 500 void 501 esp_quick_write_reg(sc, reg, val) 502 struct ncr53c9x_softc *sc; 503 int reg; 504 u_char val; 505 { 506 struct esp_softc *esc = (struct esp_softc *)sc; 507 u_char v = val; 508 509 esc->sc_reg[reg * 16] = v; 510 } 511 512 int 513 esp_quick_dma_intr(sc) 514 struct ncr53c9x_softc *sc; 515 { 516 struct esp_softc *esc = (struct esp_softc *)sc; 517 int trans=0, resid=0; 518 519 if (esc->sc_active == 0) 520 panic("dma_intr--inactive DMA\n"); 521 522 esc->sc_active = 0; 523 524 if (esc->sc_dmasize == 0) { 525 int res; 526 527 res = 65536; 528 res -= NCR_READ_REG(sc, NCR_TCL); 529 res -= NCR_READ_REG(sc, NCR_TCM) << 8; 530 printf("dmaintr: discarded %d b (last transfer was %d b).\n", 531 res, esc->sc_prevdmasize); 532 return 0; 533 } 534 535 if (esc->sc_datain && 536 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 537 printf("dmaintr: empty FIFO of %d\n", resid); 538 DELAY(1); 539 } 540 541 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 542 resid += NCR_READ_REG(sc, NCR_TCL); 543 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 544 545 if (resid == 0) 546 resid = 65536; 547 } 548 549 trans = esc->sc_dmasize - resid; 550 if (trans < 0) { 551 printf("dmaintr: trans < 0????"); 552 trans = esc->sc_dmasize; 553 } 554 555 NCR_DMA(("dmaintr: trans %d, resid %d.\n", trans, resid)); 556 *esc->sc_dmaaddr += trans; 557 *esc->sc_dmalen -= trans; 558 559 return 0; 560 } 561 562 int 563 esp_quick_dma_setup(sc, addr, len, datain, dmasize) 564 struct ncr53c9x_softc *sc; 565 caddr_t *addr; 566 size_t *len; 567 int datain; 568 size_t *dmasize; 569 { 570 struct esp_softc *esc = (struct esp_softc *)sc; 571 572 esc->sc_dmaaddr = addr; 573 esc->sc_dmalen = len; 574 575 if (((int) *addr) & 1) 576 panic("Implement odd-base transfers, now."); 577 578 esc->sc_pdmaddr = (u_int16_t *) *addr; 579 esc->sc_pdmalen = *len; 580 581 if (*len & 1) 582 panic("Implement odd-length transfers, now."); 583 584 esc->sc_datain = datain; 585 esc->sc_prevdmasize = esc->sc_dmasize; 586 esc->sc_dmasize = *dmasize; 587 588 return 0; 589 } 590 591 static __inline__ int 592 esp_dafb_have_dreq(esc) 593 struct esp_softc *esc; 594 { 595 u_int32_t r; 596 597 r = bus_space_read_4(esc->sc_tag, esc->sc_bsh, 0); 598 return (r & 0x200); 599 } 600 601 static __inline__ int 602 esp_iosb_have_dreq(esc) 603 struct esp_softc *esc; 604 { 605 return (via2_reg(vIFR) & V2IF_SCSIDRQ); 606 } 607 608 static int espspl=-1; 609 #define __splx(s) __asm __volatile ("movew %0,sr" : : "di" (s)); 610 #define __spl2() __splx(PSL_S|PSL_IPL2) 611 #define __spl4() __splx(PSL_S|PSL_IPL4) 612 613 void 614 esp_quick_dma_go(sc) 615 struct ncr53c9x_softc *sc; 616 { 617 struct esp_softc *esc = (struct esp_softc *)sc; 618 extern int *nofault; 619 label_t faultbuf; 620 u_int16_t volatile *pdma; 621 u_char volatile *statreg; 622 623 esc->sc_active = 1; 624 625 espspl = spl2(); 626 627 restart_dmago: 628 nofault = (int *) &faultbuf; 629 if (setjmp((label_t *) nofault)) { 630 int i=0; 631 632 nofault = (int *) 0; 633 statreg = esc->sc_reg + NCR_STAT * 16; 634 for (;;) { 635 if (*statreg & 0x80) { 636 goto gotintr; 637 } 638 639 if (esp_have_dreq(esc)) { 640 break; 641 } 642 643 DELAY(1); 644 if (i++ > 10000) 645 panic("esp_dma_go: Argh!"); 646 } 647 goto restart_dmago; 648 } 649 650 statreg = esc->sc_reg + NCR_STAT * 16; 651 pdma = (u_int16_t *) (esc->sc_reg + 0x100); 652 653 #define WAIT while (!esp_have_dreq(esc)) if (*statreg & 0x80) goto gotintr 654 655 if (esc->sc_datain == 0) { 656 while (esc->sc_pdmalen) { 657 WAIT; 658 __spl4(); *pdma = *(esc->sc_pdmaddr)++; __spl2() 659 esc->sc_pdmalen -= 2; 660 } 661 } else { 662 while (esc->sc_pdmalen) { 663 WAIT; 664 __spl4(); *(esc->sc_pdmaddr)++ = *pdma; __spl2() 665 esc->sc_pdmalen -= 2; 666 } 667 } 668 #undef WAIT 669 670 nofault = (int *) 0; 671 672 if ((*statreg & 0x80) == 0) { 673 if (espspl != -1) splx(espspl); espspl = -1; 674 return; 675 } 676 677 gotintr: 678 ncr53c9x_intr(sc); 679 if (espspl != -1) splx(espspl); espspl = -1; 680 } 681
Indexes created Mon Sep 29 18:09:42 GMT 2025