esp.c revision 1.16 1 /* $NetBSD: esp.c,v 1.16 1998/05/09 22:47:53 briggs Exp $ */
2
3 /*
4 * Copyright (c) 1997 Jason R. Thorpe.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed for the NetBSD Project
18 * by Jason R. Thorpe.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Copyright (c) 1994 Peter Galbavy
36 * Copyright (c) 1995 Paul Kranenburg
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in the
46 * documentation and/or other materials provided with the distribution.
47 * 3. All advertising materials mentioning features or use of this software
48 * must display the following acknowledgement:
49 * This product includes software developed by Peter Galbavy
50 * 4. The name of the author may not be used to endorse or promote products
51 * derived from this software without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
55 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
56 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
61 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
62 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
63 * POSSIBILITY OF SUCH DAMAGE.
64 */
65
66 /*
67 * Based on aic6360 by Jarle Greipsland
68 *
69 * Acknowledgements: Many of the algorithms used in this driver are
70 * inspired by the work of Julian Elischer (julian (at) tfs.com) and
71 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million!
72 */
73
74 /*
75 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com>
76 * (basically consisting of the match, a bit of the attach, and the
77 * "DMA" glue functions).
78 */
79
80 #include <sys/types.h>
81 #include <sys/param.h>
82 #include <sys/systm.h>
83 #include <sys/kernel.h>
84 #include <sys/errno.h>
85 #include <sys/ioctl.h>
86 #include <sys/device.h>
87 #include <sys/buf.h>
88 #include <sys/proc.h>
89 #include <sys/user.h>
90 #include <sys/queue.h>
91
92 #include <dev/scsipi/scsi_all.h>
93 #include <dev/scsipi/scsipi_all.h>
94 #include <dev/scsipi/scsiconf.h>
95 #include <dev/scsipi/scsi_message.h>
96
97 #include <machine/cpu.h>
98 #include <machine/bus.h>
99 #include <machine/param.h>
100
101 #include <dev/ic/ncr53c9xreg.h>
102 #include <dev/ic/ncr53c9xvar.h>
103
104 #include <machine/viareg.h>
105
106 #include <mac68k/obio/espvar.h>
107 #include <mac68k/obio/obiovar.h>
108
109 void espattach __P((struct device *, struct device *, void *));
110 int espmatch __P((struct device *, struct cfdata *, void *));
111
112 /* Linkup to the rest of the kernel */
113 struct cfattach esp_ca = {
114 sizeof(struct esp_softc), espmatch, espattach
115 };
116
117 struct scsipi_adapter esp_switch = {
118 ncr53c9x_scsi_cmd,
119 minphys, /* no max at this level; handled by DMA code */
120 NULL,
121 NULL,
122 };
123
124 struct scsipi_device esp_dev = {
125 NULL, /* Use default error handler */
126 NULL, /* have a queue, served by this */
127 NULL, /* have no async handler */
128 NULL, /* Use default 'done' routine */
129 };
130
131 /*
132 * Functions and the switch for the MI code.
133 */
134 u_char esp_read_reg __P((struct ncr53c9x_softc *, int));
135 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
136 int esp_dma_isintr __P((struct ncr53c9x_softc *));
137 void esp_dma_reset __P((struct ncr53c9x_softc *));
138 int esp_dma_intr __P((struct ncr53c9x_softc *));
139 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
140 size_t *, int, size_t *));
141 void esp_dma_go __P((struct ncr53c9x_softc *));
142 void esp_dma_stop __P((struct ncr53c9x_softc *));
143 int esp_dma_isactive __P((struct ncr53c9x_softc *));
144 void esp_quick_write_reg __P((struct ncr53c9x_softc *, int, u_char));
145 int esp_quick_dma_intr __P((struct ncr53c9x_softc *));
146 int esp_quick_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
147 size_t *, int, size_t *));
148 void esp_quick_dma_go __P((struct ncr53c9x_softc *));
149
150 int esp_dualbus_intr __P((register struct ncr53c9x_softc *sc));
151 static struct esp_softc *esp0 = NULL, *esp1 = NULL;
152
153 static __inline__ int esp_dafb_have_dreq __P((struct esp_softc *esc));
154 static __inline__ int esp_iosb_have_dreq __P((struct esp_softc *esc));
155 int (*esp_have_dreq) __P((struct esp_softc *esc));
156
157 struct ncr53c9x_glue esp_glue = {
158 esp_read_reg,
159 esp_write_reg,
160 esp_dma_isintr,
161 esp_dma_reset,
162 esp_dma_intr,
163 esp_dma_setup,
164 esp_dma_go,
165 esp_dma_stop,
166 esp_dma_isactive,
167 NULL, /* gl_clear_latched_intr */
168 };
169
170 int
171 espmatch(parent, cf, aux)
172 struct device *parent;
173 struct cfdata *cf;
174 void *aux;
175 {
176 int found = 0;
177
178 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) {
179 found = 1;
180 }
181 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) {
182 found = 1;
183 }
184
185 return found;
186 }
187
188 /*
189 * Attach this instance, and then all the sub-devices
190 */
191 void
192 espattach(parent, self, aux)
193 struct device *parent, *self;
194 void *aux;
195 {
196 struct obio_attach_args *oa = (struct obio_attach_args *)aux;
197 extern vm_offset_t SCSIBase;
198 struct esp_softc *esc = (void *)self;
199 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
200 int quick = 0;
201 unsigned long reg_offset;
202
203 reg_offset = SCSIBase - IOBase;
204 esc->sc_tag = oa->oa_tag;
205 /*
206 * For Wombat, Primus and Optimus motherboards, DREQ is
207 * visible on bit 0 of the IOSB's emulated VIA2 vIFR (and
208 * the scsi registers are offset 0x1000 bytes from IOBase).
209 *
210 * For the Q700/900/950 it's at f9800024 for bus 0 and
211 * f9800028 for bus 1 (900/950). For these machines, that is also
212 * a (12-bit) configuration register for DAFB's control of the
213 * pseudo-DMA timing. The default value is 0x1d1.
214 */
215 esp_have_dreq = esp_dafb_have_dreq;
216 if (sc->sc_dev.dv_unit == 0) {
217 if (reg_offset == 0x10000) {
218 quick = 1;
219 esp_have_dreq = esp_iosb_have_dreq;
220 } else if (reg_offset == 0x18000) {
221 quick = 0;
222 } else {
223 if (bus_space_map(esc->sc_tag, 0xf9800024,
224 4, 0, &esc->sc_bsh)) {
225 printf("failed to map 4 at 0xf9800024.\n");
226 } else {
227 quick = 1;
228 bus_space_write_4(esc->sc_tag,
229 esc->sc_bsh, 0, 0x1d1);
230 }
231 }
232 } else {
233 if (bus_space_map(esc->sc_tag, 0xf9800028,
234 4, 0, &esc->sc_bsh)) {
235 printf("failed to map 4 at 0xf9800028.\n");
236 } else {
237 quick = 1;
238 bus_space_write_4(esc->sc_tag, esc->sc_bsh, 0, 0x1d1);
239 }
240 }
241 if (quick) {
242 esp_glue.gl_write_reg = esp_quick_write_reg;
243 esp_glue.gl_dma_intr = esp_quick_dma_intr;
244 esp_glue.gl_dma_setup = esp_quick_dma_setup;
245 esp_glue.gl_dma_go = esp_quick_dma_go;
246 }
247
248 /*
249 * Set up the glue for MI code early; we use some of it here.
250 */
251 sc->sc_glue = &esp_glue;
252
253 /*
254 * Save the regs
255 */
256 if (sc->sc_dev.dv_unit == 0) {
257 esp0 = esc;
258
259 esc->sc_reg = (volatile u_char *) SCSIBase;
260 via2_register_irq(VIA2_SCSIIRQ,
261 (void (*)(void *))ncr53c9x_intr, esc);
262 esc->irq_mask = V2IF_SCSIIRQ;
263 if (reg_offset == 0x10000) {
264 sc->sc_freq = 16500000;
265 } else {
266 sc->sc_freq = 25000000;
267 }
268
269 if (esp_glue.gl_dma_go == esp_quick_dma_go) {
270 printf(" (quick)");
271 }
272 } else {
273 esp1 = esc;
274
275 esc->sc_reg = (volatile u_char *) SCSIBase + 0x402;
276 via2_register_irq(VIA2_SCSIIRQ,
277 (void (*)(void *))esp_dualbus_intr, NULL);
278 esc->irq_mask = 0;
279 sc->sc_freq = 25000000;
280
281 if (esp_glue.gl_dma_go == esp_quick_dma_go) {
282 printf(" (quick)");
283 }
284 }
285
286 printf(": address %p", esc->sc_reg);
287
288 sc->sc_id = 7;
289
290 /* gimme Mhz */
291 sc->sc_freq /= 1000000;
292
293 /*
294 * It is necessary to try to load the 2nd config register here,
295 * to find out what rev the esp chip is, else the esp_reset
296 * will not set up the defaults correctly.
297 */
298 sc->sc_cfg1 = sc->sc_id; /* | NCRCFG1_PARENB; */
299 sc->sc_cfg2 = NCRCFG2_SCSI2;
300 sc->sc_cfg3 = 0;
301 sc->sc_rev = NCR_VARIANT_NCR53C96;
302
303 /*
304 * This is the value used to start sync negotiations
305 * Note that the NCR register "SYNCTP" is programmed
306 * in "clocks per byte", and has a minimum value of 4.
307 * The SCSI period used in negotiation is one-fourth
308 * of the time (in nanoseconds) needed to transfer one byte.
309 * Since the chip's clock is given in MHz, we have the following
310 * formula: 4 * period = (1000 / freq) * 4
311 */
312 sc->sc_minsync = 1000 / sc->sc_freq;
313
314 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */
315 /* Really no limit, but since we want to fit into the TCR... */
316 sc->sc_maxxfer = 8 * 1024; /*64 * 1024; XXX */
317
318 /*
319 * Now try to attach all the sub-devices
320 */
321 ncr53c9x_attach(sc, &esp_switch, &esp_dev);
322
323 /*
324 * Configure interrupts.
325 */
326 if (esc->irq_mask) {
327 via2_reg(vPCR) = 0x22;
328 via2_reg(vIFR) = esc->irq_mask;
329 via2_reg(vIER) = 0x80 | esc->irq_mask;
330 }
331 }
332
333 /*
334 * Glue functions.
335 */
336
337 u_char
338 esp_read_reg(sc, reg)
339 struct ncr53c9x_softc *sc;
340 int reg;
341 {
342 struct esp_softc *esc = (struct esp_softc *)sc;
343
344 return esc->sc_reg[reg * 16];
345 }
346
347 void
348 esp_write_reg(sc, reg, val)
349 struct ncr53c9x_softc *sc;
350 int reg;
351 u_char val;
352 {
353 struct esp_softc *esc = (struct esp_softc *)sc;
354 u_char v = val;
355
356 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) {
357 v = NCRCMD_TRANS;
358 }
359 esc->sc_reg[reg * 16] = v;
360 }
361
362 void
363 esp_dma_stop(sc)
364 struct ncr53c9x_softc *sc;
365 {
366 }
367
368 int
369 esp_dma_isactive(sc)
370 struct ncr53c9x_softc *sc;
371 {
372 struct esp_softc *esc = (struct esp_softc *)sc;
373
374 return esc->sc_active;
375 }
376
377 int
378 esp_dma_isintr(sc)
379 struct ncr53c9x_softc *sc;
380 {
381 struct esp_softc *esc = (struct esp_softc *)sc;
382
383 return esc->sc_reg[NCR_STAT * 16] & 0x80;
384 }
385
386 void
387 esp_dma_reset(sc)
388 struct ncr53c9x_softc *sc;
389 {
390 struct esp_softc *esc = (struct esp_softc *)sc;
391
392 esc->sc_active = 0;
393 esc->sc_tc = 0;
394 }
395
396 int
397 esp_dma_intr(sc)
398 struct ncr53c9x_softc *sc;
399 {
400 register struct esp_softc *esc = (struct esp_softc *)sc;
401 register u_char *p;
402 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg;
403 register u_int espphase, espstat, espintr;
404 register int cnt;
405
406 if (esc->sc_active == 0) {
407 printf("dma_intr--inactive DMA\n");
408 return -1;
409 }
410
411 if ((sc->sc_espintr & NCRINTR_BS) == 0) {
412 esc->sc_active = 0;
413 return 0;
414 }
415
416 cnt = *esc->sc_dmalen;
417 if (*esc->sc_dmalen == 0) {
418 printf("data interrupt, but no count left.");
419 }
420
421 p = *esc->sc_dmaaddr;
422 espphase = sc->sc_phase;
423 espstat = (u_int) sc->sc_espstat;
424 espintr = (u_int) sc->sc_espintr;
425 cmdreg = esc->sc_reg + NCR_CMD * 16;
426 fiforeg = esc->sc_reg + NCR_FIFO * 16;
427 statreg = esc->sc_reg + NCR_STAT * 16;
428 intrreg = esc->sc_reg + NCR_INTR * 16;
429 do {
430 if (esc->sc_datain) {
431 *p++ = *fiforeg;
432 cnt--;
433 if (espphase == DATA_IN_PHASE) {
434 *cmdreg = NCRCMD_TRANS;
435 } else {
436 esc->sc_active = 0;
437 }
438 } else {
439 if ( (espphase == DATA_OUT_PHASE)
440 || (espphase == MESSAGE_OUT_PHASE)) {
441 *fiforeg = *p++;
442 cnt--;
443 *cmdreg = NCRCMD_TRANS;
444 } else {
445 esc->sc_active = 0;
446 }
447 }
448
449 if (esc->sc_active) {
450 while (!(*statreg & 0x80));
451 espstat = *statreg;
452 espintr = *intrreg;
453 espphase = (espintr & NCRINTR_DIS)
454 ? /* Disconnected */ BUSFREE_PHASE
455 : espstat & PHASE_MASK;
456 }
457 } while (esc->sc_active && (espintr & NCRINTR_BS));
458 sc->sc_phase = espphase;
459 sc->sc_espstat = (u_char) espstat;
460 sc->sc_espintr = (u_char) espintr;
461 *esc->sc_dmaaddr = p;
462 *esc->sc_dmalen = cnt;
463
464 if (*esc->sc_dmalen == 0) {
465 esc->sc_tc = NCRSTAT_TC;
466 }
467 sc->sc_espstat |= esc->sc_tc;
468 return 0;
469 }
470
471 int
472 esp_dma_setup(sc, addr, len, datain, dmasize)
473 struct ncr53c9x_softc *sc;
474 caddr_t *addr;
475 size_t *len;
476 int datain;
477 size_t *dmasize;
478 {
479 struct esp_softc *esc = (struct esp_softc *)sc;
480
481 esc->sc_dmaaddr = addr;
482 esc->sc_dmalen = len;
483 esc->sc_datain = datain;
484 esc->sc_dmasize = *dmasize;
485 esc->sc_tc = 0;
486
487 return 0;
488 }
489
490 void
491 esp_dma_go(sc)
492 struct ncr53c9x_softc *sc;
493 {
494 struct esp_softc *esc = (struct esp_softc *)sc;
495
496 if (esc->sc_datain == 0) {
497 esc->sc_reg[NCR_FIFO * 16] = **esc->sc_dmaaddr;
498 (*esc->sc_dmalen)--;
499 (*esc->sc_dmaaddr)++;
500 }
501 esc->sc_active = 1;
502 }
503
504 void
505 esp_quick_write_reg(sc, reg, val)
506 struct ncr53c9x_softc *sc;
507 int reg;
508 u_char val;
509 {
510 struct esp_softc *esc = (struct esp_softc *)sc;
511 u_char v = val;
512
513 esc->sc_reg[reg * 16] = v;
514 }
515
516 int
517 esp_quick_dma_intr(sc)
518 struct ncr53c9x_softc *sc;
519 {
520 struct esp_softc *esc = (struct esp_softc *)sc;
521 int trans=0, resid=0;
522
523 if (esc->sc_active == 0)
524 panic("dma_intr--inactive DMA\n");
525
526 esc->sc_active = 0;
527
528 if (esc->sc_dmasize == 0) {
529 int res;
530
531 res = 65536;
532 res -= NCR_READ_REG(sc, NCR_TCL);
533 res -= NCR_READ_REG(sc, NCR_TCM) << 8;
534 printf("dmaintr: discarded %d b (last transfer was %d b).\n",
535 res, esc->sc_prevdmasize);
536 return 0;
537 }
538
539 if (esc->sc_datain &&
540 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
541 printf("dmaintr: empty FIFO of %d\n", resid);
542 DELAY(1);
543 }
544
545 if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
546 resid += NCR_READ_REG(sc, NCR_TCL);
547 resid += NCR_READ_REG(sc, NCR_TCM) << 8;
548
549 if (resid == 0)
550 resid = 65536;
551 }
552
553 trans = esc->sc_dmasize - resid;
554 if (trans < 0) {
555 printf("dmaintr: trans < 0????");
556 trans = esc->sc_dmasize;
557 }
558
559 NCR_DMA(("dmaintr: trans %d, resid %d.\n", trans, resid));
560 *esc->sc_dmaaddr += trans;
561 *esc->sc_dmalen -= trans;
562
563 return 0;
564 }
565
566 int
567 esp_quick_dma_setup(sc, addr, len, datain, dmasize)
568 struct ncr53c9x_softc *sc;
569 caddr_t *addr;
570 size_t *len;
571 int datain;
572 size_t *dmasize;
573 {
574 struct esp_softc *esc = (struct esp_softc *)sc;
575
576 esc->sc_dmaaddr = addr;
577 esc->sc_dmalen = len;
578
579 esc->sc_pdmaddr = (u_int16_t *) *addr;
580 esc->sc_pdmalen = *len;
581 if (esc->sc_pdmalen & 1) {
582 esc->sc_pdmalen--;
583 esc->sc_pad = 1;
584 } else {
585 esc->sc_pad = 0;
586 }
587
588 esc->sc_datain = datain;
589 esc->sc_prevdmasize = esc->sc_dmasize;
590 esc->sc_dmasize = *dmasize;
591
592 return 0;
593 }
594
595 static __inline__ int
596 esp_dafb_have_dreq(esc)
597 struct esp_softc *esc;
598 {
599 u_int32_t r;
600
601 r = bus_space_read_4(esc->sc_tag, esc->sc_bsh, 0);
602 return (r & 0x200);
603 }
604
605 static __inline__ int
606 esp_iosb_have_dreq(esc)
607 struct esp_softc *esc;
608 {
609 return (via2_reg(vIFR) & V2IF_SCSIDRQ);
610 }
611
612 static int espspl=-1;
613 #define __splx(s) __asm __volatile ("movew %0,sr" : : "di" (s));
614 #define __spl2() __splx(PSL_S|PSL_IPL2)
615 #define __spl4() __splx(PSL_S|PSL_IPL4)
616
617 void
618 esp_quick_dma_go(sc)
619 struct ncr53c9x_softc *sc;
620 {
621 struct esp_softc *esc = (struct esp_softc *)sc;
622 extern int *nofault;
623 label_t faultbuf;
624 u_int16_t volatile *pdma;
625 u_char volatile *statreg;
626
627 esc->sc_active = 1;
628
629 espspl = spl2();
630
631 restart_dmago:
632 nofault = (int *) &faultbuf;
633 if (setjmp((label_t *) nofault)) {
634 int i=0;
635
636 nofault = (int *) 0;
637 statreg = esc->sc_reg + NCR_STAT * 16;
638 for (;;) {
639 if (*statreg & 0x80) {
640 goto gotintr;
641 }
642
643 if (esp_have_dreq(esc)) {
644 break;
645 }
646
647 DELAY(1);
648 if (i++ > 10000)
649 panic("esp_dma_go: Argh!");
650 }
651 goto restart_dmago;
652 }
653
654 statreg = esc->sc_reg + NCR_STAT * 16;
655 pdma = (u_int16_t *) (esc->sc_reg + 0x100);
656
657 #define WAIT while (!esp_have_dreq(esc)) if (*statreg & 0x80) goto gotintr
658
659 if (esc->sc_datain == 0) {
660 while (esc->sc_pdmalen) {
661 WAIT;
662 __spl4(); *pdma = *(esc->sc_pdmaddr)++; __spl2()
663 esc->sc_pdmalen -= 2;
664 }
665 if (esc->sc_pad) {
666 unsigned short us;
667 unsigned char *c;
668 c = (unsigned char *) esc->sc_pdmaddr;
669 us = *c;
670 WAIT;
671 __spl4(); *pdma = us; __spl2()
672 }
673 } else {
674 while (esc->sc_pdmalen) {
675 WAIT;
676 __spl4(); *(esc->sc_pdmaddr)++ = *pdma; __spl2()
677 esc->sc_pdmalen -= 2;
678 }
679 if (esc->sc_pad) {
680 unsigned short us;
681 unsigned char *c;
682 WAIT;
683 __spl4(); us = *pdma; __spl2()
684 c = (unsigned char *) esc->sc_pdmaddr;
685 *c = us & 0xff;
686 }
687 }
688 #undef WAIT
689
690 nofault = (int *) 0;
691
692 if ((*statreg & 0x80) == 0) {
693 if (espspl != -1) splx(espspl); espspl = -1;
694 return;
695 }
696
697 gotintr:
698 ncr53c9x_intr(sc);
699 if (espspl != -1) splx(espspl); espspl = -1;
700 }
701
702 int
703 esp_dualbus_intr(sc)
704 register struct ncr53c9x_softc *sc;
705 {
706 if (esp0 && (esp0->sc_reg[NCR_STAT * 16] & 0x80))
707 ncr53c9x_intr((struct ncr53c9x_softc *) esp0);
708
709 if (esp1 && (esp1->sc_reg[NCR_STAT * 16] & 0x80))
710 ncr53c9x_intr((struct ncr53c9x_softc *) esp1);
711
712 return 0;
713 }
714