esp.c revision 1.17
1 /* $NetBSD: esp.c,v 1.17 1998/09/05 15:15:35 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Jason R. Thorpe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project 18 * by Jason R. Thorpe. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1994 Peter Galbavy 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Peter Galbavy 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 54 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 55 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 56 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 57 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 58 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 60 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 61 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Based on aic6360 by Jarle Greipsland 67 * 68 * Acknowledgements: Many of the algorithms used in this driver are 69 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 70 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 71 */ 72 73 /* 74 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 75 * (basically consisting of the match, a bit of the attach, and the 76 * "DMA" glue functions). 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/errno.h> 84 #include <sys/ioctl.h> 85 #include <sys/device.h> 86 #include <sys/buf.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/queue.h> 90 91 #include <dev/scsipi/scsi_all.h> 92 #include <dev/scsipi/scsipi_all.h> 93 #include <dev/scsipi/scsiconf.h> 94 #include <dev/scsipi/scsi_message.h> 95 96 #include <machine/cpu.h> 97 #include <machine/bus.h> 98 #include <machine/param.h> 99 100 #include <dev/ic/ncr53c9xreg.h> 101 #include <dev/ic/ncr53c9xvar.h> 102 103 #include <machine/viareg.h> 104 105 #include <mac68k/obio/espvar.h> 106 #include <mac68k/obio/obiovar.h> 107 108 void espattach __P((struct device *, struct device *, void *)); 109 int espmatch __P((struct device *, struct cfdata *, void *)); 110 111 /* Linkup to the rest of the kernel */ 112 struct cfattach esp_ca = { 113 sizeof(struct esp_softc), espmatch, espattach 114 }; 115 116 struct scsipi_adapter esp_switch = { 117 ncr53c9x_scsi_cmd, 118 minphys, /* no max at this level; handled by DMA code */ 119 NULL, 120 NULL, 121 }; 122 123 struct scsipi_device esp_dev = { 124 NULL, /* Use default error handler */ 125 NULL, /* have a queue, served by this */ 126 NULL, /* have no async handler */ 127 NULL, /* Use default 'done' routine */ 128 }; 129 130 /* 131 * Functions and the switch for the MI code. 132 */ 133 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 134 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 135 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 136 void esp_dma_reset __P((struct ncr53c9x_softc *)); 137 int esp_dma_intr __P((struct ncr53c9x_softc *)); 138 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 139 size_t *, int, size_t *)); 140 void esp_dma_go __P((struct ncr53c9x_softc *)); 141 void esp_dma_stop __P((struct ncr53c9x_softc *)); 142 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 143 void esp_quick_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 144 int esp_quick_dma_intr __P((struct ncr53c9x_softc *)); 145 int esp_quick_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 146 size_t *, int, size_t *)); 147 void esp_quick_dma_go __P((struct ncr53c9x_softc *)); 148 149 int esp_dualbus_intr __P((register struct ncr53c9x_softc *sc)); 150 static struct esp_softc *esp0 = NULL, *esp1 = NULL; 151 152 static __inline__ int esp_dafb_have_dreq __P((struct esp_softc *esc)); 153 static __inline__ int esp_iosb_have_dreq __P((struct esp_softc *esc)); 154 int (*esp_have_dreq) __P((struct esp_softc *esc)); 155 156 struct ncr53c9x_glue esp_glue = { 157 esp_read_reg, 158 esp_write_reg, 159 esp_dma_isintr, 160 esp_dma_reset, 161 esp_dma_intr, 162 esp_dma_setup, 163 esp_dma_go, 164 esp_dma_stop, 165 esp_dma_isactive, 166 NULL, /* gl_clear_latched_intr */ 167 }; 168 169 int 170 espmatch(parent, cf, aux) 171 struct device *parent; 172 struct cfdata *cf; 173 void *aux; 174 { 175 int found = 0; 176 177 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) { 178 found = 1; 179 } 180 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) { 181 found = 1; 182 } 183 184 return found; 185 } 186 187 /* 188 * Attach this instance, and then all the sub-devices 189 */ 190 void 191 espattach(parent, self, aux) 192 struct device *parent, *self; 193 void *aux; 194 { 195 struct obio_attach_args *oa = (struct obio_attach_args *)aux; 196 extern vm_offset_t SCSIBase; 197 struct esp_softc *esc = (void *)self; 198 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 199 int quick = 0; 200 unsigned long reg_offset; 201 202 reg_offset = SCSIBase - IOBase; 203 esc->sc_tag = oa->oa_tag; 204 /* 205 * For Wombat, Primus and Optimus motherboards, DREQ is 206 * visible on bit 0 of the IOSB's emulated VIA2 vIFR (and 207 * the scsi registers are offset 0x1000 bytes from IOBase). 208 * 209 * For the Q700/900/950 it's at f9800024 for bus 0 and 210 * f9800028 for bus 1 (900/950). For these machines, that is also 211 * a (12-bit) configuration register for DAFB's control of the 212 * pseudo-DMA timing. The default value is 0x1d1. 213 */ 214 esp_have_dreq = esp_dafb_have_dreq; 215 if (sc->sc_dev.dv_unit == 0) { 216 if (reg_offset == 0x10000) { 217 quick = 1; 218 esp_have_dreq = esp_iosb_have_dreq; 219 } else if (reg_offset == 0x18000) { 220 quick = 0; 221 } else { 222 if (bus_space_map(esc->sc_tag, 0xf9800024, 223 4, 0, &esc->sc_bsh)) { 224 printf("failed to map 4 at 0xf9800024.\n"); 225 } else { 226 quick = 1; 227 bus_space_write_4(esc->sc_tag, 228 esc->sc_bsh, 0, 0x1d1); 229 } 230 } 231 } else { 232 if (bus_space_map(esc->sc_tag, 0xf9800028, 233 4, 0, &esc->sc_bsh)) { 234 printf("failed to map 4 at 0xf9800028.\n"); 235 } else { 236 quick = 1; 237 bus_space_write_4(esc->sc_tag, esc->sc_bsh, 0, 0x1d1); 238 } 239 } 240 if (quick) { 241 esp_glue.gl_write_reg = esp_quick_write_reg; 242 esp_glue.gl_dma_intr = esp_quick_dma_intr; 243 esp_glue.gl_dma_setup = esp_quick_dma_setup; 244 esp_glue.gl_dma_go = esp_quick_dma_go; 245 } 246 247 /* 248 * Set up the glue for MI code early; we use some of it here. 249 */ 250 sc->sc_glue = &esp_glue; 251 252 /* 253 * Save the regs 254 */ 255 if (sc->sc_dev.dv_unit == 0) { 256 esp0 = esc; 257 258 esc->sc_reg = (volatile u_char *) SCSIBase; 259 via2_register_irq(VIA2_SCSIIRQ, 260 (void (*)(void *))ncr53c9x_intr, esc); 261 esc->irq_mask = V2IF_SCSIIRQ; 262 if (reg_offset == 0x10000) { 263 sc->sc_freq = 16500000; 264 } else { 265 sc->sc_freq = 25000000; 266 } 267 268 if (esp_glue.gl_dma_go == esp_quick_dma_go) { 269 printf(" (quick)"); 270 } 271 } else { 272 esp1 = esc; 273 274 esc->sc_reg = (volatile u_char *) SCSIBase + 0x402; 275 via2_register_irq(VIA2_SCSIIRQ, 276 (void (*)(void *))esp_dualbus_intr, NULL); 277 esc->irq_mask = 0; 278 sc->sc_freq = 25000000; 279 280 if (esp_glue.gl_dma_go == esp_quick_dma_go) { 281 printf(" (quick)"); 282 } 283 } 284 285 printf(": address %p", esc->sc_reg); 286 287 sc->sc_id = 7; 288 289 /* gimme Mhz */ 290 sc->sc_freq /= 1000000; 291 292 /* 293 * It is necessary to try to load the 2nd config register here, 294 * to find out what rev the esp chip is, else the esp_reset 295 * will not set up the defaults correctly. 296 */ 297 sc->sc_cfg1 = sc->sc_id; /* | NCRCFG1_PARENB; */ 298 sc->sc_cfg2 = NCRCFG2_SCSI2; 299 sc->sc_cfg3 = 0; 300 sc->sc_rev = NCR_VARIANT_NCR53C96; 301 302 /* 303 * This is the value used to start sync negotiations 304 * Note that the NCR register "SYNCTP" is programmed 305 * in "clocks per byte", and has a minimum value of 4. 306 * The SCSI period used in negotiation is one-fourth 307 * of the time (in nanoseconds) needed to transfer one byte. 308 * Since the chip's clock is given in MHz, we have the following 309 * formula: 4 * period = (1000 / freq) * 4 310 */ 311 sc->sc_minsync = 1000 / sc->sc_freq; 312 313 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */ 314 /* Really no limit, but since we want to fit into the TCR... */ 315 sc->sc_maxxfer = 8 * 1024; /*64 * 1024; XXX */ 316 317 /* 318 * Now try to attach all the sub-devices 319 */ 320 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 321 322 /* 323 * Configure interrupts. 324 */ 325 if (esc->irq_mask) { 326 via2_reg(vPCR) = 0x22; 327 via2_reg(vIFR) = esc->irq_mask; 328 via2_reg(vIER) = 0x80 | esc->irq_mask; 329 } 330 } 331 332 /* 333 * Glue functions. 334 */ 335 336 u_char 337 esp_read_reg(sc, reg) 338 struct ncr53c9x_softc *sc; 339 int reg; 340 { 341 struct esp_softc *esc = (struct esp_softc *)sc; 342 343 return esc->sc_reg[reg * 16]; 344 } 345 346 void 347 esp_write_reg(sc, reg, val) 348 struct ncr53c9x_softc *sc; 349 int reg; 350 u_char val; 351 { 352 struct esp_softc *esc = (struct esp_softc *)sc; 353 u_char v = val; 354 355 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 356 v = NCRCMD_TRANS; 357 } 358 esc->sc_reg[reg * 16] = v; 359 } 360 361 void 362 esp_dma_stop(sc) 363 struct ncr53c9x_softc *sc; 364 { 365 } 366 367 int 368 esp_dma_isactive(sc) 369 struct ncr53c9x_softc *sc; 370 { 371 struct esp_softc *esc = (struct esp_softc *)sc; 372 373 return esc->sc_active; 374 } 375 376 int 377 esp_dma_isintr(sc) 378 struct ncr53c9x_softc *sc; 379 { 380 struct esp_softc *esc = (struct esp_softc *)sc; 381 382 return esc->sc_reg[NCR_STAT * 16] & 0x80; 383 } 384 385 void 386 esp_dma_reset(sc) 387 struct ncr53c9x_softc *sc; 388 { 389 struct esp_softc *esc = (struct esp_softc *)sc; 390 391 esc->sc_active = 0; 392 esc->sc_tc = 0; 393 } 394 395 int 396 esp_dma_intr(sc) 397 struct ncr53c9x_softc *sc; 398 { 399 register struct esp_softc *esc = (struct esp_softc *)sc; 400 register u_char *p; 401 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 402 register u_int espphase, espstat, espintr; 403 register int cnt; 404 405 if (esc->sc_active == 0) { 406 printf("dma_intr--inactive DMA\n"); 407 return -1; 408 } 409 410 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 411 esc->sc_active = 0; 412 return 0; 413 } 414 415 cnt = *esc->sc_dmalen; 416 if (*esc->sc_dmalen == 0) { 417 printf("data interrupt, but no count left."); 418 } 419 420 p = *esc->sc_dmaaddr; 421 espphase = sc->sc_phase; 422 espstat = (u_int) sc->sc_espstat; 423 espintr = (u_int) sc->sc_espintr; 424 cmdreg = esc->sc_reg + NCR_CMD * 16; 425 fiforeg = esc->sc_reg + NCR_FIFO * 16; 426 statreg = esc->sc_reg + NCR_STAT * 16; 427 intrreg = esc->sc_reg + NCR_INTR * 16; 428 do { 429 if (esc->sc_datain) { 430 *p++ = *fiforeg; 431 cnt--; 432 if (espphase == DATA_IN_PHASE) { 433 *cmdreg = NCRCMD_TRANS; 434 } else { 435 esc->sc_active = 0; 436 } 437 } else { 438 if ( (espphase == DATA_OUT_PHASE) 439 || (espphase == MESSAGE_OUT_PHASE)) { 440 *fiforeg = *p++; 441 cnt--; 442 *cmdreg = NCRCMD_TRANS; 443 } else { 444 esc->sc_active = 0; 445 } 446 } 447 448 if (esc->sc_active) { 449 while (!(*statreg & 0x80)); 450 espstat = *statreg; 451 espintr = *intrreg; 452 espphase = (espintr & NCRINTR_DIS) 453 ? /* Disconnected */ BUSFREE_PHASE 454 : espstat & PHASE_MASK; 455 } 456 } while (esc->sc_active && (espintr & NCRINTR_BS)); 457 sc->sc_phase = espphase; 458 sc->sc_espstat = (u_char) espstat; 459 sc->sc_espintr = (u_char) espintr; 460 *esc->sc_dmaaddr = p; 461 *esc->sc_dmalen = cnt; 462 463 if (*esc->sc_dmalen == 0) { 464 esc->sc_tc = NCRSTAT_TC; 465 } 466 sc->sc_espstat |= esc->sc_tc; 467 return 0; 468 } 469 470 int 471 esp_dma_setup(sc, addr, len, datain, dmasize) 472 struct ncr53c9x_softc *sc; 473 caddr_t *addr; 474 size_t *len; 475 int datain; 476 size_t *dmasize; 477 { 478 struct esp_softc *esc = (struct esp_softc *)sc; 479 480 esc->sc_dmaaddr = addr; 481 esc->sc_dmalen = len; 482 esc->sc_datain = datain; 483 esc->sc_dmasize = *dmasize; 484 esc->sc_tc = 0; 485 486 return 0; 487 } 488 489 void 490 esp_dma_go(sc) 491 struct ncr53c9x_softc *sc; 492 { 493 struct esp_softc *esc = (struct esp_softc *)sc; 494 495 if (esc->sc_datain == 0) { 496 esc->sc_reg[NCR_FIFO * 16] = **esc->sc_dmaaddr; 497 (*esc->sc_dmalen)--; 498 (*esc->sc_dmaaddr)++; 499 } 500 esc->sc_active = 1; 501 } 502 503 void 504 esp_quick_write_reg(sc, reg, val) 505 struct ncr53c9x_softc *sc; 506 int reg; 507 u_char val; 508 { 509 struct esp_softc *esc = (struct esp_softc *)sc; 510 u_char v = val; 511 512 esc->sc_reg[reg * 16] = v; 513 } 514 515 int 516 esp_quick_dma_intr(sc) 517 struct ncr53c9x_softc *sc; 518 { 519 struct esp_softc *esc = (struct esp_softc *)sc; 520 int trans=0, resid=0; 521 522 if (esc->sc_active == 0) 523 panic("dma_intr--inactive DMA\n"); 524 525 esc->sc_active = 0; 526 527 if (esc->sc_dmasize == 0) { 528 int res; 529 530 res = 65536; 531 res -= NCR_READ_REG(sc, NCR_TCL); 532 res -= NCR_READ_REG(sc, NCR_TCM) << 8; 533 printf("dmaintr: discarded %d b (last transfer was %d b).\n", 534 res, esc->sc_prevdmasize); 535 return 0; 536 } 537 538 if (esc->sc_datain && 539 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 540 printf("dmaintr: empty FIFO of %d\n", resid); 541 DELAY(1); 542 } 543 544 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 545 resid += NCR_READ_REG(sc, NCR_TCL); 546 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 547 548 if (resid == 0) 549 resid = 65536; 550 } 551 552 trans = esc->sc_dmasize - resid; 553 if (trans < 0) { 554 printf("dmaintr: trans < 0????"); 555 trans = esc->sc_dmasize; 556 } 557 558 NCR_DMA(("dmaintr: trans %d, resid %d.\n", trans, resid)); 559 *esc->sc_dmaaddr += trans; 560 *esc->sc_dmalen -= trans; 561 562 return 0; 563 } 564 565 int 566 esp_quick_dma_setup(sc, addr, len, datain, dmasize) 567 struct ncr53c9x_softc *sc; 568 caddr_t *addr; 569 size_t *len; 570 int datain; 571 size_t *dmasize; 572 { 573 struct esp_softc *esc = (struct esp_softc *)sc; 574 575 esc->sc_dmaaddr = addr; 576 esc->sc_dmalen = len; 577 578 esc->sc_pdmaddr = (u_int16_t *) *addr; 579 esc->sc_pdmalen = *len; 580 if (esc->sc_pdmalen & 1) { 581 esc->sc_pdmalen--; 582 esc->sc_pad = 1; 583 } else { 584 esc->sc_pad = 0; 585 } 586 587 esc->sc_datain = datain; 588 esc->sc_prevdmasize = esc->sc_dmasize; 589 esc->sc_dmasize = *dmasize; 590 591 return 0; 592 } 593 594 static __inline__ int 595 esp_dafb_have_dreq(esc) 596 struct esp_softc *esc; 597 { 598 u_int32_t r; 599 600 r = bus_space_read_4(esc->sc_tag, esc->sc_bsh, 0); 601 return (r & 0x200); 602 } 603 604 static __inline__ int 605 esp_iosb_have_dreq(esc) 606 struct esp_softc *esc; 607 { 608 return (via2_reg(vIFR) & V2IF_SCSIDRQ); 609 } 610 611 static int espspl=-1; 612 #define __splx(s) __asm __volatile ("movew %0,sr" : : "di" (s)); 613 #define __spl2() __splx(PSL_S|PSL_IPL2) 614 #define __spl4() __splx(PSL_S|PSL_IPL4) 615 616 void 617 esp_quick_dma_go(sc) 618 struct ncr53c9x_softc *sc; 619 { 620 struct esp_softc *esc = (struct esp_softc *)sc; 621 extern int *nofault; 622 label_t faultbuf; 623 u_int16_t volatile *pdma; 624 u_char volatile *statreg; 625 626 esc->sc_active = 1; 627 628 espspl = spl2(); 629 630 restart_dmago: 631 nofault = (int *) &faultbuf; 632 if (setjmp((label_t *) nofault)) { 633 int i=0; 634 635 nofault = (int *) 0; 636 statreg = esc->sc_reg + NCR_STAT * 16; 637 for (;;) { 638 if (*statreg & 0x80) { 639 goto gotintr; 640 } 641 642 if (esp_have_dreq(esc)) { 643 break; 644 } 645 646 DELAY(1); 647 if (i++ > 10000) 648 panic("esp_dma_go: Argh!"); 649 } 650 goto restart_dmago; 651 } 652 653 statreg = esc->sc_reg + NCR_STAT * 16; 654 pdma = (u_int16_t *) (esc->sc_reg + 0x100); 655 656 #define WAIT while (!esp_have_dreq(esc)) if (*statreg & 0x80) goto gotintr 657 658 if (esc->sc_datain == 0) { 659 while (esc->sc_pdmalen) { 660 WAIT; 661 __spl4(); *pdma = *(esc->sc_pdmaddr)++; __spl2() 662 esc->sc_pdmalen -= 2; 663 } 664 if (esc->sc_pad) { 665 unsigned short us; 666 unsigned char *c; 667 c = (unsigned char *) esc->sc_pdmaddr; 668 us = *c; 669 WAIT; 670 __spl4(); *pdma = us; __spl2() 671 } 672 } else { 673 while (esc->sc_pdmalen) { 674 WAIT; 675 __spl4(); *(esc->sc_pdmaddr)++ = *pdma; __spl2() 676 esc->sc_pdmalen -= 2; 677 } 678 if (esc->sc_pad) { 679 unsigned short us; 680 unsigned char *c; 681 WAIT; 682 __spl4(); us = *pdma; __spl2() 683 c = (unsigned char *) esc->sc_pdmaddr; 684 *c = us & 0xff; 685 } 686 } 687 #undef WAIT 688 689 nofault = (int *) 0; 690 691 if ((*statreg & 0x80) == 0) { 692 if (espspl != -1) splx(espspl); espspl = -1; 693 return; 694 } 695 696 gotintr: 697 ncr53c9x_intr(sc); 698 if (espspl != -1) splx(espspl); espspl = -1; 699 } 700 701 int 702 esp_dualbus_intr(sc) 703 register struct ncr53c9x_softc *sc; 704 { 705 if (esp0 && (esp0->sc_reg[NCR_STAT * 16] & 0x80)) 706 ncr53c9x_intr((struct ncr53c9x_softc *) esp0); 707 708 if (esp1 && (esp1->sc_reg[NCR_STAT * 16] & 0x80)) 709 ncr53c9x_intr((struct ncr53c9x_softc *) esp1); 710 711 return 0; 712 } 713
Indexes created Wed Oct 22 00:09:40 GMT 2025