esp.c revision 1.2
1 /* $NetBSD: esp.c,v 1.2 1996/10/30 05:39:21 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <scsi/scsi_all.h> 85 #include <scsi/scsiconf.h> 86 #include <scsi/scsi_message.h> 87 88 #include <machine/cpu.h> 89 #include <machine/param.h> 90 91 #if defined(__sparc__) 92 #define SPARC_DRIVER 93 #include <machine/autoconf.h> 94 #include <sparc/dev/sbusvar.h> 95 #include <sparc/dev/dmareg.h> 96 #include <sparc/dev/dmavar.h> 97 #include <sparc/dev/espreg.h> 98 #include <sparc/dev/espvar.h> 99 #else 100 #if (_MACHINE == mac68k) 101 #define MAC68K_DRIVER 102 #include <machine/viareg.h> 103 104 struct dma_softc { 105 struct esp_softc *sc_esp; 106 int sc_active; 107 int sc_datain; 108 size_t sc_dmasize; 109 size_t sc_dmatrans; 110 char **sc_dmaaddr; 111 size_t *sc_pdmalen; 112 }; 113 114 #include <mac68k/dev/espreg.h> 115 #include <mac68k/dev/espvar.h> 116 #undef ESPCMD_DMA 117 #define ESPCMD_DMA 0 /* No DMA */ 118 #undef ESPCMD_TRPAD 119 #define ESPCMD_TRPAD 0x98 /* TRPAD needs DMA flag*/ 120 121 static __inline__ void dma_intr __P((struct dma_softc *sc)); 122 123 static __inline__ void 124 dma_intr(sc) 125 struct dma_softc *sc; 126 { 127 u_char *p; 128 129 if (sc->sc_active == 0) { 130 printf("dma_intr--inactive\n"); 131 return; 132 } 133 134 p = *sc->sc_dmaaddr; 135 if (sc->sc_datain) { 136 if (ESP_READ_REG(sc->sc_esp, ESP_FFLAG) & ESPFIFO_FF) { 137 *p++ = ESP_READ_REG(sc->sc_esp, ESP_FIFO); 138 (*sc->sc_pdmalen)--; 139 } else { 140 printf("DMA, Data in, no data, pdmalen is %d\n", 141 *sc->sc_pdmalen); 142 } 143 *sc->sc_dmaaddr = p; 144 if (sc->sc_esp->sc_phase != DATA_IN_PHASE) { 145 if (*sc->sc_pdmalen == 0) { 146 /* 147 * Fake terminal count since this isn't 148 * a real DMA transaction and the chip 149 * will therefore not trip TC itself. 150 */ 151 sc->sc_esp->sc_espstat |= ESPSTAT_TC; 152 } 153 sc->sc_active = 0; 154 return; 155 } 156 ESPCMD(sc->sc_esp, ESPCMD_TRANS); 157 } else if (sc->sc_esp->sc_phase == DATA_OUT_PHASE) { 158 p++; 159 ESP_WRITE_REG(sc->sc_esp, ESP_FIFO, *p); 160 *sc->sc_dmaaddr = p; 161 (*sc->sc_pdmalen)--; 162 ESPCMD(sc->sc_esp, ESPCMD_TRANS); 163 } else { 164 if ( (sc->sc_esp->sc_prevphase == DATA_OUT_PHASE) 165 && (*sc->sc_pdmalen == 0)) { 166 sc->sc_esp->sc_espstat |= ESPSTAT_TC; 167 } 168 sc->sc_active = 0; 169 } 170 } 171 #else 172 #include <dev/tc/tcvar.h> 173 #include <alpha/tc/tcdsvar.h> 174 #include <alpha/tc/espreg.h> 175 #include <alpha/tc/espvar.h> 176 #endif 177 #endif 178 179 int esp_debug = 0; /*ESP_SHOWPHASE|ESP_SHOWMISC|ESP_SHOWTRAC|ESP_SHOWCMDS;*/ 180 181 /*static*/ void espattach __P((struct device *, struct device *, void *)); 182 /*static*/ int espmatch __P((struct device *, void *, void *)); 183 /*static*/ u_int esp_adapter_info __P((struct esp_softc *)); 184 /*static*/ void espreadregs __P((struct esp_softc *)); 185 /*static*/ void esp_select __P((struct esp_softc *, struct esp_ecb *)); 186 /*static*/ int esp_reselect __P((struct esp_softc *, int)); 187 /*static*/ void esp_scsi_reset __P((struct esp_softc *)); 188 /*static*/ void esp_reset __P((struct esp_softc *)); 189 /*static*/ void esp_init __P((struct esp_softc *, int)); 190 /*static*/ int esp_scsi_cmd __P((struct scsi_xfer *)); 191 /*static*/ int esp_poll __P((struct esp_softc *, struct scsi_xfer *, int)); 192 /*static*/ void esp_sched __P((struct esp_softc *)); 193 /*static*/ void esp_done __P((struct esp_softc *, struct esp_ecb *)); 194 /*static*/ void esp_msgin __P((struct esp_softc *)); 195 /*static*/ void esp_msgout __P((struct esp_softc *)); 196 /*static*/ int espintr __P((struct esp_softc *)); 197 /*static*/ void esp_timeout __P((void *arg)); 198 /*static*/ void esp_abort __P((struct esp_softc *, struct esp_ecb *)); 199 /*static*/ void esp_dequeue __P((struct esp_softc *, struct esp_ecb *)); 200 void esp_sense __P((struct esp_softc *, struct esp_ecb *)); 201 void esp_free_ecb __P((struct esp_softc *, struct esp_ecb *, int)); 202 struct esp_ecb *esp_get_ecb __P((struct esp_softc *, int)); 203 static inline int esp_stp2cpb __P((struct esp_softc *, int)); 204 static inline int esp_cpb2stp __P((struct esp_softc *, int)); 205 static inline void esp_setsync __P((struct esp_softc *, struct esp_tinfo *)); 206 207 /* Linkup to the rest of the kernel */ 208 struct cfattach esp_ca = { 209 sizeof(struct esp_softc), espmatch, espattach 210 }; 211 212 struct cfdriver esp_cd = { 213 NULL, "esp", DV_DULL 214 }; 215 216 struct scsi_adapter esp_switch = { 217 esp_scsi_cmd, 218 minphys, /* no max at this level; handled by DMA code */ 219 NULL, 220 NULL, 221 }; 222 223 struct scsi_device esp_dev = { 224 NULL, /* Use default error handler */ 225 NULL, /* have a queue, served by this */ 226 NULL, /* have no async handler */ 227 NULL, /* Use default 'done' routine */ 228 }; 229 230 int 231 espmatch(parent, vcf, aux) 232 struct device *parent; 233 void *vcf, *aux; 234 { 235 struct cfdata *cf = vcf; 236 #ifdef SPARC_DRIVER 237 register struct confargs *ca = aux; 238 register struct romaux *ra = &ca->ca_ra; 239 240 if (strcmp(cf->cf_driver->cd_name, ra->ra_name)) 241 return (0); 242 if (ca->ca_bustype == BUS_SBUS) 243 return (1); 244 ra->ra_len = NBPG; 245 return (probeget(ra->ra_vaddr, 1) != -1); 246 #else 247 #ifdef MAC68K_DRIVER 248 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) 249 return (1); 250 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) 251 return (1); 252 return (0); 253 #else 254 struct tcdsdev_attach_args *tcdsdev = aux; 255 256 if (strncmp(tcdsdev->tcdsda_modname, "PMAZ-AA ", TC_ROM_LLEN)) 257 return (0); 258 return (!tc_badaddr(tcdsdev->tcdsda_addr)); 259 #endif 260 #endif 261 } 262 263 /* 264 * Attach this instance, and then all the sub-devices 265 */ 266 void 267 espattach(parent, self, aux) 268 struct device *parent, *self; 269 void *aux; 270 { 271 #ifdef SPARC_DRIVER 272 register struct confargs *ca = aux; 273 #else 274 #ifdef MAC68K_DRIVER 275 extern vm_offset_t SCSIBase; 276 #else 277 register struct tcdsdev_attach_args *tcdsdev = aux; 278 #endif 279 #endif 280 struct esp_softc *sc = (void *)self; 281 #ifdef SPARC_DRIVER 282 struct bootpath *bp; 283 int dmachild = strncmp(parent->dv_xname, "dma", 3) == 0; 284 #endif 285 286 #ifdef SPARC_DRIVER 287 /* 288 * Make sure things are sane. I don't know if this is ever 289 * necessary, but it seem to be in all of Torek's code. 290 */ 291 if (ca->ca_ra.ra_nintr != 1) { 292 printf(": expected 1 interrupt, got %d\n", ca->ca_ra.ra_nintr); 293 return; 294 } 295 296 sc->sc_pri = ca->ca_ra.ra_intr[0].int_pri; 297 printf(" pri %d", sc->sc_pri); 298 299 /* 300 * Map my registers in, if they aren't already in virtual 301 * address space. 302 */ 303 if (ca->ca_ra.ra_vaddr) 304 sc->sc_reg = (volatile u_char *) ca->ca_ra.ra_vaddr; 305 else { 306 sc->sc_reg = (volatile u_char *) 307 mapiodev(ca->ca_ra.ra_reg, 0, ca->ca_ra.ra_len, ca->ca_bustype); 308 } 309 #else 310 #ifdef MAC68K_DRIVER 311 if (sc->sc_dev.dv_unit == 0) { 312 unsigned long reg_offset; 313 314 sc->sc_reg = (volatile u_char *) SCSIBase; 315 mac68k_register_scsi_irq((void (*)(void *)) espintr, sc); 316 sc->irq_mask = V2IF_SCSIIRQ; 317 reg_offset = SCSIBase - IOBase; 318 if (reg_offset == 0x10000) { 319 sc->sc_freq = 16500000; 320 } else { 321 sc->sc_freq = 25000000; 322 } 323 } else { 324 sc->sc_reg = (volatile u_char *) SCSIBase + 0x400; 325 mac68k_register_scsi_b_irq((void (*)(void *)) espintr, sc); 326 sc->irq_mask = V2IF_SCSIDRQ; /* V2IF_T1? If so, fix ^^, too */ 327 sc->sc_freq = 25000000; 328 } 329 sc->sc_dma = &sc->_sc_dma; 330 printf(": address %p", sc->sc_reg); 331 332 sc->sc_id = 7; 333 #else 334 sc->sc_reg = (volatile u_int32_t *)tcdsdev->tcdsda_addr; 335 sc->sc_cookie = tcdsdev->tcdsda_cookie; 336 sc->sc_dma = tcdsdev->tcdsda_sc; 337 338 printf(": address %x", sc->sc_reg); 339 tcds_intr_establish(parent, sc->sc_cookie, TC_IPL_BIO, 340 (int (*)(void *))espintr, sc); 341 #endif 342 #endif 343 344 #ifdef SPARC_DRIVER 345 /* Other settings */ 346 sc->sc_node = ca->ca_ra.ra_node; 347 if (ca->ca_bustype == BUS_SBUS) { 348 sc->sc_id = getpropint(sc->sc_node, "initiator-id", 7); 349 sc->sc_freq = getpropint(sc->sc_node, "clock-frequency", -1); 350 } else { 351 sc->sc_id = 7; 352 sc->sc_freq = 24000000; 353 } 354 if (sc->sc_freq < 0) 355 sc->sc_freq = ((struct sbus_softc *) 356 sc->sc_dev.dv_parent)->sc_clockfreq; 357 #else 358 #ifdef MAC68K_DRIVER 359 #else 360 if (parent->dv_cfdata->cf_driver == &tcds_cd) { 361 sc->sc_id = tcdsdev->tcdsda_id; 362 sc->sc_freq = tcdsdev->tcdsda_freq; 363 } else { 364 /* XXX */ 365 sc->sc_id = 7; 366 sc->sc_freq = 24000000; 367 } 368 #endif 369 #endif 370 371 /* gimme Mhz */ 372 sc->sc_freq /= 1000000; 373 374 #ifdef SPARC_DRIVER 375 if (dmachild) { 376 sc->sc_dma = (struct dma_softc *)parent; 377 sc->sc_dma->sc_esp = sc; 378 } else { 379 /* 380 * find the DMA by poking around the dma device structures 381 * 382 * What happens here is that if the dma driver has not been 383 * configured, then this returns a NULL pointer. Then when the 384 * dma actually gets configured, it does the opposing test, and 385 * if the sc->sc_esp field in it's softc is NULL, then tries to 386 * find the matching esp driver. 387 * 388 */ 389 sc->sc_dma = (struct dma_softc *) 390 getdevunit("dma", sc->sc_dev.dv_unit); 391 392 /* 393 * and a back pointer to us, for DMA 394 */ 395 if (sc->sc_dma) 396 sc->sc_dma->sc_esp = sc; 397 else 398 panic("espattach: no dma found"); 399 } 400 #else 401 sc->sc_dma->sc_esp = sc; /* XXX */ 402 #endif 403 404 /* 405 * It is necessary to try to load the 2nd config register here, 406 * to find out what rev the esp chip is, else the esp_reset 407 * will not set up the defaults correctly. 408 */ 409 sc->sc_cfg1 = sc->sc_id | ESPCFG1_PARENB; 410 #ifdef SPARC_DRIVER 411 sc->sc_cfg2 = ESPCFG2_SCSI2 | ESPCFG2_RPE; 412 sc->sc_cfg3 = ESPCFG3_CDB; 413 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 414 415 if ((ESP_READ_REG(sc, ESP_CFG2) & ~ESPCFG2_RSVD) != (ESPCFG2_SCSI2 | ESPCFG2_RPE)) { 416 printf(": ESP100"); 417 sc->sc_rev = ESP100; 418 } else { 419 sc->sc_cfg2 = ESPCFG2_SCSI2; 420 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 421 sc->sc_cfg3 = 0; 422 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 423 sc->sc_cfg3 = (ESPCFG3_CDB | ESPCFG3_FCLK); 424 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 425 if (ESP_READ_REG(sc, ESP_CFG3) != (ESPCFG3_CDB | ESPCFG3_FCLK)) { 426 printf(": ESP100A"); 427 sc->sc_rev = ESP100A; 428 } else { 429 /* ESPCFG2_FE enables > 64K transfers */ 430 sc->sc_cfg2 |= ESPCFG2_FE; 431 sc->sc_cfg3 = 0; 432 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 433 printf(": ESP200"); 434 sc->sc_rev = ESP200; 435 } 436 } 437 #else 438 #ifdef MAC68K_DRIVER 439 sc->sc_cfg2 = ESPCFG2_SCSI2; 440 sc->sc_cfg3 = 0x4; 441 printf(": NCR53C96"); 442 sc->sc_rev = NCR53C96; 443 #else 444 sc->sc_cfg2 = ESPCFG2_SCSI2; 445 sc->sc_cfg3 = 0x4; /* Save residual byte. XXX??? */ 446 printf(": NCR53C94"); 447 sc->sc_rev = NCR53C94; 448 #endif 449 #endif 450 451 /* 452 * This is the value used to start sync negotiations 453 * Note that the ESP register "SYNCTP" is programmed 454 * in "clocks per byte", and has a minimum value of 4. 455 * The SCSI period used in negotiation is one-fourth 456 * of the time (in nanoseconds) needed to transfer one byte. 457 * Since the chip's clock is given in MHz, we have the following 458 * formula: 4 * period = (1000 / freq) * 4 459 */ 460 sc->sc_minsync = 1000 / sc->sc_freq; 461 462 #ifdef SPARC_DRIVER 463 /* 464 * Alas, we must now modify the value a bit, because it's 465 * only valid when can switch on FASTCLK and FASTSCSI bits 466 * in config register 3... 467 */ 468 switch (sc->sc_rev) { 469 case ESP100: 470 sc->sc_maxxfer = 64 * 1024; 471 sc->sc_minsync = 0; /* No synch on old chip? */ 472 break; 473 case ESP100A: 474 sc->sc_maxxfer = 64 * 1024; 475 sc->sc_minsync = esp_cpb2stp(sc, 5); /* Min clocks/byte is 5 */ 476 break; 477 case ESP200: 478 sc->sc_maxxfer = 16 * 1024 * 1024; 479 /* XXX - do actually set FAST* bits */ 480 } 481 #else 482 #ifdef MAC68K_DRIVER 483 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */ 484 /* Really no limit, but since we want to fit into the TCR... */ 485 sc->sc_maxxfer = 64 * 1024; 486 #else 487 sc->sc_maxxfer = 64 * 1024; 488 #endif 489 #endif 490 491 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 492 493 /* The value *must not* be == 1. Make it 2 */ 494 if (sc->sc_ccf == 1) 495 sc->sc_ccf = 2; 496 497 /* 498 * The recommended timeout is 250ms. This register is loaded 499 * with a value calculated as follows, from the docs: 500 * 501 * (timout period) x (CLK frequency) 502 * reg = ------------------------------------- 503 * 8192 x (Clock Conversion Factor) 504 * 505 * Since CCF has a linear relation to CLK, this generally computes 506 * to the constant of 153. 507 */ 508 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 509 510 /* CCF register only has 3 bits; 0 is actually 8 */ 511 sc->sc_ccf &= 7; 512 513 /* Reset state & bus */ 514 sc->sc_state = 0; 515 esp_init(sc, 1); 516 517 printf(" %dMhz, target %d\n", sc->sc_freq, sc->sc_id); 518 519 #ifdef SPARC_DRIVER 520 /* add me to the sbus structures */ 521 sc->sc_sd.sd_reset = (void *) esp_reset; 522 #if defined(SUN4C) || defined(SUN4M) 523 if (ca->ca_bustype == BUS_SBUS) { 524 if (dmachild) 525 sbus_establish(&sc->sc_sd, sc->sc_dev.dv_parent); 526 else 527 sbus_establish(&sc->sc_sd, &sc->sc_dev); 528 } 529 #endif /* SUN4C || SUN4M */ 530 #endif 531 532 #ifdef SPARC_DRIVER 533 /* and the interuppts */ 534 sc->sc_ih.ih_fun = (void *) espintr; 535 sc->sc_ih.ih_arg = sc; 536 intr_establish(sc->sc_pri, &sc->sc_ih); 537 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 538 #endif 539 540 /* 541 * fill in the prototype scsi_link. 542 */ 543 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 544 sc->sc_link.adapter_softc = sc; 545 sc->sc_link.adapter_target = sc->sc_id; 546 sc->sc_link.adapter = &esp_switch; 547 sc->sc_link.device = &esp_dev; 548 sc->sc_link.openings = 2; 549 550 /* 551 * If the boot path is "esp" at the moment and it's me, then 552 * walk our pointer to the sub-device, ready for the config 553 * below. 554 */ 555 #ifdef SPARC_DRIVER 556 bp = ca->ca_ra.ra_bp; 557 switch (ca->ca_bustype) { 558 case BUS_SBUS: 559 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 560 SAME_ESP(sc, bp, ca)) 561 bootpath_store(1, bp + 1); 562 break; 563 default: 564 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 565 bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit) 566 bootpath_store(1, bp + 1); 567 break; 568 } 569 #endif 570 571 /* 572 * Now try to attach all the sub-devices 573 */ 574 config_found(self, &sc->sc_link, scsiprint); 575 576 #ifdef MAC68K_DRIVER 577 via2_reg(vPCR) = 0x22; 578 via2_reg(vIFR) = sc->irq_mask; 579 via2_reg(vIER) = 0x80 | sc->irq_mask; 580 #endif 581 #ifdef SPARC_DRIVER 582 bootpath_store(1, NULL); 583 #endif 584 } 585 586 /* 587 * This is the generic esp reset function. It does not reset the SCSI bus, 588 * only this controllers, but kills any on-going commands, and also stops 589 * and resets the DMA. 590 * 591 * After reset, registers are loaded with the defaults from the attach 592 * routine above. 593 */ 594 void 595 esp_reset(sc) 596 struct esp_softc *sc; 597 { 598 599 /* reset DMA first */ 600 DMA_RESET(sc->sc_dma); 601 602 /* reset SCSI chip */ 603 ESPCMD(sc, ESPCMD_RSTCHIP); 604 ESPCMD(sc, ESPCMD_NOP); 605 DELAY(500); 606 607 /* do these backwards, and fall through */ 608 switch (sc->sc_rev) { 609 #ifndef SPARC_DRIVER 610 case NCR53C96: 611 case NCR53C94: 612 #endif 613 case ESP200: 614 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 615 case ESP100A: 616 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 617 case ESP100: 618 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 619 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 620 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 621 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 622 break; 623 default: 624 printf("%s: unknown revision code, assuming ESP100\n", 625 sc->sc_dev.dv_xname); 626 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 627 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 628 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 629 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 630 } 631 } 632 633 /* 634 * Reset the SCSI bus, but not the chip 635 */ 636 void 637 esp_scsi_reset(sc) 638 struct esp_softc *sc; 639 { 640 #ifdef SPARC_DRIVER 641 /* stop DMA first, as the chip will return to Bus Free phase */ 642 DMACSR(sc->sc_dma) &= ~D_EN_DMA; 643 #else 644 /* 645 * XXX STOP DMA FIRST 646 */ 647 #endif 648 649 printf("esp: resetting SCSI bus\n"); 650 ESPCMD(sc, ESPCMD_RSTSCSI); 651 } 652 653 /* 654 * Initialize esp state machine 655 */ 656 void 657 esp_init(sc, doreset) 658 struct esp_softc *sc; 659 int doreset; 660 { 661 struct esp_ecb *ecb; 662 int r; 663 664 ESP_TRACE(("[ESP_INIT(%d)] ", doreset)); 665 666 if (sc->sc_state == 0) { 667 /* First time through; initialize. */ 668 TAILQ_INIT(&sc->ready_list); 669 TAILQ_INIT(&sc->nexus_list); 670 TAILQ_INIT(&sc->free_list); 671 sc->sc_nexus = NULL; 672 ecb = sc->sc_ecb; 673 bzero(ecb, sizeof(sc->sc_ecb)); 674 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 675 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 676 ecb++; 677 } 678 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 679 } else { 680 /* Cancel any active commands. */ 681 sc->sc_state = ESP_CLEANING; 682 if ((ecb = sc->sc_nexus) != NULL) { 683 ecb->xs->error = XS_DRIVER_STUFFUP; 684 untimeout(esp_timeout, ecb); 685 esp_done(sc, ecb); 686 } 687 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 688 ecb->xs->error = XS_DRIVER_STUFFUP; 689 untimeout(esp_timeout, ecb); 690 esp_done(sc, ecb); 691 } 692 } 693 694 /* 695 * reset the chip to a known state 696 */ 697 esp_reset(sc); 698 699 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 700 for (r = 0; r < 8; r++) { 701 struct esp_tinfo *ti = &sc->sc_tinfo[r]; 702 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 703 int fl = sc->sc_dev.dv_cfdata->cf_flags; 704 705 ti->flags = ((sc->sc_minsync && !(fl & (1<<(r+8)))) 706 ? T_NEGOTIATE : 0) | 707 ((fl & (1<<r)) ? T_RSELECTOFF : 0) | 708 T_NEED_TO_RESET; 709 ti->period = sc->sc_minsync; 710 ti->offset = 0; 711 } 712 713 if (doreset) { 714 sc->sc_state = ESP_SBR; 715 ESPCMD(sc, ESPCMD_RSTSCSI); 716 } else { 717 sc->sc_state = ESP_IDLE; 718 } 719 } 720 721 /* 722 * Read the ESP registers, and save their contents for later use. 723 * ESP_STAT, ESP_STEP & ESP_INTR are mostly zeroed out when reading 724 * ESP_INTR - so make sure it is the last read. 725 * 726 * I think that (from reading the docs) most bits in these registers 727 * only make sense when he DMA CSR has an interrupt showing. Call only 728 * if an interrupt is pending. 729 */ 730 void 731 espreadregs(sc) 732 struct esp_softc *sc; 733 { 734 735 sc->sc_espstat = ESP_READ_REG(sc, ESP_STAT); 736 /* Only the stepo bits are of interest */ 737 sc->sc_espstep = ESP_READ_REG(sc, ESP_STEP) & ESPSTEP_MASK; 738 sc->sc_espintr = ESP_READ_REG(sc, ESP_INTR); 739 740 #if !defined(SPARC_DRIVER) && !defined(MAC68K_DRIVER) 741 /* Clear the TCDS interrupt bit. */ 742 (void)tcds_scsi_isintr(sc->sc_dma, 1); 743 #endif 744 745 /* 746 * Determine the SCSI bus phase, return either a real SCSI bus phase 747 * or some pseudo phase we use to detect certain exceptions. 748 */ 749 750 sc->sc_phase = (sc->sc_espintr & ESPINTR_DIS) 751 ? /* Disconnected */ BUSFREE_PHASE 752 : sc->sc_espstat & ESPSTAT_PHASE; 753 754 ESP_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 755 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 756 } 757 758 /* 759 * Convert chip register Clock Per Byte value to Synchronous Transfer Period. 760 */ 761 static inline int 762 esp_cpb2stp(sc, cpb) 763 struct esp_softc *sc; 764 int cpb; 765 { 766 return ((250 * cpb) / sc->sc_freq); 767 } 768 769 /* 770 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 771 */ 772 static inline int 773 esp_stp2cpb(sc, period) 774 struct esp_softc *sc; 775 int period; 776 { 777 int v; 778 v = (sc->sc_freq * period) / 250; 779 if (esp_cpb2stp(sc, v) < period) 780 /* Correct round-down error */ 781 v++; 782 return v; 783 } 784 785 static inline void 786 esp_setsync(sc, ti) 787 struct esp_softc *sc; 788 struct esp_tinfo *ti; 789 { 790 791 if (ti->flags & T_SYNCMODE) { 792 ESP_WRITE_REG(sc, ESP_SYNCOFF, ti->offset); 793 ESP_WRITE_REG(sc, ESP_SYNCTP, esp_stp2cpb(sc, ti->period)); 794 } else { 795 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 796 ESP_WRITE_REG(sc, ESP_SYNCTP, 0); 797 } 798 } 799 800 /* 801 * Send a command to a target, set the driver state to ESP_SELECTING 802 * and let the caller take care of the rest. 803 * 804 * Keeping this as a function allows me to say that this may be done 805 * by DMA instead of programmed I/O soon. 806 */ 807 void 808 esp_select(sc, ecb) 809 struct esp_softc *sc; 810 struct esp_ecb *ecb; 811 { 812 struct scsi_link *sc_link = ecb->xs->sc_link; 813 int target = sc_link->target; 814 struct esp_tinfo *ti = &sc->sc_tinfo[target]; 815 u_char *cmd; 816 int clen; 817 818 ESP_TRACE(("[esp_select(t%d,l%d,cmd:%x)] ", sc_link->target, sc_link->lun, ecb->cmd.opcode)); 819 820 /* new state ESP_SELECTING */ 821 sc->sc_state = ESP_SELECTING; 822 823 ESPCMD(sc, ESPCMD_FLUSH); 824 825 /* 826 * The docs say the target register is never reset, and I 827 * can't think of a better place to set it 828 */ 829 ESP_WRITE_REG(sc, ESP_SELID, target); 830 esp_setsync(sc, ti); 831 832 /* 833 * Who am I. This is where we tell the target that we are 834 * happy for it to disconnect etc. 835 */ 836 ESP_WRITE_REG(sc, ESP_FIFO, 837 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 838 839 if (ti->flags & T_NEGOTIATE) { 840 /* Arbitrate, select and stop after IDENTIFY message */ 841 ESPCMD(sc, ESPCMD_SELATNS); 842 return; 843 } 844 845 /* Now the command into the FIFO */ 846 cmd = (u_char *)&ecb->cmd; 847 clen = ecb->clen; 848 while (clen--) 849 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 850 851 /* And get the targets attention */ 852 ESPCMD(sc, ESPCMD_SELATN); 853 } 854 855 void 856 esp_free_ecb(sc, ecb, flags) 857 struct esp_softc *sc; 858 struct esp_ecb *ecb; 859 int flags; 860 { 861 int s; 862 863 s = splbio(); 864 865 ecb->flags = 0; 866 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 867 868 /* 869 * If there were none, wake anybody waiting for one to come free, 870 * starting with queued entries. 871 */ 872 if (ecb->chain.tqe_next == 0) 873 wakeup(&sc->free_list); 874 875 splx(s); 876 } 877 878 struct esp_ecb * 879 esp_get_ecb(sc, flags) 880 struct esp_softc *sc; 881 int flags; 882 { 883 struct esp_ecb *ecb; 884 int s; 885 886 s = splbio(); 887 888 while ((ecb = sc->free_list.tqh_first) == NULL && 889 (flags & SCSI_NOSLEEP) == 0) 890 tsleep(&sc->free_list, PRIBIO, "especb", 0); 891 if (ecb) { 892 TAILQ_REMOVE(&sc->free_list, ecb, chain); 893 ecb->flags |= ECB_ALLOC; 894 } 895 896 splx(s); 897 return ecb; 898 } 899 900 /* 901 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 902 */ 903 904 /* 905 * Start a SCSI-command 906 * This function is called by the higher level SCSI-driver to queue/run 907 * SCSI-commands. 908 */ 909 int 910 esp_scsi_cmd(xs) 911 struct scsi_xfer *xs; 912 { 913 struct scsi_link *sc_link = xs->sc_link; 914 struct esp_softc *sc = sc_link->adapter_softc; 915 struct esp_ecb *ecb; 916 int s, flags; 917 918 ESP_TRACE(("[esp_scsi_cmd] ")); 919 ESP_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 920 sc_link->target)); 921 922 flags = xs->flags; 923 if ((ecb = esp_get_ecb(sc, flags)) == NULL) { 924 xs->error = XS_DRIVER_STUFFUP; 925 return TRY_AGAIN_LATER; 926 } 927 928 /* Initialize ecb */ 929 ecb->xs = xs; 930 ecb->timeout = xs->timeout; 931 932 if (xs->flags & SCSI_RESET) { 933 ecb->flags |= ECB_RESET; 934 ecb->clen = 0; 935 ecb->dleft = 0; 936 } else { 937 bcopy(xs->cmd, &ecb->cmd, xs->cmdlen); 938 ecb->clen = xs->cmdlen; 939 ecb->daddr = xs->data; 940 ecb->dleft = xs->datalen; 941 } 942 ecb->stat = 0; 943 944 s = splbio(); 945 946 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 947 if (sc->sc_state == ESP_IDLE) 948 esp_sched(sc); 949 950 splx(s); 951 952 if ((flags & SCSI_POLL) == 0) 953 return SUCCESSFULLY_QUEUED; 954 955 /* Not allowed to use interrupts, use polling instead */ 956 if (esp_poll(sc, xs, ecb->timeout)) { 957 esp_timeout(ecb); 958 if (esp_poll(sc, xs, ecb->timeout)) 959 esp_timeout(ecb); 960 } 961 return COMPLETE; 962 } 963 964 /* 965 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 966 */ 967 int 968 esp_poll(sc, xs, count) 969 struct esp_softc *sc; 970 struct scsi_xfer *xs; 971 int count; 972 { 973 974 ESP_TRACE(("[esp_poll] ")); 975 while (count) { 976 if (DMA_ISINTR(sc->sc_dma)) { 977 espintr(sc); 978 } 979 #if alternatively 980 if (ESP_READ_REG(sc, ESP_STAT) & ESPSTAT_INT) 981 espintr(sc); 982 #endif 983 if ((xs->flags & ITSDONE) != 0) 984 return 0; 985 if (sc->sc_state == ESP_IDLE) { 986 ESP_TRACE(("[esp_poll: rescheduling] ")); 987 esp_sched(sc); 988 } 989 DELAY(1000); 990 count--; 991 } 992 return 1; 993 } 994 995 996 /* 997 * LOW LEVEL SCSI UTILITIES 998 */ 999 1000 /* 1001 * Schedule a scsi operation. This has now been pulled out of the interrupt 1002 * handler so that we may call it from esp_scsi_cmd and esp_done. This may 1003 * save us an unecessary interrupt just to get things going. Should only be 1004 * called when state == ESP_IDLE and at bio pl. 1005 */ 1006 void 1007 esp_sched(sc) 1008 struct esp_softc *sc; 1009 { 1010 struct esp_ecb *ecb; 1011 struct scsi_link *sc_link; 1012 struct esp_tinfo *ti; 1013 1014 ESP_TRACE(("[esp_sched] ")); 1015 if (sc->sc_state != ESP_IDLE) 1016 panic("esp_sched: not IDLE (state=%d)", sc->sc_state); 1017 1018 /* 1019 * Find first ecb in ready queue that is for a target/lunit 1020 * combinations that is not busy. 1021 */ 1022 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 1023 sc_link = ecb->xs->sc_link; 1024 ti = &sc->sc_tinfo[sc_link->target]; 1025 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 1026 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1027 sc->sc_nexus = ecb; 1028 esp_select(sc, ecb); 1029 break; 1030 } else 1031 ESP_MISC(("%d:%d busy\n", 1032 sc_link->target, sc_link->lun)); 1033 } 1034 } 1035 1036 void 1037 esp_sense(sc, ecb) 1038 struct esp_softc *sc; 1039 struct esp_ecb *ecb; 1040 { 1041 struct scsi_xfer *xs = ecb->xs; 1042 struct scsi_link *sc_link = xs->sc_link; 1043 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1044 struct scsi_sense *ss = (void *)&ecb->cmd; 1045 1046 ESP_MISC(("requesting sense ")); 1047 /* Next, setup a request sense command block */ 1048 bzero(ss, sizeof(*ss)); 1049 ss->opcode = REQUEST_SENSE; 1050 ss->byte2 = sc_link->lun << 5; 1051 ss->length = sizeof(struct scsi_sense_data); 1052 ecb->clen = sizeof(*ss); 1053 ecb->daddr = (char *)&xs->sense; 1054 ecb->dleft = sizeof(struct scsi_sense_data); 1055 ecb->flags |= ECB_SENSE; 1056 ti->senses++; 1057 if (ecb->flags & ECB_NEXUS) 1058 ti->lubusy &= ~(1 << sc_link->lun); 1059 if (ecb == sc->sc_nexus) { 1060 esp_select(sc, ecb); 1061 } else { 1062 esp_dequeue(sc, ecb); 1063 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1064 if (sc->sc_state == ESP_IDLE) 1065 esp_sched(sc); 1066 } 1067 } 1068 1069 /* 1070 * POST PROCESSING OF SCSI_CMD (usually current) 1071 */ 1072 void 1073 esp_done(sc, ecb) 1074 struct esp_softc *sc; 1075 struct esp_ecb *ecb; 1076 { 1077 struct scsi_xfer *xs = ecb->xs; 1078 struct scsi_link *sc_link = xs->sc_link; 1079 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1080 1081 ESP_TRACE(("[esp_done(error:%x)] ", xs->error)); 1082 1083 /* 1084 * Now, if we've come here with no error code, i.e. we've kept the 1085 * initial XS_NOERROR, and the status code signals that we should 1086 * check sense, we'll need to set up a request sense cmd block and 1087 * push the command back into the ready queue *before* any other 1088 * commands for this target/lunit, else we lose the sense info. 1089 * We don't support chk sense conditions for the request sense cmd. 1090 */ 1091 if (xs->error == XS_NOERROR) { 1092 if ((ecb->flags & ECB_ABORT) != 0) { 1093 xs->error = XS_DRIVER_STUFFUP; 1094 } else if ((ecb->flags & ECB_SENSE) != 0) { 1095 xs->error = XS_SENSE; 1096 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 1097 /* First, save the return values */ 1098 xs->resid = ecb->dleft; 1099 xs->status = ecb->stat; 1100 esp_sense(sc, ecb); 1101 return; 1102 } else { 1103 xs->resid = ecb->dleft; 1104 } 1105 } 1106 1107 xs->flags |= ITSDONE; 1108 1109 #ifdef ESP_DEBUG 1110 if (esp_debug & ESP_SHOWMISC) { 1111 if (xs->resid != 0) 1112 printf("resid=%d ", xs->resid); 1113 if (xs->error == XS_SENSE) 1114 printf("sense=0x%02x\n", xs->sense.error_code); 1115 else 1116 printf("error=%d\n", xs->error); 1117 } 1118 #endif 1119 1120 /* 1121 * Remove the ECB from whatever queue it's on. 1122 */ 1123 if (ecb->flags & ECB_NEXUS) 1124 ti->lubusy &= ~(1 << sc_link->lun); 1125 if (ecb == sc->sc_nexus) { 1126 sc->sc_nexus = NULL; 1127 sc->sc_state = ESP_IDLE; 1128 esp_sched(sc); 1129 } else 1130 esp_dequeue(sc, ecb); 1131 1132 esp_free_ecb(sc, ecb, xs->flags); 1133 ti->cmds++; 1134 scsi_done(xs); 1135 } 1136 1137 void 1138 esp_dequeue(sc, ecb) 1139 struct esp_softc *sc; 1140 struct esp_ecb *ecb; 1141 { 1142 1143 if (ecb->flags & ECB_NEXUS) { 1144 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1145 } else { 1146 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1147 } 1148 } 1149 1150 /* 1151 * INTERRUPT/PROTOCOL ENGINE 1152 */ 1153 1154 /* 1155 * Schedule an outgoing message by prioritizing it, and asserting 1156 * attention on the bus. We can only do this when we are the initiator 1157 * else there will be an illegal command interrupt. 1158 */ 1159 #define esp_sched_msgout(m) \ 1160 do { \ 1161 ESP_MISC(("esp_sched_msgout %d ", m)); \ 1162 ESPCMD(sc, ESPCMD_SETATN); \ 1163 sc->sc_flags |= ESP_ATN; \ 1164 sc->sc_msgpriq |= (m); \ 1165 } while (0) 1166 1167 int 1168 esp_reselect(sc, message) 1169 struct esp_softc *sc; 1170 int message; 1171 { 1172 u_char selid, target, lun; 1173 struct esp_ecb *ecb; 1174 struct scsi_link *sc_link; 1175 struct esp_tinfo *ti; 1176 1177 /* 1178 * The SCSI chip made a snapshot of the data bus while the reselection 1179 * was being negotiated. This enables us to determine which target did 1180 * the reselect. 1181 */ 1182 selid = sc->sc_selid & ~(1 << sc->sc_id); 1183 if (selid & (selid - 1)) { 1184 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 1185 sc->sc_dev.dv_xname, selid); 1186 goto reset; 1187 } 1188 1189 /* 1190 * Search wait queue for disconnected cmd 1191 * The list should be short, so I haven't bothered with 1192 * any more sophisticated structures than a simple 1193 * singly linked list. 1194 */ 1195 target = ffs(selid) - 1; 1196 lun = message & 0x07; 1197 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 1198 ecb = ecb->chain.tqe_next) { 1199 sc_link = ecb->xs->sc_link; 1200 if (sc_link->target == target && sc_link->lun == lun) 1201 break; 1202 } 1203 if (ecb == NULL) { 1204 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 1205 sc->sc_dev.dv_xname, target, lun); 1206 goto abort; 1207 } 1208 1209 /* Make this nexus active again. */ 1210 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1211 sc->sc_state = ESP_CONNECTED; 1212 sc->sc_nexus = ecb; 1213 ti = &sc->sc_tinfo[target]; 1214 ti->lubusy |= (1 << lun); 1215 esp_setsync(sc, ti); 1216 1217 if (ecb->flags & ECB_RESET) 1218 esp_sched_msgout(SEND_DEV_RESET); 1219 else if (ecb->flags & ECB_ABORT) 1220 esp_sched_msgout(SEND_ABORT); 1221 1222 /* Do an implicit RESTORE POINTERS. */ 1223 sc->sc_dp = ecb->daddr; 1224 sc->sc_dleft = ecb->dleft; 1225 1226 return (0); 1227 1228 reset: 1229 esp_sched_msgout(SEND_DEV_RESET); 1230 return (1); 1231 1232 abort: 1233 esp_sched_msgout(SEND_ABORT); 1234 return (1); 1235 } 1236 1237 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 1238 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1239 #define ISEXTMSG(m) ((m) == 1) 1240 1241 /* 1242 * Get an incoming message as initiator. 1243 * 1244 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1245 * byte in the FIFO 1246 */ 1247 void 1248 esp_msgin(sc) 1249 register struct esp_softc *sc; 1250 { 1251 register int v; 1252 1253 ESP_TRACE(("[esp_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1254 1255 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) == 0) { 1256 printf("%s: msgin: no msg byte available\n", 1257 sc->sc_dev.dv_xname); 1258 return; 1259 } 1260 1261 /* 1262 * Prepare for a new message. A message should (according 1263 * to the SCSI standard) be transmitted in one single 1264 * MESSAGE_IN_PHASE. If we have been in some other phase, 1265 * then this is a new message. 1266 */ 1267 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1268 sc->sc_flags &= ~ESP_DROP_MSGI; 1269 sc->sc_imlen = 0; 1270 } 1271 1272 v = ESP_READ_REG(sc, ESP_FIFO); 1273 ESP_MISC(("<msgbyte:0x%02x>", v)); 1274 1275 #if 0 1276 if (sc->sc_state == ESP_RESELECTED && sc->sc_imlen == 0) { 1277 /* 1278 * Which target is reselecting us? (The ID bit really) 1279 */ 1280 sc->sc_selid = v; 1281 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1282 return; 1283 } 1284 #endif 1285 1286 sc->sc_imess[sc->sc_imlen] = v; 1287 1288 /* 1289 * If we're going to reject the message, don't bother storing 1290 * the incoming bytes. But still, we need to ACK them. 1291 */ 1292 1293 if ((sc->sc_flags & ESP_DROP_MSGI)) { 1294 ESPCMD(sc, ESPCMD_MSGOK); 1295 printf("<dropping msg byte %x>", 1296 sc->sc_imess[sc->sc_imlen]); 1297 return; 1298 } 1299 1300 if (sc->sc_imlen >= ESP_MAX_MSG_LEN) { 1301 esp_sched_msgout(SEND_REJECT); 1302 sc->sc_flags |= ESP_DROP_MSGI; 1303 } else { 1304 sc->sc_imlen++; 1305 /* 1306 * This testing is suboptimal, but most 1307 * messages will be of the one byte variety, so 1308 * it should not effect performance 1309 * significantly. 1310 */ 1311 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1312 goto gotit; 1313 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1314 goto gotit; 1315 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1316 sc->sc_imlen == sc->sc_imess[1] + 2) 1317 goto gotit; 1318 } 1319 /* Ack what we have so far */ 1320 ESPCMD(sc, ESPCMD_MSGOK); 1321 return; 1322 1323 gotit: 1324 ESP_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1325 /* 1326 * Now we should have a complete message (1 byte, 2 byte 1327 * and moderately long extended messages). We only handle 1328 * extended messages which total length is shorter than 1329 * ESP_MAX_MSG_LEN. Longer messages will be amputated. 1330 */ 1331 switch (sc->sc_state) { 1332 struct esp_ecb *ecb; 1333 struct esp_tinfo *ti; 1334 1335 case ESP_CONNECTED: 1336 ecb = sc->sc_nexus; 1337 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1338 1339 switch (sc->sc_imess[0]) { 1340 case MSG_CMDCOMPLETE: 1341 ESP_MSGS(("cmdcomplete ")); 1342 if (sc->sc_dleft < 0) { 1343 struct scsi_link *sc_link = ecb->xs->sc_link; 1344 printf("%s: %d extra bytes from %d:%d\n", 1345 sc->sc_dev.dv_xname, -sc->sc_dleft, 1346 sc_link->target, sc_link->lun); 1347 sc->sc_dleft = 0; 1348 } 1349 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 1350 sc->sc_state = ESP_CMDCOMPLETE; 1351 break; 1352 1353 case MSG_MESSAGE_REJECT: 1354 if (esp_debug & ESP_SHOWMSGS) 1355 printf("%s: our msg rejected by target\n", 1356 sc->sc_dev.dv_xname); 1357 switch (sc->sc_msgout) { 1358 case SEND_SDTR: 1359 sc->sc_flags &= ~ESP_SYNCHNEGO; 1360 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1361 esp_setsync(sc, ti); 1362 break; 1363 case SEND_INIT_DET_ERR: 1364 goto abort; 1365 } 1366 break; 1367 1368 case MSG_NOOP: 1369 ESP_MSGS(("noop ")); 1370 break; 1371 1372 case MSG_DISCONNECT: 1373 ESP_MSGS(("disconnect ")); 1374 ti->dconns++; 1375 sc->sc_state = ESP_DISCONNECT; 1376 if ((ecb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1377 break; 1378 /*FALLTHROUGH*/ 1379 1380 case MSG_SAVEDATAPOINTER: 1381 ESP_MSGS(("save datapointer ")); 1382 ecb->daddr = sc->sc_dp; 1383 ecb->dleft = sc->sc_dleft; 1384 break; 1385 1386 case MSG_RESTOREPOINTERS: 1387 ESP_MSGS(("restore datapointer ")); 1388 sc->sc_dp = ecb->daddr; 1389 sc->sc_dleft = ecb->dleft; 1390 break; 1391 1392 case MSG_EXTENDED: 1393 ESP_MSGS(("extended(%x) ", sc->sc_imess[2])); 1394 switch (sc->sc_imess[2]) { 1395 case MSG_EXT_SDTR: 1396 ESP_MSGS(("SDTR period %d, offset %d ", 1397 sc->sc_imess[3], sc->sc_imess[4])); 1398 if (sc->sc_imess[1] != 3) 1399 goto reject; 1400 ti->period = sc->sc_imess[3]; 1401 ti->offset = sc->sc_imess[4]; 1402 ti->flags &= ~T_NEGOTIATE; 1403 if (sc->sc_minsync == 0 || 1404 ti->offset == 0 || 1405 ti->period > 124) { 1406 printf("%s:%d: async\n", "esp", 1407 ecb->xs->sc_link->target); 1408 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1409 /* target initiated negotiation */ 1410 ti->offset = 0; 1411 ti->flags &= ~T_SYNCMODE; 1412 esp_sched_msgout(SEND_SDTR); 1413 } else { 1414 /* we are async */ 1415 ti->flags &= ~T_SYNCMODE; 1416 } 1417 } else { 1418 int r = 250/ti->period; 1419 int s = (100*250)/ti->period - 100*r; 1420 int p; 1421 1422 p = esp_stp2cpb(sc, ti->period); 1423 ti->period = esp_cpb2stp(sc, p); 1424 #ifdef ESP_DEBUG 1425 sc_print_addr(ecb->xs->sc_link); 1426 printf("max sync rate %d.%02dMb/s\n", 1427 r, s); 1428 #endif 1429 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1430 /* target initiated negotiation */ 1431 if (ti->period < sc->sc_minsync) 1432 ti->period = sc->sc_minsync; 1433 if (ti->offset > 15) 1434 ti->offset = 15; 1435 ti->flags &= ~T_SYNCMODE; 1436 esp_sched_msgout(SEND_SDTR); 1437 } else { 1438 /* we are sync */ 1439 ti->flags |= T_SYNCMODE; 1440 } 1441 } 1442 sc->sc_flags &= ~ESP_SYNCHNEGO; 1443 esp_setsync(sc, ti); 1444 break; 1445 1446 default: 1447 printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n", 1448 sc->sc_dev.dv_xname); 1449 goto reject; 1450 } 1451 break; 1452 1453 default: 1454 ESP_MSGS(("ident ")); 1455 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1456 sc->sc_dev.dv_xname); 1457 reject: 1458 esp_sched_msgout(SEND_REJECT); 1459 break; 1460 } 1461 break; 1462 1463 case ESP_RESELECTED: 1464 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1465 printf("%s: reselect without IDENTIFY; sending DEVICE RESET\n", 1466 sc->sc_dev.dv_xname); 1467 goto reset; 1468 } 1469 1470 (void) esp_reselect(sc, sc->sc_imess[0]); 1471 break; 1472 1473 default: 1474 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1475 sc->sc_dev.dv_xname); 1476 reset: 1477 esp_sched_msgout(SEND_DEV_RESET); 1478 break; 1479 1480 abort: 1481 esp_sched_msgout(SEND_ABORT); 1482 break; 1483 } 1484 1485 /* Ack last message byte */ 1486 ESPCMD(sc, ESPCMD_MSGOK); 1487 1488 /* Done, reset message pointer. */ 1489 sc->sc_flags &= ~ESP_DROP_MSGI; 1490 sc->sc_imlen = 0; 1491 } 1492 1493 1494 /* 1495 * Send the highest priority, scheduled message 1496 */ 1497 void 1498 esp_msgout(sc) 1499 register struct esp_softc *sc; 1500 { 1501 struct esp_tinfo *ti; 1502 struct esp_ecb *ecb; 1503 size_t size; 1504 1505 ESP_TRACE(("[esp_msgout(priq:%x, prevphase:%x)]", sc->sc_msgpriq, sc->sc_prevphase)); 1506 1507 if (sc->sc_flags & ESP_ATN) { 1508 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1509 new: 1510 ESPCMD(sc, ESPCMD_FLUSH); 1511 DELAY(1); 1512 sc->sc_msgoutq = 0; 1513 sc->sc_omlen = 0; 1514 } 1515 } else { 1516 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1517 esp_sched_msgout(sc->sc_msgoutq); 1518 goto new; 1519 } else { 1520 printf("esp at line %d: unexpected MESSAGE OUT phase\n", __LINE__); 1521 } 1522 } 1523 1524 if (sc->sc_omlen == 0) { 1525 /* Pick up highest priority message */ 1526 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1527 sc->sc_msgoutq |= sc->sc_msgout; 1528 sc->sc_msgpriq &= ~sc->sc_msgout; 1529 sc->sc_omlen = 1; /* "Default" message len */ 1530 switch (sc->sc_msgout) { 1531 case SEND_SDTR: 1532 ecb = sc->sc_nexus; 1533 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1534 sc->sc_omess[0] = MSG_EXTENDED; 1535 sc->sc_omess[1] = 3; 1536 sc->sc_omess[2] = MSG_EXT_SDTR; 1537 sc->sc_omess[3] = ti->period; 1538 sc->sc_omess[4] = ti->offset; 1539 sc->sc_omlen = 5; 1540 if ((sc->sc_flags & ESP_SYNCHNEGO) == 0) { 1541 ti->flags |= T_SYNCMODE; 1542 esp_setsync(sc, ti); 1543 } 1544 break; 1545 case SEND_IDENTIFY: 1546 if (sc->sc_state != ESP_CONNECTED) { 1547 printf("esp at line %d: no nexus\n", __LINE__); 1548 } 1549 ecb = sc->sc_nexus; 1550 sc->sc_omess[0] = MSG_IDENTIFY(ecb->xs->sc_link->lun,0); 1551 break; 1552 case SEND_DEV_RESET: 1553 sc->sc_flags |= ESP_ABORTING; 1554 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1555 ecb = sc->sc_nexus; 1556 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1557 ti->flags &= ~T_SYNCMODE; 1558 ti->flags |= T_NEGOTIATE; 1559 break; 1560 case SEND_PARITY_ERROR: 1561 sc->sc_omess[0] = MSG_PARITY_ERROR; 1562 break; 1563 case SEND_ABORT: 1564 sc->sc_flags |= ESP_ABORTING; 1565 sc->sc_omess[0] = MSG_ABORT; 1566 break; 1567 case SEND_INIT_DET_ERR: 1568 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1569 break; 1570 case SEND_REJECT: 1571 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1572 break; 1573 default: 1574 ESPCMD(sc, ESPCMD_RSTATN); 1575 sc->sc_flags &= ~ESP_ATN; 1576 sc->sc_omess[0] = MSG_NOOP; 1577 break; 1578 } 1579 sc->sc_omp = sc->sc_omess; 1580 } 1581 1582 #if 1 1583 /* (re)send the message */ 1584 size = min(sc->sc_omlen, sc->sc_maxxfer); 1585 DMA_SETUP(sc->sc_dma, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1586 /* Program the SCSI counter */ 1587 ESP_WRITE_REG(sc, ESP_TCL, size); 1588 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 1589 if (sc->sc_cfg2 & ESPCFG2_FE) { 1590 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 1591 } 1592 /* load the count in */ 1593 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 1594 ESPCMD(sc, ESPCMD_TRANS|ESPCMD_DMA); 1595 DMA_GO(sc->sc_dma); 1596 #else 1597 { int i; 1598 for (i = 0; i < sc->sc_omlen; i++) 1599 ESP_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1600 ESPCMD(sc, ESPCMD_TRANS); 1601 sc->sc_omlen = 0; 1602 } 1603 #endif 1604 } 1605 1606 /* 1607 * This is the most critical part of the driver, and has to know 1608 * how to deal with *all* error conditions and phases from the SCSI 1609 * bus. If there are no errors and the DMA was active, then call the 1610 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1611 * and we can return from here without further processing. 1612 * 1613 * Most of this needs verifying. 1614 */ 1615 int 1616 espintr(sc) 1617 register struct esp_softc *sc; 1618 { 1619 register struct esp_ecb *ecb; 1620 register struct scsi_link *sc_link; 1621 struct esp_tinfo *ti; 1622 int loop; 1623 size_t size; 1624 1625 ESP_TRACE(("[espintr]")); 1626 1627 /* 1628 * I have made some (maybe seriously flawed) assumptions here, 1629 * but basic testing (uncomment the printf() below), show that 1630 * certainly something happens when this loop is here. 1631 * 1632 * The idea is that many of the SCSI operations take very little 1633 * time, and going away and getting interrupted is too high an 1634 * overhead to pay. For example, selecting, sending a message 1635 * and command and then doing some work can be done in one "pass". 1636 * 1637 * The DELAY is not variable because I do not understand that the 1638 * DELAY loop should be fixed-time regardless of CPU speed, but 1639 * I am *assuming* that the faster SCSI processors get things done 1640 * quicker (sending a command byte etc), and so there is no 1641 * need to be too slow. 1642 * 1643 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1644 * at 40Mhz. This needs testing. 1645 */ 1646 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1647 /* a feeling of deja-vu */ 1648 if (!DMA_ISINTR(sc->sc_dma)) 1649 return (loop != 0); 1650 #if 0 1651 if (loop) 1652 printf("*"); 1653 #endif 1654 1655 /* and what do the registers say... */ 1656 espreadregs(sc); 1657 1658 sc->sc_intrcnt.ev_count++; 1659 1660 /* 1661 * At the moment, only a SCSI Bus Reset or Illegal 1662 * Command are classed as errors. A disconnect is a 1663 * valid condition, and we let the code check is the 1664 * "ESP_BUSFREE_OK" flag was set before declaring it 1665 * and error. 1666 * 1667 * Also, the status register tells us about "Gross 1668 * Errors" and "Parity errors". Only the Gross Error 1669 * is really bad, and the parity errors are dealt 1670 * with later 1671 * 1672 * TODO 1673 * If there are too many parity error, go to slow 1674 * cable mode ? 1675 */ 1676 1677 /* SCSI Reset */ 1678 if (sc->sc_espintr & ESPINTR_SBR) { 1679 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1680 ESPCMD(sc, ESPCMD_FLUSH); 1681 DELAY(1); 1682 } 1683 if (sc->sc_state != ESP_SBR) { 1684 printf("%s: SCSI bus reset\n", 1685 sc->sc_dev.dv_xname); 1686 esp_init(sc, 0); /* Restart everything */ 1687 return 1; 1688 } 1689 #if 0 1690 /*XXX*/ printf("<expected bus reset: " 1691 "[intr %x, stat %x, step %d]>\n", 1692 sc->sc_espintr, sc->sc_espstat, 1693 sc->sc_espstep); 1694 #endif 1695 if (sc->sc_nexus) 1696 panic("%s: nexus in reset state", 1697 sc->sc_dev.dv_xname); 1698 goto sched; 1699 } 1700 1701 ecb = sc->sc_nexus; 1702 1703 #define ESPINTR_ERR (ESPINTR_SBR|ESPINTR_ILL) 1704 if (sc->sc_espintr & ESPINTR_ERR || 1705 sc->sc_espstat & ESPSTAT_GE) { 1706 1707 if (sc->sc_espstat & ESPSTAT_GE) { 1708 /* no target ? */ 1709 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1710 ESPCMD(sc, ESPCMD_FLUSH); 1711 DELAY(1); 1712 } 1713 if (sc->sc_state == ESP_CONNECTED || 1714 sc->sc_state == ESP_SELECTING) { 1715 ecb->xs->error = XS_DRIVER_STUFFUP; 1716 esp_done(sc, ecb); 1717 } 1718 return 1; 1719 } 1720 1721 if (sc->sc_espintr & ESPINTR_ILL) { 1722 /* illegal command, out of sync ? */ 1723 printf("%s: illegal command: 0x%x (state %d, phase %x, prevphase %x)\n", 1724 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1725 sc->sc_state, sc->sc_phase, 1726 sc->sc_prevphase); 1727 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1728 ESPCMD(sc, ESPCMD_FLUSH); 1729 DELAY(1); 1730 } 1731 esp_init(sc, 0); /* Restart everything */ 1732 return 1; 1733 } 1734 } 1735 1736 /* 1737 * Call if DMA is active. 1738 * 1739 * If DMA_INTR returns true, then maybe go 'round the loop 1740 * again in case there is no more DMA queued, but a phase 1741 * change is expected. 1742 */ 1743 if (DMA_ISACTIVE(sc->sc_dma)) { 1744 DMA_INTR(sc->sc_dma); 1745 /* If DMA active here, then go back to work... */ 1746 if (DMA_ISACTIVE(sc->sc_dma)) 1747 return 1; 1748 1749 if (sc->sc_dleft == 0 && 1750 (sc->sc_espstat & ESPSTAT_TC) == 0) 1751 printf("%s: !TC [intr %x, stat %x, step %d]" 1752 " prevphase %x, resid %x\n", 1753 sc->sc_dev.dv_xname, 1754 sc->sc_espintr, 1755 sc->sc_espstat, 1756 sc->sc_espstep, 1757 sc->sc_prevphase, 1758 ecb?ecb->dleft:-1); 1759 } 1760 1761 #if 0 /* Unreliable on some ESP revisions? */ 1762 if ((sc->sc_espstat & ESPSTAT_INT) == 0) { 1763 printf("%s: spurious interrupt\n", sc->sc_dev.dv_xname); 1764 return 1; 1765 } 1766 #endif 1767 1768 /* 1769 * check for less serious errors 1770 */ 1771 if (sc->sc_espstat & ESPSTAT_PE) { 1772 printf("%s: SCSI bus parity error\n", 1773 sc->sc_dev.dv_xname); 1774 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1775 esp_sched_msgout(SEND_PARITY_ERROR); 1776 else 1777 esp_sched_msgout(SEND_INIT_DET_ERR); 1778 } 1779 1780 if (sc->sc_espintr & ESPINTR_DIS) { 1781 ESP_MISC(("<DISC [intr %x, stat %x, step %d]>", 1782 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1783 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1784 ESPCMD(sc, ESPCMD_FLUSH); 1785 DELAY(1); 1786 } 1787 /* 1788 * This command must (apparently) be issued within 1789 * 250mS of a disconnect. So here you are... 1790 */ 1791 ESPCMD(sc, ESPCMD_ENSEL); 1792 switch (sc->sc_state) { 1793 case ESP_RESELECTED: 1794 goto sched; 1795 1796 case ESP_SELECTING: 1797 ecb->xs->error = XS_SELTIMEOUT; 1798 goto finish; 1799 1800 case ESP_CONNECTED: 1801 if ((sc->sc_flags & ESP_SYNCHNEGO)) { 1802 #ifdef ESP_DEBUG 1803 if (ecb) 1804 sc_print_addr(ecb->xs->sc_link); 1805 printf("sync nego not completed!\n"); 1806 #endif 1807 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1808 sc->sc_flags &= ~ESP_SYNCHNEGO; 1809 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1810 } 1811 1812 /* it may be OK to disconnect */ 1813 if ((sc->sc_flags & ESP_ABORTING) == 0) { 1814 /* 1815 * Section 5.1.1 of the SCSI 2 spec 1816 * suggests issuing a REQUEST SENSE 1817 * following an unexpected disconnect. 1818 * Some devices go into a contingent 1819 * allegiance condition when 1820 * disconnecting, and this is necessary 1821 * to clean up their state. 1822 */ 1823 printf("%s: unexpected disconnect; ", 1824 sc->sc_dev.dv_xname); 1825 if (ecb->flags & ECB_SENSE) { 1826 printf("resetting\n"); 1827 goto reset; 1828 } 1829 printf("sending REQUEST SENSE\n"); 1830 esp_sense(sc, ecb); 1831 goto out; 1832 } 1833 1834 ecb->xs->error = XS_DRIVER_STUFFUP; 1835 goto finish; 1836 1837 case ESP_DISCONNECT: 1838 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1839 sc->sc_nexus = NULL; 1840 goto sched; 1841 1842 case ESP_CMDCOMPLETE: 1843 goto finish; 1844 } 1845 } 1846 1847 switch (sc->sc_state) { 1848 1849 case ESP_SBR: 1850 printf("%s: waiting for SCSI Bus Reset to happen\n", 1851 sc->sc_dev.dv_xname); 1852 return 1; 1853 1854 case ESP_RESELECTED: 1855 /* 1856 * we must be continuing a message ? 1857 */ 1858 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1859 printf("%s: target didn't identify\n", 1860 sc->sc_dev.dv_xname); 1861 esp_init(sc, 1); 1862 return 1; 1863 } 1864 printf("<<RESELECT CONT'd>>"); 1865 #if XXXX 1866 esp_msgin(sc); 1867 if (sc->sc_state != ESP_CONNECTED) { 1868 /* IDENTIFY fail?! */ 1869 printf("%s: identify failed\n", 1870 sc->sc_dev.dv_xname); 1871 esp_init(sc, 1); 1872 return 1; 1873 } 1874 #endif 1875 break; 1876 1877 case ESP_IDLE: 1878 if (sc->sc_flags & ESP_ICCS) printf("[[esp: BUMMER]]"); 1879 case ESP_SELECTING: 1880 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1881 sc->sc_flags = 0; 1882 1883 if (sc->sc_espintr & ESPINTR_RESEL) { 1884 /* 1885 * If we're trying to select a 1886 * target ourselves, push our command 1887 * back into the ready list. 1888 */ 1889 if (sc->sc_state == ESP_SELECTING) { 1890 ESP_MISC(("backoff selector ")); 1891 sc_link = sc->sc_nexus->xs->sc_link; 1892 ti = &sc->sc_tinfo[sc_link->target]; 1893 TAILQ_INSERT_HEAD(&sc->ready_list, 1894 sc->sc_nexus, chain); 1895 ecb = sc->sc_nexus = NULL; 1896 } 1897 sc->sc_state = ESP_RESELECTED; 1898 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1899 /* 1900 * Things are seriously fucked up. 1901 * Pull the brakes, i.e. reset 1902 */ 1903 printf("%s: target didn't identify\n", 1904 sc->sc_dev.dv_xname); 1905 esp_init(sc, 1); 1906 return 1; 1907 } 1908 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 1909 printf("%s: RESELECT: %d bytes in FIFO!\n", 1910 sc->sc_dev.dv_xname, 1911 ESP_READ_REG(sc, ESP_FFLAG) & 1912 ESPFIFO_FF); 1913 esp_init(sc, 1); 1914 return 1; 1915 } 1916 sc->sc_selid = ESP_READ_REG(sc, ESP_FIFO); 1917 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1918 esp_msgin(sc); /* Handle identify message */ 1919 if (sc->sc_state != ESP_CONNECTED) { 1920 /* IDENTIFY fail?! */ 1921 printf("%s: identify failed\n", 1922 sc->sc_dev.dv_xname); 1923 esp_init(sc, 1); 1924 return 1; 1925 } 1926 continue; /* ie. next phase expected soon */ 1927 } 1928 1929 #define ESPINTR_DONE (ESPINTR_FC|ESPINTR_BS) 1930 if ((sc->sc_espintr & ESPINTR_DONE) == ESPINTR_DONE) { 1931 ecb = sc->sc_nexus; 1932 if (!ecb) 1933 panic("esp: not nexus at sc->sc_nexus"); 1934 1935 sc_link = ecb->xs->sc_link; 1936 ti = &sc->sc_tinfo[sc_link->target]; 1937 1938 switch (sc->sc_espstep) { 1939 case 0: 1940 printf("%s: select timeout/no disconnect\n", 1941 sc->sc_dev.dv_xname); 1942 ecb->xs->error = XS_SELTIMEOUT; 1943 goto finish; 1944 case 1: 1945 if ((ti->flags & T_NEGOTIATE) == 0) { 1946 printf("%s: step 1 & !NEG\n", 1947 sc->sc_dev.dv_xname); 1948 goto reset; 1949 } 1950 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1951 printf("%s: !MSGOUT\n", 1952 sc->sc_dev.dv_xname); 1953 goto reset; 1954 } 1955 /* Start negotiating */ 1956 ti->period = sc->sc_minsync; 1957 ti->offset = 15; 1958 sc->sc_flags |= ESP_SYNCHNEGO; 1959 esp_sched_msgout(SEND_SDTR); 1960 break; 1961 case 3: 1962 /* 1963 * Grr, this is supposed to mean 1964 * "target left command phase 1965 * prematurely". It seems to happen 1966 * regularly when sync mode is on. 1967 * Look at FIFO to see if command 1968 * went out. 1969 * (Timing problems?) 1970 */ 1971 if ((ESP_READ_REG(sc, ESP_FFLAG)&ESPFIFO_FF) == 0) { 1972 /* Hope for the best.. */ 1973 break; 1974 } 1975 printf("(%s:%d:%d): selection failed;" 1976 " %d left in FIFO " 1977 "[intr %x, stat %x, step %d]\n", 1978 sc->sc_dev.dv_xname, 1979 sc_link->target, 1980 sc_link->lun, 1981 ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF, 1982 sc->sc_espintr, sc->sc_espstat, 1983 sc->sc_espstep); 1984 ESPCMD(sc, ESPCMD_FLUSH); 1985 esp_sched_msgout(SEND_ABORT); 1986 return 1; 1987 case 2: 1988 /* Select stuck at Command Phase */ 1989 ESPCMD(sc, ESPCMD_FLUSH); 1990 case 4: 1991 /* So far, everything went fine */ 1992 break; 1993 } 1994 #if 0 1995 if (ecb->xs->flags & SCSI_RESET) 1996 esp_sched_msgout(SEND_DEV_RESET); 1997 else if (ti->flags & T_NEGOTIATE) 1998 esp_sched_msgout( 1999 SEND_IDENTIFY | SEND_SDTR); 2000 else 2001 esp_sched_msgout(SEND_IDENTIFY); 2002 #endif 2003 2004 ecb->flags |= ECB_NEXUS; 2005 ti->lubusy |= (1 << sc_link->lun); 2006 2007 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 2008 /* Do an implicit RESTORE POINTERS. */ 2009 sc->sc_dp = ecb->daddr; 2010 sc->sc_dleft = ecb->dleft; 2011 2012 /* On our first connection, schedule a timeout. */ 2013 if ((ecb->xs->flags & SCSI_POLL) == 0) 2014 timeout(esp_timeout, ecb, (ecb->timeout * hz) / 1000); 2015 2016 sc->sc_state = ESP_CONNECTED; 2017 break; 2018 } else { 2019 printf("%s: unexpected status after select" 2020 ": [intr %x, stat %x, step %x]\n", 2021 sc->sc_dev.dv_xname, 2022 sc->sc_espintr, sc->sc_espstat, 2023 sc->sc_espstep); 2024 ESPCMD(sc, ESPCMD_FLUSH); 2025 DELAY(1); 2026 goto reset; 2027 } 2028 if (sc->sc_state == ESP_IDLE) { 2029 printf("%s: stray interrupt\n", sc->sc_dev.dv_xname); 2030 return 0; 2031 } 2032 break; 2033 2034 case ESP_CONNECTED: 2035 if (sc->sc_flags & ESP_ICCS) { 2036 u_char msg; 2037 2038 sc->sc_flags &= ~ESP_ICCS; 2039 2040 if (!(sc->sc_espintr & ESPINTR_DONE)) { 2041 printf("%s: ICCS: " 2042 ": [intr %x, stat %x, step %x]\n", 2043 sc->sc_dev.dv_xname, 2044 sc->sc_espintr, sc->sc_espstat, 2045 sc->sc_espstep); 2046 } 2047 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 2048 int i = (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) - 2; 2049 while (i--) 2050 (void) ESP_READ_REG(sc, ESP_FIFO); 2051 } 2052 ecb->stat = ESP_READ_REG(sc, ESP_FIFO); 2053 msg = ESP_READ_REG(sc, ESP_FIFO); 2054 ESP_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 2055 if (msg == MSG_CMDCOMPLETE) { 2056 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 2057 sc->sc_state = ESP_CMDCOMPLETE; 2058 } else 2059 printf("%s: STATUS_PHASE: msg %d\n", 2060 sc->sc_dev.dv_xname, msg); 2061 ESPCMD(sc, ESPCMD_MSGOK); 2062 continue; /* ie. wait for disconnect */ 2063 } 2064 break; 2065 default: 2066 panic("%s: invalid state: %d", 2067 sc->sc_dev.dv_xname, 2068 sc->sc_state); 2069 } 2070 2071 /* 2072 * Driver is now in state ESP_CONNECTED, i.e. we 2073 * have a current command working the SCSI bus. 2074 */ 2075 if (sc->sc_state != ESP_CONNECTED || ecb == NULL) { 2076 panic("esp no nexus"); 2077 } 2078 2079 switch (sc->sc_phase) { 2080 case MESSAGE_OUT_PHASE: 2081 ESP_PHASE(("MESSAGE_OUT_PHASE ")); 2082 esp_msgout(sc); 2083 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2084 break; 2085 case MESSAGE_IN_PHASE: 2086 ESP_PHASE(("MESSAGE_IN_PHASE ")); 2087 if (sc->sc_espintr & ESPINTR_BS) { 2088 ESPCMD(sc, ESPCMD_FLUSH); 2089 sc->sc_flags |= ESP_WAITI; 2090 ESPCMD(sc, ESPCMD_TRANS); 2091 } else if (sc->sc_espintr & ESPINTR_FC) { 2092 if ((sc->sc_flags & ESP_WAITI) == 0) { 2093 printf("%s: MSGIN: unexpected FC bit: " 2094 "[intr %x, stat %x, step %x]\n", 2095 sc->sc_dev.dv_xname, 2096 sc->sc_espintr, sc->sc_espstat, 2097 sc->sc_espstep); 2098 } 2099 sc->sc_flags &= ~ESP_WAITI; 2100 esp_msgin(sc); 2101 } else { 2102 printf("%s: MSGIN: weird bits: " 2103 "[intr %x, stat %x, step %x]\n", 2104 sc->sc_dev.dv_xname, 2105 sc->sc_espintr, sc->sc_espstat, 2106 sc->sc_espstep); 2107 } 2108 sc->sc_prevphase = MESSAGE_IN_PHASE; 2109 break; 2110 case COMMAND_PHASE: { 2111 /* well, this means send the command again */ 2112 u_char *cmd = (u_char *)&ecb->cmd; 2113 int i; 2114 2115 ESP_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2116 ecb->cmd.opcode, ecb->clen)); 2117 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 2118 ESPCMD(sc, ESPCMD_FLUSH); 2119 DELAY(1); 2120 } 2121 /* Now the command into the FIFO */ 2122 for (i = 0; i < ecb->clen; i++) 2123 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 2124 ESPCMD(sc, ESPCMD_TRANS); 2125 sc->sc_prevphase = COMMAND_PHASE; 2126 } 2127 break; 2128 case DATA_OUT_PHASE: 2129 ESP_PHASE(("DATA_OUT_PHASE [%d] ", sc->sc_dleft)); 2130 ESPCMD(sc, ESPCMD_FLUSH); 2131 size = min(sc->sc_dleft, sc->sc_maxxfer); 2132 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2133 0, &size); 2134 sc->sc_prevphase = DATA_OUT_PHASE; 2135 goto setup_xfer; 2136 case DATA_IN_PHASE: 2137 ESP_PHASE(("DATA_IN_PHASE ")); 2138 if (sc->sc_rev == ESP100) 2139 ESPCMD(sc, ESPCMD_FLUSH); 2140 size = min(sc->sc_dleft, sc->sc_maxxfer); 2141 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2142 1, &size); 2143 sc->sc_prevphase = DATA_IN_PHASE; 2144 setup_xfer: 2145 /* Program the SCSI counter */ 2146 ESP_WRITE_REG(sc, ESP_TCL, size); 2147 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 2148 if (sc->sc_cfg2 & ESPCFG2_FE) { 2149 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 2150 } 2151 /* load the count in */ 2152 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 2153 2154 /* 2155 * Note that if `size' is 0, we've already transceived 2156 * all the bytes we want but we're still in DATA PHASE. 2157 * Apparently, the device needs padding. Also, a 2158 * transfer size of 0 means "maximum" to the chip 2159 * DMA logic. 2160 */ 2161 ESPCMD(sc, 2162 (size==0?ESPCMD_TRPAD:ESPCMD_TRANS)|ESPCMD_DMA); 2163 DMA_GO(sc->sc_dma); 2164 return 1; 2165 case STATUS_PHASE: 2166 ESP_PHASE(("STATUS_PHASE ")); 2167 sc->sc_flags |= ESP_ICCS; 2168 ESPCMD(sc, ESPCMD_ICCS); 2169 sc->sc_prevphase = STATUS_PHASE; 2170 break; 2171 case INVALID_PHASE: 2172 break; 2173 default: 2174 printf("%s: unexpected bus phase; resetting\n", 2175 sc->sc_dev.dv_xname); 2176 goto reset; 2177 } 2178 } 2179 panic("esp: should not get here.."); 2180 2181 reset: 2182 esp_init(sc, 1); 2183 return 1; 2184 2185 finish: 2186 untimeout(esp_timeout, ecb); 2187 esp_done(sc, ecb); 2188 goto out; 2189 2190 sched: 2191 sc->sc_state = ESP_IDLE; 2192 esp_sched(sc); 2193 goto out; 2194 2195 out: 2196 return 1; 2197 } 2198 2199 void 2200 esp_abort(sc, ecb) 2201 struct esp_softc *sc; 2202 struct esp_ecb *ecb; 2203 { 2204 2205 /* 2 secs for the abort */ 2206 ecb->timeout = ESP_ABORT_TIMEOUT; 2207 ecb->flags |= ECB_ABORT; 2208 2209 if (ecb == sc->sc_nexus) { 2210 /* 2211 * If we're still selecting, the message will be scheduled 2212 * after selection is complete. 2213 */ 2214 if (sc->sc_state == ESP_CONNECTED) 2215 esp_sched_msgout(SEND_ABORT); 2216 } else { 2217 esp_dequeue(sc, ecb); 2218 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2219 if (sc->sc_state == ESP_IDLE) 2220 esp_sched(sc); 2221 } 2222 } 2223 2224 void 2225 esp_timeout(arg) 2226 void *arg; 2227 { 2228 struct esp_ecb *ecb = arg; 2229 struct scsi_xfer *xs = ecb->xs; 2230 struct scsi_link *sc_link = xs->sc_link; 2231 struct esp_softc *sc = sc_link->adapter_softc; 2232 int s; 2233 2234 sc_print_addr(sc_link); 2235 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2236 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) %s>", 2237 sc->sc_dev.dv_xname, 2238 ecb, ecb->flags, ecb->dleft, ecb->stat, 2239 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2240 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2241 DMA_ISACTIVE(sc->sc_dma) ? "DMA active" : ""); 2242 #if ESP_DEBUG > 0 2243 printf("TRACE: %s.", ecb->trace); 2244 #endif 2245 2246 s = splbio(); 2247 2248 if (ecb->flags & ECB_ABORT) { 2249 /* abort timed out */ 2250 printf(" AGAIN\n"); 2251 esp_init(sc, 1); 2252 } else { 2253 /* abort the operation that has timed out */ 2254 printf("\n"); 2255 xs->error = XS_TIMEOUT; 2256 esp_abort(sc, ecb); 2257 } 2258 2259 splx(s); 2260 } 2261
Indexes created Wed Oct 22 06:10:02 GMT 2025