esp.c revision 1.20
1 /* $NetBSD: esp.c,v 1.20 1998/12/22 08:47:07 scottr Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Jason R. Thorpe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project 18 * by Jason R. Thorpe. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1994 Peter Galbavy 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Peter Galbavy 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 54 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 55 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 56 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 57 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 58 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 60 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 61 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Based on aic6360 by Jarle Greipsland 67 * 68 * Acknowledgements: Many of the algorithms used in this driver are 69 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 70 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 71 */ 72 73 /* 74 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 75 * (basically consisting of the match, a bit of the attach, and the 76 * "DMA" glue functions). 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/errno.h> 84 #include <sys/ioctl.h> 85 #include <sys/device.h> 86 #include <sys/buf.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/queue.h> 90 91 #include <dev/scsipi/scsi_all.h> 92 #include <dev/scsipi/scsipi_all.h> 93 #include <dev/scsipi/scsiconf.h> 94 #include <dev/scsipi/scsi_message.h> 95 96 #include <machine/cpu.h> 97 #include <machine/bus.h> 98 #include <machine/param.h> 99 100 #include <dev/ic/ncr53c9xreg.h> 101 #include <dev/ic/ncr53c9xvar.h> 102 103 #include <machine/viareg.h> 104 105 #include <mac68k/obio/espvar.h> 106 #include <mac68k/obio/obiovar.h> 107 108 void espattach __P((struct device *, struct device *, void *)); 109 int espmatch __P((struct device *, struct cfdata *, void *)); 110 111 /* Linkup to the rest of the kernel */ 112 struct cfattach esp_ca = { 113 sizeof(struct esp_softc), espmatch, espattach 114 }; 115 116 struct scsipi_device esp_dev = { 117 NULL, /* Use default error handler */ 118 NULL, /* have a queue, served by this */ 119 NULL, /* have no async handler */ 120 NULL, /* Use default 'done' routine */ 121 }; 122 123 /* 124 * Functions and the switch for the MI code. 125 */ 126 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 127 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 128 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 129 void esp_dma_reset __P((struct ncr53c9x_softc *)); 130 int esp_dma_intr __P((struct ncr53c9x_softc *)); 131 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 132 size_t *, int, size_t *)); 133 void esp_dma_go __P((struct ncr53c9x_softc *)); 134 void esp_dma_stop __P((struct ncr53c9x_softc *)); 135 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 136 void esp_quick_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 137 int esp_quick_dma_intr __P((struct ncr53c9x_softc *)); 138 int esp_quick_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 139 size_t *, int, size_t *)); 140 void esp_quick_dma_go __P((struct ncr53c9x_softc *)); 141 142 int esp_dualbus_intr __P((register struct ncr53c9x_softc *sc)); 143 static struct esp_softc *esp0 = NULL, *esp1 = NULL; 144 145 static __inline__ int esp_dafb_have_dreq __P((struct esp_softc *esc)); 146 static __inline__ int esp_iosb_have_dreq __P((struct esp_softc *esc)); 147 int (*esp_have_dreq) __P((struct esp_softc *esc)); 148 149 struct ncr53c9x_glue esp_glue = { 150 esp_read_reg, 151 esp_write_reg, 152 esp_dma_isintr, 153 esp_dma_reset, 154 esp_dma_intr, 155 esp_dma_setup, 156 esp_dma_go, 157 esp_dma_stop, 158 esp_dma_isactive, 159 NULL, /* gl_clear_latched_intr */ 160 }; 161 162 int 163 espmatch(parent, cf, aux) 164 struct device *parent; 165 struct cfdata *cf; 166 void *aux; 167 { 168 int found = 0; 169 170 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) { 171 found = 1; 172 } 173 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) { 174 found = 1; 175 } 176 177 return found; 178 } 179 180 /* 181 * Attach this instance, and then all the sub-devices 182 */ 183 void 184 espattach(parent, self, aux) 185 struct device *parent, *self; 186 void *aux; 187 { 188 struct obio_attach_args *oa = (struct obio_attach_args *)aux; 189 extern vaddr_t SCSIBase; 190 struct esp_softc *esc = (void *)self; 191 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 192 int quick = 0; 193 unsigned long reg_offset; 194 195 reg_offset = SCSIBase - IOBase; 196 esc->sc_tag = oa->oa_tag; 197 /* 198 * For Wombat, Primus and Optimus motherboards, DREQ is 199 * visible on bit 0 of the IOSB's emulated VIA2 vIFR (and 200 * the scsi registers are offset 0x1000 bytes from IOBase). 201 * 202 * For the Q700/900/950 it's at f9800024 for bus 0 and 203 * f9800028 for bus 1 (900/950). For these machines, that is also 204 * a (12-bit) configuration register for DAFB's control of the 205 * pseudo-DMA timing. The default value is 0x1d1. 206 */ 207 esp_have_dreq = esp_dafb_have_dreq; 208 if (sc->sc_dev.dv_unit == 0) { 209 if (reg_offset == 0x10000) { 210 quick = 1; 211 esp_have_dreq = esp_iosb_have_dreq; 212 } else if (reg_offset == 0x18000) { 213 quick = 0; 214 } else { 215 if (bus_space_map(esc->sc_tag, 0xf9800024, 216 4, 0, &esc->sc_bsh)) { 217 printf("failed to map 4 at 0xf9800024.\n"); 218 } else { 219 quick = 1; 220 bus_space_write_4(esc->sc_tag, 221 esc->sc_bsh, 0, 0x1d1); 222 } 223 } 224 } else { 225 if (bus_space_map(esc->sc_tag, 0xf9800028, 226 4, 0, &esc->sc_bsh)) { 227 printf("failed to map 4 at 0xf9800028.\n"); 228 } else { 229 quick = 1; 230 bus_space_write_4(esc->sc_tag, esc->sc_bsh, 0, 0x1d1); 231 } 232 } 233 if (quick) { 234 esp_glue.gl_write_reg = esp_quick_write_reg; 235 esp_glue.gl_dma_intr = esp_quick_dma_intr; 236 esp_glue.gl_dma_setup = esp_quick_dma_setup; 237 esp_glue.gl_dma_go = esp_quick_dma_go; 238 } 239 240 /* 241 * Set up the glue for MI code early; we use some of it here. 242 */ 243 sc->sc_glue = &esp_glue; 244 245 /* 246 * Save the regs 247 */ 248 if (sc->sc_dev.dv_unit == 0) { 249 esp0 = esc; 250 251 esc->sc_reg = (volatile u_char *) SCSIBase; 252 via2_register_irq(VIA2_SCSIIRQ, 253 (void (*)(void *))ncr53c9x_intr, esc); 254 esc->irq_mask = V2IF_SCSIIRQ; 255 if (reg_offset == 0x10000) { 256 sc->sc_freq = 16500000; 257 } else { 258 sc->sc_freq = 25000000; 259 } 260 261 if (esp_glue.gl_dma_go == esp_quick_dma_go) { 262 printf(" (quick)"); 263 } 264 } else { 265 esp1 = esc; 266 267 esc->sc_reg = (volatile u_char *) SCSIBase + 0x402; 268 via2_register_irq(VIA2_SCSIIRQ, 269 (void (*)(void *))esp_dualbus_intr, NULL); 270 esc->irq_mask = 0; 271 sc->sc_freq = 25000000; 272 273 if (esp_glue.gl_dma_go == esp_quick_dma_go) { 274 printf(" (quick)"); 275 } 276 } 277 278 printf(": address %p", esc->sc_reg); 279 280 sc->sc_id = 7; 281 282 /* gimme Mhz */ 283 sc->sc_freq /= 1000000; 284 285 /* 286 * It is necessary to try to load the 2nd config register here, 287 * to find out what rev the esp chip is, else the esp_reset 288 * will not set up the defaults correctly. 289 */ 290 sc->sc_cfg1 = sc->sc_id; /* | NCRCFG1_PARENB; */ 291 sc->sc_cfg2 = NCRCFG2_SCSI2; 292 sc->sc_cfg3 = 0; 293 sc->sc_rev = NCR_VARIANT_NCR53C96; 294 295 /* 296 * This is the value used to start sync negotiations 297 * Note that the NCR register "SYNCTP" is programmed 298 * in "clocks per byte", and has a minimum value of 4. 299 * The SCSI period used in negotiation is one-fourth 300 * of the time (in nanoseconds) needed to transfer one byte. 301 * Since the chip's clock is given in MHz, we have the following 302 * formula: 4 * period = (1000 / freq) * 4 303 */ 304 sc->sc_minsync = 1000 / sc->sc_freq; 305 306 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */ 307 /* Really no limit, but since we want to fit into the TCR... */ 308 sc->sc_maxxfer = 8 * 1024; /*64 * 1024; XXX */ 309 310 /* 311 * Now try to attach all the sub-devices 312 */ 313 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 314 sc->sc_adapter.scsipi_minphys = minphys; 315 ncr53c9x_attach(sc, &esp_dev); 316 317 /* 318 * Configure interrupts. 319 */ 320 if (esc->irq_mask) { 321 via2_reg(vPCR) = 0x22; 322 via2_reg(vIFR) = esc->irq_mask; 323 via2_reg(vIER) = 0x80 | esc->irq_mask; 324 } 325 } 326 327 /* 328 * Glue functions. 329 */ 330 331 u_char 332 esp_read_reg(sc, reg) 333 struct ncr53c9x_softc *sc; 334 int reg; 335 { 336 struct esp_softc *esc = (struct esp_softc *)sc; 337 338 return esc->sc_reg[reg * 16]; 339 } 340 341 void 342 esp_write_reg(sc, reg, val) 343 struct ncr53c9x_softc *sc; 344 int reg; 345 u_char val; 346 { 347 struct esp_softc *esc = (struct esp_softc *)sc; 348 u_char v = val; 349 350 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 351 v = NCRCMD_TRANS; 352 } 353 esc->sc_reg[reg * 16] = v; 354 } 355 356 void 357 esp_dma_stop(sc) 358 struct ncr53c9x_softc *sc; 359 { 360 } 361 362 int 363 esp_dma_isactive(sc) 364 struct ncr53c9x_softc *sc; 365 { 366 struct esp_softc *esc = (struct esp_softc *)sc; 367 368 return esc->sc_active; 369 } 370 371 int 372 esp_dma_isintr(sc) 373 struct ncr53c9x_softc *sc; 374 { 375 struct esp_softc *esc = (struct esp_softc *)sc; 376 377 return esc->sc_reg[NCR_STAT * 16] & 0x80; 378 } 379 380 void 381 esp_dma_reset(sc) 382 struct ncr53c9x_softc *sc; 383 { 384 struct esp_softc *esc = (struct esp_softc *)sc; 385 386 esc->sc_active = 0; 387 esc->sc_tc = 0; 388 } 389 390 int 391 esp_dma_intr(sc) 392 struct ncr53c9x_softc *sc; 393 { 394 register struct esp_softc *esc = (struct esp_softc *)sc; 395 register u_char *p; 396 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 397 register u_int espphase, espstat, espintr; 398 register int cnt; 399 400 if (esc->sc_active == 0) { 401 printf("dma_intr--inactive DMA\n"); 402 return -1; 403 } 404 405 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 406 esc->sc_active = 0; 407 return 0; 408 } 409 410 cnt = *esc->sc_dmalen; 411 if (*esc->sc_dmalen == 0) { 412 printf("data interrupt, but no count left."); 413 } 414 415 p = *esc->sc_dmaaddr; 416 espphase = sc->sc_phase; 417 espstat = (u_int) sc->sc_espstat; 418 espintr = (u_int) sc->sc_espintr; 419 cmdreg = esc->sc_reg + NCR_CMD * 16; 420 fiforeg = esc->sc_reg + NCR_FIFO * 16; 421 statreg = esc->sc_reg + NCR_STAT * 16; 422 intrreg = esc->sc_reg + NCR_INTR * 16; 423 do { 424 if (esc->sc_datain) { 425 *p++ = *fiforeg; 426 cnt--; 427 if (espphase == DATA_IN_PHASE) { 428 *cmdreg = NCRCMD_TRANS; 429 } else { 430 esc->sc_active = 0; 431 } 432 } else { 433 if ( (espphase == DATA_OUT_PHASE) 434 || (espphase == MESSAGE_OUT_PHASE)) { 435 *fiforeg = *p++; 436 cnt--; 437 *cmdreg = NCRCMD_TRANS; 438 } else { 439 esc->sc_active = 0; 440 } 441 } 442 443 if (esc->sc_active) { 444 while (!(*statreg & 0x80)); 445 espstat = *statreg; 446 espintr = *intrreg; 447 espphase = (espintr & NCRINTR_DIS) 448 ? /* Disconnected */ BUSFREE_PHASE 449 : espstat & PHASE_MASK; 450 } 451 } while (esc->sc_active && (espintr & NCRINTR_BS)); 452 sc->sc_phase = espphase; 453 sc->sc_espstat = (u_char) espstat; 454 sc->sc_espintr = (u_char) espintr; 455 *esc->sc_dmaaddr = p; 456 *esc->sc_dmalen = cnt; 457 458 if (*esc->sc_dmalen == 0) { 459 esc->sc_tc = NCRSTAT_TC; 460 } 461 sc->sc_espstat |= esc->sc_tc; 462 return 0; 463 } 464 465 int 466 esp_dma_setup(sc, addr, len, datain, dmasize) 467 struct ncr53c9x_softc *sc; 468 caddr_t *addr; 469 size_t *len; 470 int datain; 471 size_t *dmasize; 472 { 473 struct esp_softc *esc = (struct esp_softc *)sc; 474 475 esc->sc_dmaaddr = addr; 476 esc->sc_dmalen = len; 477 esc->sc_datain = datain; 478 esc->sc_dmasize = *dmasize; 479 esc->sc_tc = 0; 480 481 return 0; 482 } 483 484 void 485 esp_dma_go(sc) 486 struct ncr53c9x_softc *sc; 487 { 488 struct esp_softc *esc = (struct esp_softc *)sc; 489 490 if (esc->sc_datain == 0) { 491 esc->sc_reg[NCR_FIFO * 16] = **esc->sc_dmaaddr; 492 (*esc->sc_dmalen)--; 493 (*esc->sc_dmaaddr)++; 494 } 495 esc->sc_active = 1; 496 } 497 498 void 499 esp_quick_write_reg(sc, reg, val) 500 struct ncr53c9x_softc *sc; 501 int reg; 502 u_char val; 503 { 504 struct esp_softc *esc = (struct esp_softc *)sc; 505 u_char v = val; 506 507 esc->sc_reg[reg * 16] = v; 508 } 509 510 int 511 esp_quick_dma_intr(sc) 512 struct ncr53c9x_softc *sc; 513 { 514 struct esp_softc *esc = (struct esp_softc *)sc; 515 int trans=0, resid=0; 516 517 if (esc->sc_active == 0) 518 panic("dma_intr--inactive DMA\n"); 519 520 esc->sc_active = 0; 521 522 if (esc->sc_dmasize == 0) { 523 int res; 524 525 res = 65536; 526 res -= NCR_READ_REG(sc, NCR_TCL); 527 res -= NCR_READ_REG(sc, NCR_TCM) << 8; 528 printf("dmaintr: discarded %d b (last transfer was %d b).\n", 529 res, esc->sc_prevdmasize); 530 return 0; 531 } 532 533 if (esc->sc_datain && 534 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 535 printf("dmaintr: empty FIFO of %d\n", resid); 536 DELAY(1); 537 } 538 539 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 540 resid += NCR_READ_REG(sc, NCR_TCL); 541 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 542 543 if (resid == 0) 544 resid = 65536; 545 } 546 547 trans = esc->sc_dmasize - resid; 548 if (trans < 0) { 549 printf("dmaintr: trans < 0????"); 550 trans = esc->sc_dmasize; 551 } 552 553 NCR_DMA(("dmaintr: trans %d, resid %d.\n", trans, resid)); 554 *esc->sc_dmaaddr += trans; 555 *esc->sc_dmalen -= trans; 556 557 return 0; 558 } 559 560 int 561 esp_quick_dma_setup(sc, addr, len, datain, dmasize) 562 struct ncr53c9x_softc *sc; 563 caddr_t *addr; 564 size_t *len; 565 int datain; 566 size_t *dmasize; 567 { 568 struct esp_softc *esc = (struct esp_softc *)sc; 569 570 esc->sc_dmaaddr = addr; 571 esc->sc_dmalen = len; 572 573 esc->sc_pdmaddr = (u_int16_t *) *addr; 574 esc->sc_pdmalen = *len; 575 if (esc->sc_pdmalen & 1) { 576 esc->sc_pdmalen--; 577 esc->sc_pad = 1; 578 } else { 579 esc->sc_pad = 0; 580 } 581 582 esc->sc_datain = datain; 583 esc->sc_prevdmasize = esc->sc_dmasize; 584 esc->sc_dmasize = *dmasize; 585 586 return 0; 587 } 588 589 static __inline__ int 590 esp_dafb_have_dreq(esc) 591 struct esp_softc *esc; 592 { 593 u_int32_t r; 594 595 r = bus_space_read_4(esc->sc_tag, esc->sc_bsh, 0); 596 return (r & 0x200); 597 } 598 599 static __inline__ int 600 esp_iosb_have_dreq(esc) 601 struct esp_softc *esc; 602 { 603 return (via2_reg(vIFR) & V2IF_SCSIDRQ); 604 } 605 606 static int espspl=-1; 607 #define __splx(s) __asm __volatile ("movew %0,sr" : : "di" (s)); 608 #define __spl2() __splx(PSL_S|PSL_IPL2) 609 #define __spl4() __splx(PSL_S|PSL_IPL4) 610 611 void 612 esp_quick_dma_go(sc) 613 struct ncr53c9x_softc *sc; 614 { 615 struct esp_softc *esc = (struct esp_softc *)sc; 616 extern int *nofault; 617 label_t faultbuf; 618 u_int16_t volatile *pdma; 619 u_char volatile *statreg; 620 621 esc->sc_active = 1; 622 623 espspl = spl2(); 624 625 restart_dmago: 626 nofault = (int *) &faultbuf; 627 if (setjmp((label_t *) nofault)) { 628 int i=0; 629 630 nofault = (int *) 0; 631 statreg = esc->sc_reg + NCR_STAT * 16; 632 for (;;) { 633 if (*statreg & 0x80) { 634 goto gotintr; 635 } 636 637 if (esp_have_dreq(esc)) { 638 break; 639 } 640 641 DELAY(1); 642 if (i++ > 10000) 643 panic("esp_dma_go: Argh!"); 644 } 645 goto restart_dmago; 646 } 647 648 statreg = esc->sc_reg + NCR_STAT * 16; 649 pdma = (u_int16_t *) (esc->sc_reg + 0x100); 650 651 #define WAIT while (!esp_have_dreq(esc)) if (*statreg & 0x80) goto gotintr 652 653 if (esc->sc_datain == 0) { 654 while (esc->sc_pdmalen) { 655 WAIT; 656 __spl4(); *pdma = *(esc->sc_pdmaddr)++; __spl2() 657 esc->sc_pdmalen -= 2; 658 } 659 if (esc->sc_pad) { 660 unsigned short us; 661 unsigned char *c; 662 c = (unsigned char *) esc->sc_pdmaddr; 663 us = *c; 664 WAIT; 665 __spl4(); *pdma = us; __spl2() 666 } 667 } else { 668 while (esc->sc_pdmalen) { 669 WAIT; 670 __spl4(); *(esc->sc_pdmaddr)++ = *pdma; __spl2() 671 esc->sc_pdmalen -= 2; 672 } 673 if (esc->sc_pad) { 674 unsigned short us; 675 unsigned char *c; 676 WAIT; 677 __spl4(); us = *pdma; __spl2() 678 c = (unsigned char *) esc->sc_pdmaddr; 679 *c = us & 0xff; 680 } 681 } 682 #undef WAIT 683 684 nofault = (int *) 0; 685 686 if ((*statreg & 0x80) == 0) { 687 if (espspl != -1) splx(espspl); espspl = -1; 688 return; 689 } 690 691 gotintr: 692 ncr53c9x_intr(sc); 693 if (espspl != -1) splx(espspl); espspl = -1; 694 } 695 696 int 697 esp_dualbus_intr(sc) 698 register struct ncr53c9x_softc *sc; 699 { 700 if (esp0 && (esp0->sc_reg[NCR_STAT * 16] & 0x80)) 701 ncr53c9x_intr((struct ncr53c9x_softc *) esp0); 702 703 if (esp1 && (esp1->sc_reg[NCR_STAT * 16] & 0x80)) 704 ncr53c9x_intr((struct ncr53c9x_softc *) esp1); 705 706 return 0; 707 } 708
Indexes created Mon Sep 29 03:10:08 GMT 2025