esp.c revision 1.3
1 /* $NetBSD: esp.c,v 1.3 1996/11/02 06:52:25 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <scsi/scsi_all.h> 85 #include <scsi/scsiconf.h> 86 #include <scsi/scsi_message.h> 87 88 #include <machine/cpu.h> 89 #include <machine/param.h> 90 91 #if defined(__sparc__) 92 #define SPARC_DRIVER 93 #include <machine/autoconf.h> 94 #include <sparc/dev/sbusvar.h> 95 #include <sparc/dev/dmareg.h> 96 #include <sparc/dev/dmavar.h> 97 #include <sparc/dev/espreg.h> 98 #include <sparc/dev/espvar.h> 99 #else 100 #if (_MACHINE == mac68k) 101 #define MAC68K_DRIVER 102 #include <machine/viareg.h> 103 104 struct dma_softc { 105 struct esp_softc *sc_esp; 106 int sc_active; 107 int sc_tc; 108 int sc_datain; 109 size_t sc_dmasize; 110 size_t sc_dmatrans; 111 char **sc_dmaaddr; 112 size_t *sc_pdmalen; 113 }; 114 115 #include <mac68k/dev/espreg.h> 116 #include <mac68k/dev/espvar.h> 117 #undef ESPCMD_DMA 118 #define ESPCMD_DMA 0 /* No DMA */ 119 #undef ESPCMD_TRPAD 120 #define ESPCMD_TRPAD 0x98 /* TRPAD needs DMA flag*/ 121 122 static __inline__ void dma_intr __P((struct dma_softc *sc)); 123 124 static __inline__ void 125 dma_intr(sc) 126 struct dma_softc *sc; 127 { 128 register u_char *p; 129 register int cnt; 130 131 if (sc->sc_active == 0) { 132 printf("dma_intr--inactive\n"); 133 return; 134 } 135 136 if ((sc->sc_esp->sc_espintr & ESPINTR_BS) == 0) { 137 sc->sc_active = 0; 138 return; 139 } 140 141 p = *sc->sc_dmaaddr; 142 cnt = *sc->sc_pdmalen; 143 if (sc->sc_datain) { 144 if (cnt) { 145 *p++ = ESP_READ_REG(sc->sc_esp, ESP_FIFO); 146 *sc->sc_dmaaddr = p; 147 --(*sc->sc_pdmalen); 148 } else { 149 printf("data in, but no count!\n"); 150 } 151 } 152 if (sc->sc_esp->sc_phase == DATA_IN_PHASE) { 153 ESPCMD(sc->sc_esp, ESPCMD_TRANS); 154 } else if ( (sc->sc_esp->sc_phase == DATA_OUT_PHASE) 155 || (sc->sc_esp->sc_phase == MESSAGE_OUT_PHASE)) { 156 if (cnt) { 157 ESP_WRITE_REG(sc->sc_esp, ESP_FIFO, *p++); 158 *sc->sc_dmaaddr = p; 159 --(*sc->sc_pdmalen); 160 } else { 161 printf("data out, but no count!\n"); 162 } 163 ESPCMD(sc->sc_esp, ESPCMD_TRANS); 164 } else { 165 sc->sc_active = 0; 166 } 167 if (*sc->sc_pdmalen == 0) { 168 sc->sc_tc = ESPSTAT_TC; 169 } 170 sc->sc_esp->sc_espstat |= sc->sc_tc; 171 } 172 #else 173 #include <dev/tc/tcvar.h> 174 #include <alpha/tc/tcdsvar.h> 175 #include <alpha/tc/espreg.h> 176 #include <alpha/tc/espvar.h> 177 #endif 178 #endif 179 180 int esp_debug = 0; /*ESP_SHOWPHASE|ESP_SHOWMISC|ESP_SHOWTRAC|ESP_SHOWCMDS;*/ 181 182 /*static*/ void espattach __P((struct device *, struct device *, void *)); 183 /*static*/ int espmatch __P((struct device *, void *, void *)); 184 /*static*/ u_int esp_adapter_info __P((struct esp_softc *)); 185 /*static*/ void espreadregs __P((struct esp_softc *)); 186 /*static*/ void esp_select __P((struct esp_softc *, struct esp_ecb *)); 187 /*static*/ int esp_reselect __P((struct esp_softc *, int)); 188 /*static*/ void esp_scsi_reset __P((struct esp_softc *)); 189 /*static*/ void esp_reset __P((struct esp_softc *)); 190 /*static*/ void esp_init __P((struct esp_softc *, int)); 191 /*static*/ int esp_scsi_cmd __P((struct scsi_xfer *)); 192 /*static*/ int esp_poll __P((struct esp_softc *, struct scsi_xfer *, int)); 193 /*static*/ void esp_sched __P((struct esp_softc *)); 194 /*static*/ void esp_done __P((struct esp_softc *, struct esp_ecb *)); 195 /*static*/ void esp_msgin __P((struct esp_softc *)); 196 /*static*/ void esp_msgout __P((struct esp_softc *)); 197 /*static*/ int espintr __P((struct esp_softc *)); 198 /*static*/ void esp_timeout __P((void *arg)); 199 /*static*/ void esp_abort __P((struct esp_softc *, struct esp_ecb *)); 200 /*static*/ void esp_dequeue __P((struct esp_softc *, struct esp_ecb *)); 201 void esp_sense __P((struct esp_softc *, struct esp_ecb *)); 202 void esp_free_ecb __P((struct esp_softc *, struct esp_ecb *, int)); 203 struct esp_ecb *esp_get_ecb __P((struct esp_softc *, int)); 204 static inline int esp_stp2cpb __P((struct esp_softc *, int)); 205 static inline int esp_cpb2stp __P((struct esp_softc *, int)); 206 static inline void esp_setsync __P((struct esp_softc *, struct esp_tinfo *)); 207 208 /* Linkup to the rest of the kernel */ 209 struct cfattach esp_ca = { 210 sizeof(struct esp_softc), espmatch, espattach 211 }; 212 213 struct cfdriver esp_cd = { 214 NULL, "esp", DV_DULL 215 }; 216 217 struct scsi_adapter esp_switch = { 218 esp_scsi_cmd, 219 minphys, /* no max at this level; handled by DMA code */ 220 NULL, 221 NULL, 222 }; 223 224 struct scsi_device esp_dev = { 225 NULL, /* Use default error handler */ 226 NULL, /* have a queue, served by this */ 227 NULL, /* have no async handler */ 228 NULL, /* Use default 'done' routine */ 229 }; 230 231 int 232 espmatch(parent, vcf, aux) 233 struct device *parent; 234 void *vcf, *aux; 235 { 236 struct cfdata *cf = vcf; 237 #ifdef SPARC_DRIVER 238 register struct confargs *ca = aux; 239 register struct romaux *ra = &ca->ca_ra; 240 241 if (strcmp(cf->cf_driver->cd_name, ra->ra_name)) 242 return (0); 243 if (ca->ca_bustype == BUS_SBUS) 244 return (1); 245 ra->ra_len = NBPG; 246 return (probeget(ra->ra_vaddr, 1) != -1); 247 #else 248 #ifdef MAC68K_DRIVER 249 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) 250 return (1); 251 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) 252 return (1); 253 return (0); 254 #else 255 struct tcdsdev_attach_args *tcdsdev = aux; 256 257 if (strncmp(tcdsdev->tcdsda_modname, "PMAZ-AA ", TC_ROM_LLEN)) 258 return (0); 259 return (!tc_badaddr(tcdsdev->tcdsda_addr)); 260 #endif 261 #endif 262 } 263 264 /* 265 * Attach this instance, and then all the sub-devices 266 */ 267 void 268 espattach(parent, self, aux) 269 struct device *parent, *self; 270 void *aux; 271 { 272 #ifdef SPARC_DRIVER 273 register struct confargs *ca = aux; 274 #else 275 #ifdef MAC68K_DRIVER 276 extern vm_offset_t SCSIBase; 277 #else 278 register struct tcdsdev_attach_args *tcdsdev = aux; 279 #endif 280 #endif 281 struct esp_softc *sc = (void *)self; 282 #ifdef SPARC_DRIVER 283 struct bootpath *bp; 284 int dmachild = strncmp(parent->dv_xname, "dma", 3) == 0; 285 #endif 286 287 #ifdef SPARC_DRIVER 288 /* 289 * Make sure things are sane. I don't know if this is ever 290 * necessary, but it seem to be in all of Torek's code. 291 */ 292 if (ca->ca_ra.ra_nintr != 1) { 293 printf(": expected 1 interrupt, got %d\n", ca->ca_ra.ra_nintr); 294 return; 295 } 296 297 sc->sc_pri = ca->ca_ra.ra_intr[0].int_pri; 298 printf(" pri %d", sc->sc_pri); 299 300 /* 301 * Map my registers in, if they aren't already in virtual 302 * address space. 303 */ 304 if (ca->ca_ra.ra_vaddr) 305 sc->sc_reg = (volatile u_char *) ca->ca_ra.ra_vaddr; 306 else { 307 sc->sc_reg = (volatile u_char *) 308 mapiodev(ca->ca_ra.ra_reg, 0, ca->ca_ra.ra_len, ca->ca_bustype); 309 } 310 #else 311 #ifdef MAC68K_DRIVER 312 if (sc->sc_dev.dv_unit == 0) { 313 unsigned long reg_offset; 314 315 sc->sc_reg = (volatile u_char *) SCSIBase; 316 mac68k_register_scsi_irq((void (*)(void *)) espintr, sc); 317 sc->irq_mask = V2IF_SCSIIRQ; 318 reg_offset = SCSIBase - IOBase; 319 if (reg_offset == 0x10000) { 320 sc->sc_freq = 16500000; 321 } else { 322 sc->sc_freq = 25000000; 323 } 324 } else { 325 sc->sc_reg = (volatile u_char *) SCSIBase + 0x400; 326 mac68k_register_scsi_b_irq((void (*)(void *)) espintr, sc); 327 sc->irq_mask = V2IF_T1; 328 sc->sc_freq = 25000000; 329 } 330 sc->sc_dma = &sc->_sc_dma; 331 printf(": address %p", sc->sc_reg); 332 333 sc->sc_id = 7; 334 #else 335 sc->sc_reg = (volatile u_int32_t *)tcdsdev->tcdsda_addr; 336 sc->sc_cookie = tcdsdev->tcdsda_cookie; 337 sc->sc_dma = tcdsdev->tcdsda_sc; 338 339 printf(": address %x", sc->sc_reg); 340 tcds_intr_establish(parent, sc->sc_cookie, TC_IPL_BIO, 341 (int (*)(void *))espintr, sc); 342 #endif 343 #endif 344 345 #ifdef SPARC_DRIVER 346 /* Other settings */ 347 sc->sc_node = ca->ca_ra.ra_node; 348 if (ca->ca_bustype == BUS_SBUS) { 349 sc->sc_id = getpropint(sc->sc_node, "initiator-id", 7); 350 sc->sc_freq = getpropint(sc->sc_node, "clock-frequency", -1); 351 } else { 352 sc->sc_id = 7; 353 sc->sc_freq = 24000000; 354 } 355 if (sc->sc_freq < 0) 356 sc->sc_freq = ((struct sbus_softc *) 357 sc->sc_dev.dv_parent)->sc_clockfreq; 358 #else 359 #ifdef MAC68K_DRIVER 360 #else 361 if (parent->dv_cfdata->cf_driver == &tcds_cd) { 362 sc->sc_id = tcdsdev->tcdsda_id; 363 sc->sc_freq = tcdsdev->tcdsda_freq; 364 } else { 365 /* XXX */ 366 sc->sc_id = 7; 367 sc->sc_freq = 24000000; 368 } 369 #endif 370 #endif 371 372 /* gimme Mhz */ 373 sc->sc_freq /= 1000000; 374 375 #ifdef SPARC_DRIVER 376 if (dmachild) { 377 sc->sc_dma = (struct dma_softc *)parent; 378 sc->sc_dma->sc_esp = sc; 379 } else { 380 /* 381 * find the DMA by poking around the dma device structures 382 * 383 * What happens here is that if the dma driver has not been 384 * configured, then this returns a NULL pointer. Then when the 385 * dma actually gets configured, it does the opposing test, and 386 * if the sc->sc_esp field in it's softc is NULL, then tries to 387 * find the matching esp driver. 388 * 389 */ 390 sc->sc_dma = (struct dma_softc *) 391 getdevunit("dma", sc->sc_dev.dv_unit); 392 393 /* 394 * and a back pointer to us, for DMA 395 */ 396 if (sc->sc_dma) 397 sc->sc_dma->sc_esp = sc; 398 else 399 panic("espattach: no dma found"); 400 } 401 #else 402 sc->sc_dma->sc_esp = sc; /* XXX */ 403 #endif 404 405 /* 406 * It is necessary to try to load the 2nd config register here, 407 * to find out what rev the esp chip is, else the esp_reset 408 * will not set up the defaults correctly. 409 */ 410 sc->sc_cfg1 = sc->sc_id | ESPCFG1_PARENB; 411 #ifdef SPARC_DRIVER 412 sc->sc_cfg2 = ESPCFG2_SCSI2 | ESPCFG2_RPE; 413 sc->sc_cfg3 = ESPCFG3_CDB; 414 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 415 416 if ((ESP_READ_REG(sc, ESP_CFG2) & ~ESPCFG2_RSVD) != (ESPCFG2_SCSI2 | ESPCFG2_RPE)) { 417 printf(": ESP100"); 418 sc->sc_rev = ESP100; 419 } else { 420 sc->sc_cfg2 = ESPCFG2_SCSI2; 421 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 422 sc->sc_cfg3 = 0; 423 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 424 sc->sc_cfg3 = (ESPCFG3_CDB | ESPCFG3_FCLK); 425 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 426 if (ESP_READ_REG(sc, ESP_CFG3) != (ESPCFG3_CDB | ESPCFG3_FCLK)) { 427 printf(": ESP100A"); 428 sc->sc_rev = ESP100A; 429 } else { 430 /* ESPCFG2_FE enables > 64K transfers */ 431 sc->sc_cfg2 |= ESPCFG2_FE; 432 sc->sc_cfg3 = 0; 433 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 434 printf(": ESP200"); 435 sc->sc_rev = ESP200; 436 } 437 } 438 #else 439 #ifdef MAC68K_DRIVER 440 sc->sc_cfg2 = ESPCFG2_SCSI2; 441 sc->sc_cfg3 = 0; 442 printf(": NCR53C96"); 443 sc->sc_rev = NCR53C96; 444 #else 445 sc->sc_cfg2 = ESPCFG2_SCSI2; 446 sc->sc_cfg3 = 0x4; /* Save residual byte. XXX??? */ 447 printf(": NCR53C94"); 448 sc->sc_rev = NCR53C94; 449 #endif 450 #endif 451 452 /* 453 * This is the value used to start sync negotiations 454 * Note that the ESP register "SYNCTP" is programmed 455 * in "clocks per byte", and has a minimum value of 4. 456 * The SCSI period used in negotiation is one-fourth 457 * of the time (in nanoseconds) needed to transfer one byte. 458 * Since the chip's clock is given in MHz, we have the following 459 * formula: 4 * period = (1000 / freq) * 4 460 */ 461 sc->sc_minsync = 1000 / sc->sc_freq; 462 463 #ifdef SPARC_DRIVER 464 /* 465 * Alas, we must now modify the value a bit, because it's 466 * only valid when can switch on FASTCLK and FASTSCSI bits 467 * in config register 3... 468 */ 469 switch (sc->sc_rev) { 470 case ESP100: 471 sc->sc_maxxfer = 64 * 1024; 472 sc->sc_minsync = 0; /* No synch on old chip? */ 473 break; 474 case ESP100A: 475 sc->sc_maxxfer = 64 * 1024; 476 sc->sc_minsync = esp_cpb2stp(sc, 5); /* Min clocks/byte is 5 */ 477 break; 478 case ESP200: 479 sc->sc_maxxfer = 16 * 1024 * 1024; 480 /* XXX - do actually set FAST* bits */ 481 } 482 #else 483 #ifdef MAC68K_DRIVER 484 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */ 485 /* Really no limit, but since we want to fit into the TCR... */ 486 sc->sc_maxxfer = 64 * 1024; 487 #else 488 sc->sc_maxxfer = 64 * 1024; 489 #endif 490 #endif 491 492 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 493 494 /* The value *must not* be == 1. Make it 2 */ 495 if (sc->sc_ccf == 1) 496 sc->sc_ccf = 2; 497 498 /* 499 * The recommended timeout is 250ms. This register is loaded 500 * with a value calculated as follows, from the docs: 501 * 502 * (timout period) x (CLK frequency) 503 * reg = ------------------------------------- 504 * 8192 x (Clock Conversion Factor) 505 * 506 * Since CCF has a linear relation to CLK, this generally computes 507 * to the constant of 153. 508 */ 509 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 510 511 /* CCF register only has 3 bits; 0 is actually 8 */ 512 sc->sc_ccf &= 7; 513 514 /* Reset state & bus */ 515 sc->sc_state = 0; 516 esp_init(sc, 1); 517 518 printf(" %dMhz, target %d\n", sc->sc_freq, sc->sc_id); 519 520 #ifdef SPARC_DRIVER 521 /* add me to the sbus structures */ 522 sc->sc_sd.sd_reset = (void *) esp_reset; 523 #if defined(SUN4C) || defined(SUN4M) 524 if (ca->ca_bustype == BUS_SBUS) { 525 if (dmachild) 526 sbus_establish(&sc->sc_sd, sc->sc_dev.dv_parent); 527 else 528 sbus_establish(&sc->sc_sd, &sc->sc_dev); 529 } 530 #endif /* SUN4C || SUN4M */ 531 #endif 532 533 #ifdef SPARC_DRIVER 534 /* and the interuppts */ 535 sc->sc_ih.ih_fun = (void *) espintr; 536 sc->sc_ih.ih_arg = sc; 537 intr_establish(sc->sc_pri, &sc->sc_ih); 538 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 539 #endif 540 541 /* 542 * fill in the prototype scsi_link. 543 */ 544 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 545 sc->sc_link.adapter_softc = sc; 546 sc->sc_link.adapter_target = sc->sc_id; 547 sc->sc_link.adapter = &esp_switch; 548 sc->sc_link.device = &esp_dev; 549 sc->sc_link.openings = 2; 550 551 /* 552 * If the boot path is "esp" at the moment and it's me, then 553 * walk our pointer to the sub-device, ready for the config 554 * below. 555 */ 556 #ifdef SPARC_DRIVER 557 bp = ca->ca_ra.ra_bp; 558 switch (ca->ca_bustype) { 559 case BUS_SBUS: 560 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 561 SAME_ESP(sc, bp, ca)) 562 bootpath_store(1, bp + 1); 563 break; 564 default: 565 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 566 bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit) 567 bootpath_store(1, bp + 1); 568 break; 569 } 570 #endif 571 572 /* 573 * Now try to attach all the sub-devices 574 */ 575 config_found(self, &sc->sc_link, scsiprint); 576 577 #ifdef MAC68K_DRIVER 578 via2_reg(vPCR) = 0x22; 579 via2_reg(vIFR) = sc->irq_mask; 580 via2_reg(vIER) = 0x80 | sc->irq_mask; 581 #endif 582 #ifdef SPARC_DRIVER 583 bootpath_store(1, NULL); 584 #endif 585 } 586 587 /* 588 * This is the generic esp reset function. It does not reset the SCSI bus, 589 * only this controllers, but kills any on-going commands, and also stops 590 * and resets the DMA. 591 * 592 * After reset, registers are loaded with the defaults from the attach 593 * routine above. 594 */ 595 void 596 esp_reset(sc) 597 struct esp_softc *sc; 598 { 599 600 /* reset DMA first */ 601 DMA_RESET(sc->sc_dma); 602 603 /* reset SCSI chip */ 604 ESPCMD(sc, ESPCMD_RSTCHIP); 605 ESPCMD(sc, ESPCMD_NOP); 606 DELAY(500); 607 608 /* do these backwards, and fall through */ 609 switch (sc->sc_rev) { 610 #ifndef SPARC_DRIVER 611 case NCR53C96: 612 case NCR53C94: 613 #endif 614 case ESP200: 615 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 616 case ESP100A: 617 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 618 case ESP100: 619 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 620 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 621 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 622 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 623 break; 624 default: 625 printf("%s: unknown revision code, assuming ESP100\n", 626 sc->sc_dev.dv_xname); 627 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 628 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 629 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 630 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 631 } 632 } 633 634 /* 635 * Reset the SCSI bus, but not the chip 636 */ 637 void 638 esp_scsi_reset(sc) 639 struct esp_softc *sc; 640 { 641 #ifdef SPARC_DRIVER 642 /* stop DMA first, as the chip will return to Bus Free phase */ 643 DMACSR(sc->sc_dma) &= ~D_EN_DMA; 644 #else 645 /* 646 * XXX STOP DMA FIRST 647 */ 648 #endif 649 650 printf("esp: resetting SCSI bus\n"); 651 ESPCMD(sc, ESPCMD_RSTSCSI); 652 } 653 654 /* 655 * Initialize esp state machine 656 */ 657 void 658 esp_init(sc, doreset) 659 struct esp_softc *sc; 660 int doreset; 661 { 662 struct esp_ecb *ecb; 663 int r; 664 665 ESP_TRACE(("[ESP_INIT(%d)] ", doreset)); 666 667 if (sc->sc_state == 0) { 668 /* First time through; initialize. */ 669 TAILQ_INIT(&sc->ready_list); 670 TAILQ_INIT(&sc->nexus_list); 671 TAILQ_INIT(&sc->free_list); 672 sc->sc_nexus = NULL; 673 ecb = sc->sc_ecb; 674 bzero(ecb, sizeof(sc->sc_ecb)); 675 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 676 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 677 ecb++; 678 } 679 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 680 } else { 681 /* Cancel any active commands. */ 682 sc->sc_state = ESP_CLEANING; 683 if ((ecb = sc->sc_nexus) != NULL) { 684 ecb->xs->error = XS_DRIVER_STUFFUP; 685 untimeout(esp_timeout, ecb); 686 esp_done(sc, ecb); 687 } 688 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 689 ecb->xs->error = XS_DRIVER_STUFFUP; 690 untimeout(esp_timeout, ecb); 691 esp_done(sc, ecb); 692 } 693 } 694 695 /* 696 * reset the chip to a known state 697 */ 698 esp_reset(sc); 699 700 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 701 for (r = 0; r < 8; r++) { 702 struct esp_tinfo *ti = &sc->sc_tinfo[r]; 703 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 704 int fl = sc->sc_dev.dv_cfdata->cf_flags; 705 706 ti->flags = ((sc->sc_minsync && !(fl & (1<<(r+8)))) 707 ? T_NEGOTIATE : 0) | 708 ((fl & (1<<r)) ? T_RSELECTOFF : 0) | 709 T_NEED_TO_RESET; 710 ti->period = sc->sc_minsync; 711 ti->offset = 0; 712 } 713 714 if (doreset) { 715 sc->sc_state = ESP_SBR; 716 ESPCMD(sc, ESPCMD_RSTSCSI); 717 } else { 718 sc->sc_state = ESP_IDLE; 719 } 720 } 721 722 /* 723 * Read the ESP registers, and save their contents for later use. 724 * ESP_STAT, ESP_STEP & ESP_INTR are mostly zeroed out when reading 725 * ESP_INTR - so make sure it is the last read. 726 * 727 * I think that (from reading the docs) most bits in these registers 728 * only make sense when he DMA CSR has an interrupt showing. Call only 729 * if an interrupt is pending. 730 */ 731 void 732 espreadregs(sc) 733 struct esp_softc *sc; 734 { 735 736 sc->sc_espstat = ESP_READ_REG(sc, ESP_STAT); 737 /* Only the stepo bits are of interest */ 738 sc->sc_espstep = ESP_READ_REG(sc, ESP_STEP) & ESPSTEP_MASK; 739 sc->sc_espintr = ESP_READ_REG(sc, ESP_INTR); 740 741 #if !defined(SPARC_DRIVER) && !defined(MAC68K_DRIVER) 742 /* Clear the TCDS interrupt bit. */ 743 (void)tcds_scsi_isintr(sc->sc_dma, 1); 744 #endif 745 746 /* 747 * Determine the SCSI bus phase, return either a real SCSI bus phase 748 * or some pseudo phase we use to detect certain exceptions. 749 */ 750 751 sc->sc_phase = (sc->sc_espintr & ESPINTR_DIS) 752 ? /* Disconnected */ BUSFREE_PHASE 753 : sc->sc_espstat & ESPSTAT_PHASE; 754 755 ESP_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 756 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 757 } 758 759 /* 760 * Convert chip register Clock Per Byte value to Synchronous Transfer Period. 761 */ 762 static inline int 763 esp_cpb2stp(sc, cpb) 764 struct esp_softc *sc; 765 int cpb; 766 { 767 return ((250 * cpb) / sc->sc_freq); 768 } 769 770 /* 771 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 772 */ 773 static inline int 774 esp_stp2cpb(sc, period) 775 struct esp_softc *sc; 776 int period; 777 { 778 int v; 779 v = (sc->sc_freq * period) / 250; 780 if (esp_cpb2stp(sc, v) < period) 781 /* Correct round-down error */ 782 v++; 783 return v; 784 } 785 786 static inline void 787 esp_setsync(sc, ti) 788 struct esp_softc *sc; 789 struct esp_tinfo *ti; 790 { 791 792 if (ti->flags & T_SYNCMODE) { 793 ESP_WRITE_REG(sc, ESP_SYNCOFF, ti->offset); 794 ESP_WRITE_REG(sc, ESP_SYNCTP, esp_stp2cpb(sc, ti->period)); 795 } else { 796 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 797 ESP_WRITE_REG(sc, ESP_SYNCTP, 0); 798 } 799 } 800 801 /* 802 * Send a command to a target, set the driver state to ESP_SELECTING 803 * and let the caller take care of the rest. 804 * 805 * Keeping this as a function allows me to say that this may be done 806 * by DMA instead of programmed I/O soon. 807 */ 808 void 809 esp_select(sc, ecb) 810 struct esp_softc *sc; 811 struct esp_ecb *ecb; 812 { 813 struct scsi_link *sc_link = ecb->xs->sc_link; 814 int target = sc_link->target; 815 struct esp_tinfo *ti = &sc->sc_tinfo[target]; 816 u_char *cmd; 817 int clen; 818 819 ESP_TRACE(("[esp_select(t%d,l%d,cmd:%x)] ", sc_link->target, sc_link->lun, ecb->cmd.opcode)); 820 821 /* new state ESP_SELECTING */ 822 sc->sc_state = ESP_SELECTING; 823 824 ESPCMD(sc, ESPCMD_FLUSH); 825 826 /* 827 * The docs say the target register is never reset, and I 828 * can't think of a better place to set it 829 */ 830 ESP_WRITE_REG(sc, ESP_SELID, target); 831 esp_setsync(sc, ti); 832 833 /* 834 * Who am I. This is where we tell the target that we are 835 * happy for it to disconnect etc. 836 */ 837 ESP_WRITE_REG(sc, ESP_FIFO, 838 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 839 840 if (ti->flags & T_NEGOTIATE) { 841 /* Arbitrate, select and stop after IDENTIFY message */ 842 ESPCMD(sc, ESPCMD_SELATNS); 843 return; 844 } 845 846 /* Now the command into the FIFO */ 847 cmd = (u_char *)&ecb->cmd; 848 clen = ecb->clen; 849 while (clen--) 850 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 851 852 /* And get the targets attention */ 853 ESPCMD(sc, ESPCMD_SELATN); 854 } 855 856 void 857 esp_free_ecb(sc, ecb, flags) 858 struct esp_softc *sc; 859 struct esp_ecb *ecb; 860 int flags; 861 { 862 int s; 863 864 s = splbio(); 865 866 ecb->flags = 0; 867 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 868 869 /* 870 * If there were none, wake anybody waiting for one to come free, 871 * starting with queued entries. 872 */ 873 if (ecb->chain.tqe_next == 0) 874 wakeup(&sc->free_list); 875 876 splx(s); 877 } 878 879 struct esp_ecb * 880 esp_get_ecb(sc, flags) 881 struct esp_softc *sc; 882 int flags; 883 { 884 struct esp_ecb *ecb; 885 int s; 886 887 s = splbio(); 888 889 while ((ecb = sc->free_list.tqh_first) == NULL && 890 (flags & SCSI_NOSLEEP) == 0) 891 tsleep(&sc->free_list, PRIBIO, "especb", 0); 892 if (ecb) { 893 TAILQ_REMOVE(&sc->free_list, ecb, chain); 894 ecb->flags |= ECB_ALLOC; 895 } 896 897 splx(s); 898 return ecb; 899 } 900 901 /* 902 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 903 */ 904 905 /* 906 * Start a SCSI-command 907 * This function is called by the higher level SCSI-driver to queue/run 908 * SCSI-commands. 909 */ 910 int 911 esp_scsi_cmd(xs) 912 struct scsi_xfer *xs; 913 { 914 struct scsi_link *sc_link = xs->sc_link; 915 struct esp_softc *sc = sc_link->adapter_softc; 916 struct esp_ecb *ecb; 917 int s, flags; 918 919 ESP_TRACE(("[esp_scsi_cmd] ")); 920 ESP_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 921 sc_link->target)); 922 923 flags = xs->flags; 924 if ((ecb = esp_get_ecb(sc, flags)) == NULL) { 925 xs->error = XS_DRIVER_STUFFUP; 926 return TRY_AGAIN_LATER; 927 } 928 929 /* Initialize ecb */ 930 ecb->xs = xs; 931 ecb->timeout = xs->timeout; 932 933 if (xs->flags & SCSI_RESET) { 934 ecb->flags |= ECB_RESET; 935 ecb->clen = 0; 936 ecb->dleft = 0; 937 } else { 938 bcopy(xs->cmd, &ecb->cmd, xs->cmdlen); 939 ecb->clen = xs->cmdlen; 940 ecb->daddr = xs->data; 941 ecb->dleft = xs->datalen; 942 } 943 ecb->stat = 0; 944 945 s = splbio(); 946 947 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 948 if (sc->sc_state == ESP_IDLE) 949 esp_sched(sc); 950 951 splx(s); 952 953 if ((flags & SCSI_POLL) == 0) 954 return SUCCESSFULLY_QUEUED; 955 956 /* Not allowed to use interrupts, use polling instead */ 957 if (esp_poll(sc, xs, ecb->timeout)) { 958 esp_timeout(ecb); 959 if (esp_poll(sc, xs, ecb->timeout)) 960 esp_timeout(ecb); 961 } 962 return COMPLETE; 963 } 964 965 /* 966 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 967 */ 968 int 969 esp_poll(sc, xs, count) 970 struct esp_softc *sc; 971 struct scsi_xfer *xs; 972 int count; 973 { 974 975 ESP_TRACE(("[esp_poll] ")); 976 while (count) { 977 if (DMA_ISINTR(sc->sc_dma)) { 978 espintr(sc); 979 } 980 #if alternatively 981 if (ESP_READ_REG(sc, ESP_STAT) & ESPSTAT_INT) 982 espintr(sc); 983 #endif 984 if ((xs->flags & ITSDONE) != 0) 985 return 0; 986 if (sc->sc_state == ESP_IDLE) { 987 ESP_TRACE(("[esp_poll: rescheduling] ")); 988 esp_sched(sc); 989 } 990 DELAY(1000); 991 count--; 992 } 993 return 1; 994 } 995 996 997 /* 998 * LOW LEVEL SCSI UTILITIES 999 */ 1000 1001 /* 1002 * Schedule a scsi operation. This has now been pulled out of the interrupt 1003 * handler so that we may call it from esp_scsi_cmd and esp_done. This may 1004 * save us an unecessary interrupt just to get things going. Should only be 1005 * called when state == ESP_IDLE and at bio pl. 1006 */ 1007 void 1008 esp_sched(sc) 1009 struct esp_softc *sc; 1010 { 1011 struct esp_ecb *ecb; 1012 struct scsi_link *sc_link; 1013 struct esp_tinfo *ti; 1014 1015 ESP_TRACE(("[esp_sched] ")); 1016 if (sc->sc_state != ESP_IDLE) 1017 panic("esp_sched: not IDLE (state=%d)", sc->sc_state); 1018 1019 /* 1020 * Find first ecb in ready queue that is for a target/lunit 1021 * combinations that is not busy. 1022 */ 1023 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 1024 sc_link = ecb->xs->sc_link; 1025 ti = &sc->sc_tinfo[sc_link->target]; 1026 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 1027 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1028 sc->sc_nexus = ecb; 1029 esp_select(sc, ecb); 1030 break; 1031 } else 1032 ESP_MISC(("%d:%d busy\n", 1033 sc_link->target, sc_link->lun)); 1034 } 1035 } 1036 1037 void 1038 esp_sense(sc, ecb) 1039 struct esp_softc *sc; 1040 struct esp_ecb *ecb; 1041 { 1042 struct scsi_xfer *xs = ecb->xs; 1043 struct scsi_link *sc_link = xs->sc_link; 1044 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1045 struct scsi_sense *ss = (void *)&ecb->cmd; 1046 1047 ESP_MISC(("requesting sense ")); 1048 /* Next, setup a request sense command block */ 1049 bzero(ss, sizeof(*ss)); 1050 ss->opcode = REQUEST_SENSE; 1051 ss->byte2 = sc_link->lun << 5; 1052 ss->length = sizeof(struct scsi_sense_data); 1053 ecb->clen = sizeof(*ss); 1054 ecb->daddr = (char *)&xs->sense; 1055 ecb->dleft = sizeof(struct scsi_sense_data); 1056 ecb->flags |= ECB_SENSE; 1057 ti->senses++; 1058 if (ecb->flags & ECB_NEXUS) 1059 ti->lubusy &= ~(1 << sc_link->lun); 1060 if (ecb == sc->sc_nexus) { 1061 esp_select(sc, ecb); 1062 } else { 1063 esp_dequeue(sc, ecb); 1064 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1065 if (sc->sc_state == ESP_IDLE) 1066 esp_sched(sc); 1067 } 1068 } 1069 1070 /* 1071 * POST PROCESSING OF SCSI_CMD (usually current) 1072 */ 1073 void 1074 esp_done(sc, ecb) 1075 struct esp_softc *sc; 1076 struct esp_ecb *ecb; 1077 { 1078 struct scsi_xfer *xs = ecb->xs; 1079 struct scsi_link *sc_link = xs->sc_link; 1080 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1081 1082 ESP_TRACE(("[esp_done(error:%x)] ", xs->error)); 1083 1084 /* 1085 * Now, if we've come here with no error code, i.e. we've kept the 1086 * initial XS_NOERROR, and the status code signals that we should 1087 * check sense, we'll need to set up a request sense cmd block and 1088 * push the command back into the ready queue *before* any other 1089 * commands for this target/lunit, else we lose the sense info. 1090 * We don't support chk sense conditions for the request sense cmd. 1091 */ 1092 if (xs->error == XS_NOERROR) { 1093 if ((ecb->flags & ECB_ABORT) != 0) { 1094 xs->error = XS_DRIVER_STUFFUP; 1095 } else if ((ecb->flags & ECB_SENSE) != 0) { 1096 xs->error = XS_SENSE; 1097 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 1098 /* First, save the return values */ 1099 xs->resid = ecb->dleft; 1100 xs->status = ecb->stat; 1101 esp_sense(sc, ecb); 1102 return; 1103 } else { 1104 xs->resid = ecb->dleft; 1105 } 1106 } 1107 1108 xs->flags |= ITSDONE; 1109 1110 #if ESP_DEBUG > 0 1111 if (esp_debug & ESP_SHOWMISC) { 1112 if (xs->resid != 0) 1113 printf("resid=%d ", xs->resid); 1114 if (xs->error == XS_SENSE) 1115 printf("sense=0x%02x\n", xs->sense.error_code); 1116 else 1117 printf("error=%d\n", xs->error); 1118 } 1119 #endif 1120 1121 /* 1122 * Remove the ECB from whatever queue it's on. 1123 */ 1124 if (ecb->flags & ECB_NEXUS) 1125 ti->lubusy &= ~(1 << sc_link->lun); 1126 if (ecb == sc->sc_nexus) { 1127 sc->sc_nexus = NULL; 1128 sc->sc_state = ESP_IDLE; 1129 esp_sched(sc); 1130 } else 1131 esp_dequeue(sc, ecb); 1132 1133 esp_free_ecb(sc, ecb, xs->flags); 1134 ti->cmds++; 1135 scsi_done(xs); 1136 } 1137 1138 void 1139 esp_dequeue(sc, ecb) 1140 struct esp_softc *sc; 1141 struct esp_ecb *ecb; 1142 { 1143 1144 if (ecb->flags & ECB_NEXUS) { 1145 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1146 } else { 1147 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1148 } 1149 } 1150 1151 /* 1152 * INTERRUPT/PROTOCOL ENGINE 1153 */ 1154 1155 /* 1156 * Schedule an outgoing message by prioritizing it, and asserting 1157 * attention on the bus. We can only do this when we are the initiator 1158 * else there will be an illegal command interrupt. 1159 */ 1160 #define esp_sched_msgout(m) \ 1161 do { \ 1162 ESP_MISC(("esp_sched_msgout %d ", m)); \ 1163 ESPCMD(sc, ESPCMD_SETATN); \ 1164 sc->sc_flags |= ESP_ATN; \ 1165 sc->sc_msgpriq |= (m); \ 1166 } while (0) 1167 1168 int 1169 esp_reselect(sc, message) 1170 struct esp_softc *sc; 1171 int message; 1172 { 1173 u_char selid, target, lun; 1174 struct esp_ecb *ecb; 1175 struct scsi_link *sc_link; 1176 struct esp_tinfo *ti; 1177 1178 /* 1179 * The SCSI chip made a snapshot of the data bus while the reselection 1180 * was being negotiated. This enables us to determine which target did 1181 * the reselect. 1182 */ 1183 selid = sc->sc_selid & ~(1 << sc->sc_id); 1184 if (selid & (selid - 1)) { 1185 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 1186 sc->sc_dev.dv_xname, selid); 1187 goto reset; 1188 } 1189 1190 /* 1191 * Search wait queue for disconnected cmd 1192 * The list should be short, so I haven't bothered with 1193 * any more sophisticated structures than a simple 1194 * singly linked list. 1195 */ 1196 target = ffs(selid) - 1; 1197 lun = message & 0x07; 1198 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 1199 ecb = ecb->chain.tqe_next) { 1200 sc_link = ecb->xs->sc_link; 1201 if (sc_link->target == target && sc_link->lun == lun) 1202 break; 1203 } 1204 if (ecb == NULL) { 1205 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 1206 sc->sc_dev.dv_xname, target, lun); 1207 goto abort; 1208 } 1209 1210 /* Make this nexus active again. */ 1211 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1212 sc->sc_state = ESP_CONNECTED; 1213 sc->sc_nexus = ecb; 1214 ti = &sc->sc_tinfo[target]; 1215 ti->lubusy |= (1 << lun); 1216 esp_setsync(sc, ti); 1217 1218 if (ecb->flags & ECB_RESET) 1219 esp_sched_msgout(SEND_DEV_RESET); 1220 else if (ecb->flags & ECB_ABORT) 1221 esp_sched_msgout(SEND_ABORT); 1222 1223 /* Do an implicit RESTORE POINTERS. */ 1224 sc->sc_dp = ecb->daddr; 1225 sc->sc_dleft = ecb->dleft; 1226 1227 return (0); 1228 1229 reset: 1230 esp_sched_msgout(SEND_DEV_RESET); 1231 return (1); 1232 1233 abort: 1234 esp_sched_msgout(SEND_ABORT); 1235 return (1); 1236 } 1237 1238 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 1239 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1240 #define ISEXTMSG(m) ((m) == 1) 1241 1242 /* 1243 * Get an incoming message as initiator. 1244 * 1245 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1246 * byte in the FIFO 1247 */ 1248 void 1249 esp_msgin(sc) 1250 register struct esp_softc *sc; 1251 { 1252 register int v; 1253 1254 ESP_TRACE(("[esp_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1255 1256 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) == 0) { 1257 printf("%s: msgin: no msg byte available\n", 1258 sc->sc_dev.dv_xname); 1259 return; 1260 } 1261 1262 /* 1263 * Prepare for a new message. A message should (according 1264 * to the SCSI standard) be transmitted in one single 1265 * MESSAGE_IN_PHASE. If we have been in some other phase, 1266 * then this is a new message. 1267 */ 1268 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1269 sc->sc_flags &= ~ESP_DROP_MSGI; 1270 sc->sc_imlen = 0; 1271 } 1272 1273 v = ESP_READ_REG(sc, ESP_FIFO); 1274 ESP_MISC(("<msgbyte:0x%02x>", v)); 1275 1276 #if 0 1277 if (sc->sc_state == ESP_RESELECTED && sc->sc_imlen == 0) { 1278 /* 1279 * Which target is reselecting us? (The ID bit really) 1280 */ 1281 sc->sc_selid = v; 1282 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1283 return; 1284 } 1285 #endif 1286 1287 sc->sc_imess[sc->sc_imlen] = v; 1288 1289 /* 1290 * If we're going to reject the message, don't bother storing 1291 * the incoming bytes. But still, we need to ACK them. 1292 */ 1293 1294 if ((sc->sc_flags & ESP_DROP_MSGI)) { 1295 ESPCMD(sc, ESPCMD_MSGOK); 1296 printf("<dropping msg byte %x>", 1297 sc->sc_imess[sc->sc_imlen]); 1298 return; 1299 } 1300 1301 if (sc->sc_imlen >= ESP_MAX_MSG_LEN) { 1302 esp_sched_msgout(SEND_REJECT); 1303 sc->sc_flags |= ESP_DROP_MSGI; 1304 } else { 1305 sc->sc_imlen++; 1306 /* 1307 * This testing is suboptimal, but most 1308 * messages will be of the one byte variety, so 1309 * it should not effect performance 1310 * significantly. 1311 */ 1312 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1313 goto gotit; 1314 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1315 goto gotit; 1316 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1317 sc->sc_imlen == sc->sc_imess[1] + 2) 1318 goto gotit; 1319 } 1320 /* Ack what we have so far */ 1321 ESPCMD(sc, ESPCMD_MSGOK); 1322 return; 1323 1324 gotit: 1325 ESP_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1326 /* 1327 * Now we should have a complete message (1 byte, 2 byte 1328 * and moderately long extended messages). We only handle 1329 * extended messages which total length is shorter than 1330 * ESP_MAX_MSG_LEN. Longer messages will be amputated. 1331 */ 1332 switch (sc->sc_state) { 1333 struct esp_ecb *ecb; 1334 struct esp_tinfo *ti; 1335 1336 case ESP_CONNECTED: 1337 ecb = sc->sc_nexus; 1338 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1339 1340 switch (sc->sc_imess[0]) { 1341 case MSG_CMDCOMPLETE: 1342 ESP_MSGS(("cmdcomplete ")); 1343 if (sc->sc_dleft < 0) { 1344 struct scsi_link *sc_link = ecb->xs->sc_link; 1345 printf("%s: %d extra bytes from %d:%d\n", 1346 sc->sc_dev.dv_xname, -sc->sc_dleft, 1347 sc_link->target, sc_link->lun); 1348 sc->sc_dleft = 0; 1349 } 1350 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 1351 sc->sc_state = ESP_CMDCOMPLETE; 1352 break; 1353 1354 case MSG_MESSAGE_REJECT: 1355 if (esp_debug & ESP_SHOWMSGS) 1356 printf("%s: our msg rejected by target\n", 1357 sc->sc_dev.dv_xname); 1358 switch (sc->sc_msgout) { 1359 case SEND_SDTR: 1360 sc->sc_flags &= ~ESP_SYNCHNEGO; 1361 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1362 esp_setsync(sc, ti); 1363 break; 1364 case SEND_INIT_DET_ERR: 1365 goto abort; 1366 } 1367 break; 1368 1369 case MSG_NOOP: 1370 ESP_MSGS(("noop ")); 1371 break; 1372 1373 case MSG_DISCONNECT: 1374 ESP_MSGS(("disconnect ")); 1375 ti->dconns++; 1376 sc->sc_state = ESP_DISCONNECT; 1377 if ((ecb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1378 break; 1379 /*FALLTHROUGH*/ 1380 1381 case MSG_SAVEDATAPOINTER: 1382 ESP_MSGS(("save datapointer ")); 1383 ecb->daddr = sc->sc_dp; 1384 ecb->dleft = sc->sc_dleft; 1385 break; 1386 1387 case MSG_RESTOREPOINTERS: 1388 ESP_MSGS(("restore datapointer ")); 1389 sc->sc_dp = ecb->daddr; 1390 sc->sc_dleft = ecb->dleft; 1391 break; 1392 1393 case MSG_EXTENDED: 1394 ESP_MSGS(("extended(%x) ", sc->sc_imess[2])); 1395 switch (sc->sc_imess[2]) { 1396 case MSG_EXT_SDTR: 1397 ESP_MSGS(("SDTR period %d, offset %d ", 1398 sc->sc_imess[3], sc->sc_imess[4])); 1399 if (sc->sc_imess[1] != 3) 1400 goto reject; 1401 ti->period = sc->sc_imess[3]; 1402 ti->offset = sc->sc_imess[4]; 1403 ti->flags &= ~T_NEGOTIATE; 1404 if (sc->sc_minsync == 0 || 1405 ti->offset == 0 || 1406 ti->period > 124) { 1407 printf("%s:%d: async\n", "esp", 1408 ecb->xs->sc_link->target); 1409 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1410 /* target initiated negotiation */ 1411 ti->offset = 0; 1412 ti->flags &= ~T_SYNCMODE; 1413 esp_sched_msgout(SEND_SDTR); 1414 } else { 1415 /* we are async */ 1416 ti->flags &= ~T_SYNCMODE; 1417 } 1418 } else { 1419 int r = 250/ti->period; 1420 int s = (100*250)/ti->period - 100*r; 1421 int p; 1422 1423 p = esp_stp2cpb(sc, ti->period); 1424 ti->period = esp_cpb2stp(sc, p); 1425 #ifdef ESP_DEBUG 1426 sc_print_addr(ecb->xs->sc_link); 1427 printf("max sync rate %d.%02dMb/s\n", 1428 r, s); 1429 #endif 1430 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1431 /* target initiated negotiation */ 1432 if (ti->period < sc->sc_minsync) 1433 ti->period = sc->sc_minsync; 1434 if (ti->offset > 15) 1435 ti->offset = 15; 1436 ti->flags &= ~T_SYNCMODE; 1437 esp_sched_msgout(SEND_SDTR); 1438 } else { 1439 /* we are sync */ 1440 ti->flags |= T_SYNCMODE; 1441 } 1442 } 1443 sc->sc_flags &= ~ESP_SYNCHNEGO; 1444 esp_setsync(sc, ti); 1445 break; 1446 1447 default: 1448 printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n", 1449 sc->sc_dev.dv_xname); 1450 goto reject; 1451 } 1452 break; 1453 1454 default: 1455 ESP_MSGS(("ident ")); 1456 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1457 sc->sc_dev.dv_xname); 1458 reject: 1459 esp_sched_msgout(SEND_REJECT); 1460 break; 1461 } 1462 break; 1463 1464 case ESP_RESELECTED: 1465 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1466 printf("%s: reselect without IDENTIFY; sending DEVICE RESET\n", 1467 sc->sc_dev.dv_xname); 1468 goto reset; 1469 } 1470 1471 (void) esp_reselect(sc, sc->sc_imess[0]); 1472 break; 1473 1474 default: 1475 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1476 sc->sc_dev.dv_xname); 1477 reset: 1478 esp_sched_msgout(SEND_DEV_RESET); 1479 break; 1480 1481 abort: 1482 esp_sched_msgout(SEND_ABORT); 1483 break; 1484 } 1485 1486 /* Ack last message byte */ 1487 ESPCMD(sc, ESPCMD_MSGOK); 1488 1489 /* Done, reset message pointer. */ 1490 sc->sc_flags &= ~ESP_DROP_MSGI; 1491 sc->sc_imlen = 0; 1492 } 1493 1494 1495 /* 1496 * Send the highest priority, scheduled message 1497 */ 1498 void 1499 esp_msgout(sc) 1500 register struct esp_softc *sc; 1501 { 1502 struct esp_tinfo *ti; 1503 struct esp_ecb *ecb; 1504 size_t size; 1505 1506 ESP_TRACE(("[esp_msgout(priq:%x, prevphase:%x)]", sc->sc_msgpriq, sc->sc_prevphase)); 1507 1508 if (sc->sc_flags & ESP_ATN) { 1509 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1510 new: 1511 ESPCMD(sc, ESPCMD_FLUSH); 1512 DELAY(1); 1513 sc->sc_msgoutq = 0; 1514 sc->sc_omlen = 0; 1515 } 1516 } else { 1517 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1518 esp_sched_msgout(sc->sc_msgoutq); 1519 goto new; 1520 } else { 1521 printf("esp at line %d: unexpected MESSAGE OUT phase\n", __LINE__); 1522 } 1523 } 1524 1525 if (sc->sc_omlen == 0) { 1526 /* Pick up highest priority message */ 1527 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1528 sc->sc_msgoutq |= sc->sc_msgout; 1529 sc->sc_msgpriq &= ~sc->sc_msgout; 1530 sc->sc_omlen = 1; /* "Default" message len */ 1531 switch (sc->sc_msgout) { 1532 case SEND_SDTR: 1533 ecb = sc->sc_nexus; 1534 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1535 sc->sc_omess[0] = MSG_EXTENDED; 1536 sc->sc_omess[1] = 3; 1537 sc->sc_omess[2] = MSG_EXT_SDTR; 1538 sc->sc_omess[3] = ti->period; 1539 sc->sc_omess[4] = ti->offset; 1540 sc->sc_omlen = 5; 1541 if ((sc->sc_flags & ESP_SYNCHNEGO) == 0) { 1542 ti->flags |= T_SYNCMODE; 1543 esp_setsync(sc, ti); 1544 } 1545 break; 1546 case SEND_IDENTIFY: 1547 if (sc->sc_state != ESP_CONNECTED) { 1548 printf("esp at line %d: no nexus\n", __LINE__); 1549 } 1550 ecb = sc->sc_nexus; 1551 sc->sc_omess[0] = MSG_IDENTIFY(ecb->xs->sc_link->lun,0); 1552 break; 1553 case SEND_DEV_RESET: 1554 sc->sc_flags |= ESP_ABORTING; 1555 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1556 ecb = sc->sc_nexus; 1557 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1558 ti->flags &= ~T_SYNCMODE; 1559 ti->flags |= T_NEGOTIATE; 1560 break; 1561 case SEND_PARITY_ERROR: 1562 sc->sc_omess[0] = MSG_PARITY_ERROR; 1563 break; 1564 case SEND_ABORT: 1565 sc->sc_flags |= ESP_ABORTING; 1566 sc->sc_omess[0] = MSG_ABORT; 1567 break; 1568 case SEND_INIT_DET_ERR: 1569 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1570 break; 1571 case SEND_REJECT: 1572 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1573 break; 1574 default: 1575 ESPCMD(sc, ESPCMD_RSTATN); 1576 sc->sc_flags &= ~ESP_ATN; 1577 sc->sc_omess[0] = MSG_NOOP; 1578 break; 1579 } 1580 sc->sc_omp = sc->sc_omess; 1581 } 1582 1583 #if 1 1584 /* (re)send the message */ 1585 size = min(sc->sc_omlen, sc->sc_maxxfer); 1586 DMA_SETUP(sc->sc_dma, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1587 #ifndef MAC68K_DRIVER 1588 /* Program the SCSI counter */ 1589 ESP_WRITE_REG(sc, ESP_TCL, size); 1590 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 1591 if (sc->sc_cfg2 & ESPCFG2_FE) { 1592 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 1593 } 1594 /* load the count in */ 1595 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 1596 #endif 1597 ESPCMD(sc, ESPCMD_TRANS|ESPCMD_DMA); 1598 DMA_GO(sc->sc_dma); 1599 #else 1600 { int i; 1601 for (i = 0; i < sc->sc_omlen; i++) 1602 ESP_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1603 ESPCMD(sc, ESPCMD_TRANS); 1604 sc->sc_omlen = 0; 1605 } 1606 #endif 1607 } 1608 1609 /* 1610 * This is the most critical part of the driver, and has to know 1611 * how to deal with *all* error conditions and phases from the SCSI 1612 * bus. If there are no errors and the DMA was active, then call the 1613 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1614 * and we can return from here without further processing. 1615 * 1616 * Most of this needs verifying. 1617 */ 1618 int 1619 espintr(sc) 1620 register struct esp_softc *sc; 1621 { 1622 register struct esp_ecb *ecb; 1623 register struct scsi_link *sc_link; 1624 struct esp_tinfo *ti; 1625 int loop; 1626 size_t size; 1627 1628 ESP_TRACE(("[espintr]")); 1629 1630 /* 1631 * I have made some (maybe seriously flawed) assumptions here, 1632 * but basic testing (uncomment the printf() below), show that 1633 * certainly something happens when this loop is here. 1634 * 1635 * The idea is that many of the SCSI operations take very little 1636 * time, and going away and getting interrupted is too high an 1637 * overhead to pay. For example, selecting, sending a message 1638 * and command and then doing some work can be done in one "pass". 1639 * 1640 * The DELAY is not variable because I do not understand that the 1641 * DELAY loop should be fixed-time regardless of CPU speed, but 1642 * I am *assuming* that the faster SCSI processors get things done 1643 * quicker (sending a command byte etc), and so there is no 1644 * need to be too slow. 1645 * 1646 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1647 * at 40Mhz. This needs testing. 1648 */ 1649 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1650 /* a feeling of deja-vu */ 1651 if (!DMA_ISINTR(sc->sc_dma)) 1652 return (loop != 0); 1653 #if 0 1654 if (loop) 1655 printf("*"); 1656 #endif 1657 1658 /* and what do the registers say... */ 1659 espreadregs(sc); 1660 1661 sc->sc_intrcnt.ev_count++; 1662 1663 /* 1664 * At the moment, only a SCSI Bus Reset or Illegal 1665 * Command are classed as errors. A disconnect is a 1666 * valid condition, and we let the code check is the 1667 * "ESP_BUSFREE_OK" flag was set before declaring it 1668 * and error. 1669 * 1670 * Also, the status register tells us about "Gross 1671 * Errors" and "Parity errors". Only the Gross Error 1672 * is really bad, and the parity errors are dealt 1673 * with later 1674 * 1675 * TODO 1676 * If there are too many parity error, go to slow 1677 * cable mode ? 1678 */ 1679 1680 /* SCSI Reset */ 1681 if (sc->sc_espintr & ESPINTR_SBR) { 1682 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1683 ESPCMD(sc, ESPCMD_FLUSH); 1684 DELAY(1); 1685 } 1686 if (sc->sc_state != ESP_SBR) { 1687 printf("%s: SCSI bus reset\n", 1688 sc->sc_dev.dv_xname); 1689 esp_init(sc, 0); /* Restart everything */ 1690 return 1; 1691 } 1692 #if 0 1693 /*XXX*/ printf("<expected bus reset: " 1694 "[intr %x, stat %x, step %d]>\n", 1695 sc->sc_espintr, sc->sc_espstat, 1696 sc->sc_espstep); 1697 #endif 1698 if (sc->sc_nexus) 1699 panic("%s: nexus in reset state", 1700 sc->sc_dev.dv_xname); 1701 goto sched; 1702 } 1703 1704 ecb = sc->sc_nexus; 1705 1706 #define ESPINTR_ERR (ESPINTR_SBR|ESPINTR_ILL) 1707 if (sc->sc_espintr & ESPINTR_ERR || 1708 sc->sc_espstat & ESPSTAT_GE) { 1709 1710 if (sc->sc_espstat & ESPSTAT_GE) { 1711 /* no target ? */ 1712 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1713 ESPCMD(sc, ESPCMD_FLUSH); 1714 DELAY(1); 1715 } 1716 if (sc->sc_state == ESP_CONNECTED || 1717 sc->sc_state == ESP_SELECTING) { 1718 ecb->xs->error = XS_DRIVER_STUFFUP; 1719 esp_done(sc, ecb); 1720 } 1721 return 1; 1722 } 1723 1724 if (sc->sc_espintr & ESPINTR_ILL) { 1725 /* illegal command, out of sync ? */ 1726 printf("%s: illegal command: 0x%x (state %d, phase %x, prevphase %x)\n", 1727 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1728 sc->sc_state, sc->sc_phase, 1729 sc->sc_prevphase); 1730 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1731 ESPCMD(sc, ESPCMD_FLUSH); 1732 DELAY(1); 1733 } 1734 esp_init(sc, 0); /* Restart everything */ 1735 return 1; 1736 } 1737 } 1738 1739 /* 1740 * Call if DMA is active. 1741 * 1742 * If DMA_INTR returns true, then maybe go 'round the loop 1743 * again in case there is no more DMA queued, but a phase 1744 * change is expected. 1745 */ 1746 if (DMA_ISACTIVE(sc->sc_dma)) { 1747 DMA_INTR(sc->sc_dma); 1748 /* If DMA active here, then go back to work... */ 1749 if (DMA_ISACTIVE(sc->sc_dma)) 1750 return 1; 1751 1752 if (sc->sc_dleft == 0 && 1753 (sc->sc_espstat & ESPSTAT_TC) == 0) 1754 printf("%s: !TC [intr %x, stat %x, step %d]" 1755 " prevphase %x, resid %x\n", 1756 sc->sc_dev.dv_xname, 1757 sc->sc_espintr, 1758 sc->sc_espstat, 1759 sc->sc_espstep, 1760 sc->sc_prevphase, 1761 ecb?ecb->dleft:-1); 1762 } 1763 1764 #if 0 /* Unreliable on some ESP revisions? */ 1765 if ((sc->sc_espstat & ESPSTAT_INT) == 0) { 1766 printf("%s: spurious interrupt\n", sc->sc_dev.dv_xname); 1767 return 1; 1768 } 1769 #endif 1770 1771 /* 1772 * check for less serious errors 1773 */ 1774 if (sc->sc_espstat & ESPSTAT_PE) { 1775 printf("%s: SCSI bus parity error\n", 1776 sc->sc_dev.dv_xname); 1777 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1778 esp_sched_msgout(SEND_PARITY_ERROR); 1779 else 1780 esp_sched_msgout(SEND_INIT_DET_ERR); 1781 } 1782 1783 if (sc->sc_espintr & ESPINTR_DIS) { 1784 ESP_MISC(("<DISC [intr %x, stat %x, step %d]>", 1785 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1786 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1787 ESPCMD(sc, ESPCMD_FLUSH); 1788 DELAY(1); 1789 } 1790 /* 1791 * This command must (apparently) be issued within 1792 * 250mS of a disconnect. So here you are... 1793 */ 1794 ESPCMD(sc, ESPCMD_ENSEL); 1795 switch (sc->sc_state) { 1796 case ESP_RESELECTED: 1797 goto sched; 1798 1799 case ESP_SELECTING: 1800 ecb->xs->error = XS_SELTIMEOUT; 1801 goto finish; 1802 1803 case ESP_CONNECTED: 1804 if ((sc->sc_flags & ESP_SYNCHNEGO)) { 1805 #ifdef ESP_DEBUG 1806 if (ecb) 1807 sc_print_addr(ecb->xs->sc_link); 1808 printf("sync nego not completed!\n"); 1809 #endif 1810 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1811 sc->sc_flags &= ~ESP_SYNCHNEGO; 1812 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1813 } 1814 1815 /* it may be OK to disconnect */ 1816 if ((sc->sc_flags & ESP_ABORTING) == 0) { 1817 /* 1818 * Section 5.1.1 of the SCSI 2 spec 1819 * suggests issuing a REQUEST SENSE 1820 * following an unexpected disconnect. 1821 * Some devices go into a contingent 1822 * allegiance condition when 1823 * disconnecting, and this is necessary 1824 * to clean up their state. 1825 */ 1826 printf("%s: unexpected disconnect; ", 1827 sc->sc_dev.dv_xname); 1828 if (ecb->flags & ECB_SENSE) { 1829 printf("resetting\n"); 1830 goto reset; 1831 } 1832 printf("sending REQUEST SENSE\n"); 1833 esp_sense(sc, ecb); 1834 goto out; 1835 } 1836 1837 ecb->xs->error = XS_DRIVER_STUFFUP; 1838 goto finish; 1839 1840 case ESP_DISCONNECT: 1841 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1842 sc->sc_nexus = NULL; 1843 goto sched; 1844 1845 case ESP_CMDCOMPLETE: 1846 goto finish; 1847 } 1848 } 1849 1850 switch (sc->sc_state) { 1851 1852 case ESP_SBR: 1853 printf("%s: waiting for SCSI Bus Reset to happen\n", 1854 sc->sc_dev.dv_xname); 1855 return 1; 1856 1857 case ESP_RESELECTED: 1858 /* 1859 * we must be continuing a message ? 1860 */ 1861 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1862 printf("%s: target didn't identify\n", 1863 sc->sc_dev.dv_xname); 1864 esp_init(sc, 1); 1865 return 1; 1866 } 1867 printf("<<RESELECT CONT'd>>"); 1868 #if XXXX 1869 esp_msgin(sc); 1870 if (sc->sc_state != ESP_CONNECTED) { 1871 /* IDENTIFY fail?! */ 1872 printf("%s: identify failed\n", 1873 sc->sc_dev.dv_xname); 1874 esp_init(sc, 1); 1875 return 1; 1876 } 1877 #endif 1878 break; 1879 1880 case ESP_IDLE: 1881 if (sc->sc_flags & ESP_ICCS) printf("[[esp: BUMMER]]"); 1882 case ESP_SELECTING: 1883 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1884 sc->sc_flags = 0; 1885 1886 if (sc->sc_espintr & ESPINTR_RESEL) { 1887 /* 1888 * If we're trying to select a 1889 * target ourselves, push our command 1890 * back into the ready list. 1891 */ 1892 if (sc->sc_state == ESP_SELECTING) { 1893 ESP_MISC(("backoff selector ")); 1894 sc_link = sc->sc_nexus->xs->sc_link; 1895 ti = &sc->sc_tinfo[sc_link->target]; 1896 TAILQ_INSERT_HEAD(&sc->ready_list, 1897 sc->sc_nexus, chain); 1898 ecb = sc->sc_nexus = NULL; 1899 } 1900 sc->sc_state = ESP_RESELECTED; 1901 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1902 /* 1903 * Things are seriously fucked up. 1904 * Pull the brakes, i.e. reset 1905 */ 1906 printf("%s: target didn't identify\n", 1907 sc->sc_dev.dv_xname); 1908 esp_init(sc, 1); 1909 return 1; 1910 } 1911 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 1912 printf("%s: RESELECT: %d bytes in FIFO!\n", 1913 sc->sc_dev.dv_xname, 1914 ESP_READ_REG(sc, ESP_FFLAG) & 1915 ESPFIFO_FF); 1916 esp_init(sc, 1); 1917 return 1; 1918 } 1919 sc->sc_selid = ESP_READ_REG(sc, ESP_FIFO); 1920 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1921 esp_msgin(sc); /* Handle identify message */ 1922 if (sc->sc_state != ESP_CONNECTED) { 1923 /* IDENTIFY fail?! */ 1924 printf("%s: identify failed\n", 1925 sc->sc_dev.dv_xname); 1926 esp_init(sc, 1); 1927 return 1; 1928 } 1929 continue; /* ie. next phase expected soon */ 1930 } 1931 1932 #define ESPINTR_DONE (ESPINTR_FC|ESPINTR_BS) 1933 if ((sc->sc_espintr & ESPINTR_DONE) == ESPINTR_DONE) { 1934 ecb = sc->sc_nexus; 1935 if (!ecb) 1936 panic("esp: not nexus at sc->sc_nexus"); 1937 1938 sc_link = ecb->xs->sc_link; 1939 ti = &sc->sc_tinfo[sc_link->target]; 1940 1941 switch (sc->sc_espstep) { 1942 case 0: 1943 printf("%s: select timeout/no disconnect\n", 1944 sc->sc_dev.dv_xname); 1945 ecb->xs->error = XS_SELTIMEOUT; 1946 goto finish; 1947 case 1: 1948 if ((ti->flags & T_NEGOTIATE) == 0) { 1949 printf("%s: step 1 & !NEG\n", 1950 sc->sc_dev.dv_xname); 1951 goto reset; 1952 } 1953 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1954 printf("%s: !MSGOUT\n", 1955 sc->sc_dev.dv_xname); 1956 goto reset; 1957 } 1958 /* Start negotiating */ 1959 ti->period = sc->sc_minsync; 1960 ti->offset = 15; 1961 sc->sc_flags |= ESP_SYNCHNEGO; 1962 esp_sched_msgout(SEND_SDTR); 1963 break; 1964 case 3: 1965 /* 1966 * Grr, this is supposed to mean 1967 * "target left command phase 1968 * prematurely". It seems to happen 1969 * regularly when sync mode is on. 1970 * Look at FIFO to see if command 1971 * went out. 1972 * (Timing problems?) 1973 */ 1974 if ((ESP_READ_REG(sc, ESP_FFLAG)&ESPFIFO_FF) == 0) { 1975 /* Hope for the best.. */ 1976 break; 1977 } 1978 printf("(%s:%d:%d): selection failed;" 1979 " %d left in FIFO " 1980 "[intr %x, stat %x, step %d]\n", 1981 sc->sc_dev.dv_xname, 1982 sc_link->target, 1983 sc_link->lun, 1984 ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF, 1985 sc->sc_espintr, sc->sc_espstat, 1986 sc->sc_espstep); 1987 ESPCMD(sc, ESPCMD_FLUSH); 1988 esp_sched_msgout(SEND_ABORT); 1989 return 1; 1990 case 2: 1991 /* Select stuck at Command Phase */ 1992 ESPCMD(sc, ESPCMD_FLUSH); 1993 case 4: 1994 /* So far, everything went fine */ 1995 break; 1996 } 1997 #if 0 1998 if (ecb->xs->flags & SCSI_RESET) 1999 esp_sched_msgout(SEND_DEV_RESET); 2000 else if (ti->flags & T_NEGOTIATE) 2001 esp_sched_msgout( 2002 SEND_IDENTIFY | SEND_SDTR); 2003 else 2004 esp_sched_msgout(SEND_IDENTIFY); 2005 #endif 2006 2007 ecb->flags |= ECB_NEXUS; 2008 ti->lubusy |= (1 << sc_link->lun); 2009 2010 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 2011 /* Do an implicit RESTORE POINTERS. */ 2012 sc->sc_dp = ecb->daddr; 2013 sc->sc_dleft = ecb->dleft; 2014 2015 /* On our first connection, schedule a timeout. */ 2016 if ((ecb->xs->flags & SCSI_POLL) == 0) 2017 timeout(esp_timeout, ecb, (ecb->timeout * hz) / 1000); 2018 2019 sc->sc_state = ESP_CONNECTED; 2020 break; 2021 } else { 2022 printf("%s: unexpected status after select" 2023 ": [intr %x, stat %x, step %x]\n", 2024 sc->sc_dev.dv_xname, 2025 sc->sc_espintr, sc->sc_espstat, 2026 sc->sc_espstep); 2027 ESPCMD(sc, ESPCMD_FLUSH); 2028 DELAY(1); 2029 goto reset; 2030 } 2031 if (sc->sc_state == ESP_IDLE) { 2032 printf("%s: stray interrupt\n", sc->sc_dev.dv_xname); 2033 return 0; 2034 } 2035 break; 2036 2037 case ESP_CONNECTED: 2038 if (sc->sc_flags & ESP_ICCS) { 2039 u_char msg; 2040 2041 sc->sc_flags &= ~ESP_ICCS; 2042 2043 if (!(sc->sc_espintr & ESPINTR_DONE)) { 2044 printf("%s: ICCS: " 2045 ": [intr %x, stat %x, step %x]\n", 2046 sc->sc_dev.dv_xname, 2047 sc->sc_espintr, sc->sc_espstat, 2048 sc->sc_espstep); 2049 } 2050 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 2051 int i = (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) - 2; 2052 while (i--) 2053 (void) ESP_READ_REG(sc, ESP_FIFO); 2054 } 2055 ecb->stat = ESP_READ_REG(sc, ESP_FIFO); 2056 msg = ESP_READ_REG(sc, ESP_FIFO); 2057 ESP_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 2058 if (msg == MSG_CMDCOMPLETE) { 2059 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 2060 sc->sc_state = ESP_CMDCOMPLETE; 2061 } else 2062 printf("%s: STATUS_PHASE: msg %d\n", 2063 sc->sc_dev.dv_xname, msg); 2064 ESPCMD(sc, ESPCMD_MSGOK); 2065 continue; /* ie. wait for disconnect */ 2066 } 2067 break; 2068 default: 2069 panic("%s: invalid state: %d", 2070 sc->sc_dev.dv_xname, 2071 sc->sc_state); 2072 } 2073 2074 /* 2075 * Driver is now in state ESP_CONNECTED, i.e. we 2076 * have a current command working the SCSI bus. 2077 */ 2078 if (sc->sc_state != ESP_CONNECTED || ecb == NULL) { 2079 panic("esp no nexus"); 2080 } 2081 2082 switch (sc->sc_phase) { 2083 case MESSAGE_OUT_PHASE: 2084 ESP_PHASE(("MESSAGE_OUT_PHASE ")); 2085 esp_msgout(sc); 2086 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2087 break; 2088 case MESSAGE_IN_PHASE: 2089 ESP_PHASE(("MESSAGE_IN_PHASE ")); 2090 if (sc->sc_espintr & ESPINTR_BS) { 2091 ESPCMD(sc, ESPCMD_FLUSH); 2092 sc->sc_flags |= ESP_WAITI; 2093 ESPCMD(sc, ESPCMD_TRANS); 2094 } else if (sc->sc_espintr & ESPINTR_FC) { 2095 if ((sc->sc_flags & ESP_WAITI) == 0) { 2096 printf("%s: MSGIN: unexpected FC bit: " 2097 "[intr %x, stat %x, step %x]\n", 2098 sc->sc_dev.dv_xname, 2099 sc->sc_espintr, sc->sc_espstat, 2100 sc->sc_espstep); 2101 } 2102 sc->sc_flags &= ~ESP_WAITI; 2103 esp_msgin(sc); 2104 } else { 2105 printf("%s: MSGIN: weird bits: " 2106 "[intr %x, stat %x, step %x]\n", 2107 sc->sc_dev.dv_xname, 2108 sc->sc_espintr, sc->sc_espstat, 2109 sc->sc_espstep); 2110 } 2111 sc->sc_prevphase = MESSAGE_IN_PHASE; 2112 break; 2113 case COMMAND_PHASE: { 2114 /* well, this means send the command again */ 2115 u_char *cmd = (u_char *)&ecb->cmd; 2116 int i; 2117 2118 ESP_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2119 ecb->cmd.opcode, ecb->clen)); 2120 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 2121 ESPCMD(sc, ESPCMD_FLUSH); 2122 DELAY(1); 2123 } 2124 /* Now the command into the FIFO */ 2125 for (i = 0; i < ecb->clen; i++) 2126 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 2127 ESPCMD(sc, ESPCMD_TRANS); 2128 sc->sc_prevphase = COMMAND_PHASE; 2129 } 2130 break; 2131 case DATA_OUT_PHASE: 2132 ESP_PHASE(("DATA_OUT_PHASE [%d] ", sc->sc_dleft)); 2133 ESPCMD(sc, ESPCMD_FLUSH); 2134 size = min(sc->sc_dleft, sc->sc_maxxfer); 2135 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2136 0, &size); 2137 sc->sc_prevphase = DATA_OUT_PHASE; 2138 goto setup_xfer; 2139 case DATA_IN_PHASE: 2140 ESP_PHASE(("DATA_IN_PHASE ")); 2141 if (sc->sc_rev == ESP100) 2142 ESPCMD(sc, ESPCMD_FLUSH); 2143 size = min(sc->sc_dleft, sc->sc_maxxfer); 2144 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2145 1, &size); 2146 sc->sc_prevphase = DATA_IN_PHASE; 2147 setup_xfer: 2148 #ifdef MAC68K_DRIVER 2149 if (!size) { 2150 #endif 2151 /* Program the SCSI counter */ 2152 ESP_WRITE_REG(sc, ESP_TCL, size); 2153 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 2154 if (sc->sc_cfg2 & ESPCFG2_FE) { 2155 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 2156 } 2157 /* load the count in */ 2158 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 2159 #ifdef MAC68K_DRIVER 2160 } 2161 #endif 2162 2163 /* 2164 * Note that if `size' is 0, we've already transceived 2165 * all the bytes we want but we're still in DATA PHASE. 2166 * Apparently, the device needs padding. Also, a 2167 * transfer size of 0 means "maximum" to the chip 2168 * DMA logic. 2169 */ 2170 ESPCMD(sc, 2171 (size==0?ESPCMD_TRPAD:ESPCMD_TRANS)|ESPCMD_DMA); 2172 DMA_GO(sc->sc_dma); 2173 return 1; 2174 case STATUS_PHASE: 2175 ESP_PHASE(("STATUS_PHASE ")); 2176 sc->sc_flags |= ESP_ICCS; 2177 ESPCMD(sc, ESPCMD_ICCS); 2178 sc->sc_prevphase = STATUS_PHASE; 2179 break; 2180 case INVALID_PHASE: 2181 break; 2182 default: 2183 printf("%s: unexpected bus phase; resetting\n", 2184 sc->sc_dev.dv_xname); 2185 goto reset; 2186 } 2187 } 2188 panic("esp: should not get here.."); 2189 2190 reset: 2191 esp_init(sc, 1); 2192 return 1; 2193 2194 finish: 2195 untimeout(esp_timeout, ecb); 2196 esp_done(sc, ecb); 2197 goto out; 2198 2199 sched: 2200 sc->sc_state = ESP_IDLE; 2201 esp_sched(sc); 2202 goto out; 2203 2204 out: 2205 return 1; 2206 } 2207 2208 void 2209 esp_abort(sc, ecb) 2210 struct esp_softc *sc; 2211 struct esp_ecb *ecb; 2212 { 2213 2214 /* 2 secs for the abort */ 2215 ecb->timeout = ESP_ABORT_TIMEOUT; 2216 ecb->flags |= ECB_ABORT; 2217 2218 if (ecb == sc->sc_nexus) { 2219 /* 2220 * If we're still selecting, the message will be scheduled 2221 * after selection is complete. 2222 */ 2223 if (sc->sc_state == ESP_CONNECTED) 2224 esp_sched_msgout(SEND_ABORT); 2225 } else { 2226 esp_dequeue(sc, ecb); 2227 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2228 if (sc->sc_state == ESP_IDLE) 2229 esp_sched(sc); 2230 } 2231 } 2232 2233 void 2234 esp_timeout(arg) 2235 void *arg; 2236 { 2237 struct esp_ecb *ecb = arg; 2238 struct scsi_xfer *xs = ecb->xs; 2239 struct scsi_link *sc_link = xs->sc_link; 2240 struct esp_softc *sc = sc_link->adapter_softc; 2241 int s; 2242 2243 sc_print_addr(sc_link); 2244 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2245 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) %s>", 2246 sc->sc_dev.dv_xname, 2247 ecb, ecb->flags, ecb->dleft, ecb->stat, 2248 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2249 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2250 DMA_ISACTIVE(sc->sc_dma) ? "DMA active" : ""); 2251 #if ESP_DEBUG > 0 2252 printf("TRACE: %s.", ecb->trace); 2253 #endif 2254 2255 s = splbio(); 2256 2257 if (ecb->flags & ECB_ABORT) { 2258 /* abort timed out */ 2259 printf(" AGAIN\n"); 2260 esp_init(sc, 1); 2261 } else { 2262 /* abort the operation that has timed out */ 2263 printf("\n"); 2264 xs->error = XS_TIMEOUT; 2265 esp_abort(sc, ecb); 2266 } 2267 2268 splx(s); 2269 } 2270
Indexes created Tue Oct 21 05:10:09 GMT 2025