esp.c revision 1.35
1 /* $NetBSD: esp.c,v 1.35 2003/07/15 02:43:25 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Jason R. Thorpe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project 18 * by Jason R. Thorpe. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1994 Peter Galbavy 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Peter Galbavy 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 54 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 55 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 56 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 57 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 58 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 60 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 61 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Based on aic6360 by Jarle Greipsland 67 * 68 * Acknowledgements: Many of the algorithms used in this driver are 69 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 70 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 71 */ 72 73 /* 74 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 75 * (basically consisting of the match, a bit of the attach, and the 76 * "DMA" glue functions). 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.35 2003/07/15 02:43:25 lukem Exp $"); 81 82 #include <sys/types.h> 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/kernel.h> 86 #include <sys/errno.h> 87 #include <sys/ioctl.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 #include <sys/queue.h> 93 94 #include <dev/scsipi/scsi_all.h> 95 #include <dev/scsipi/scsipi_all.h> 96 #include <dev/scsipi/scsiconf.h> 97 #include <dev/scsipi/scsi_message.h> 98 99 #include <machine/cpu.h> 100 #include <machine/bus.h> 101 #include <machine/param.h> 102 103 #include <dev/ic/ncr53c9xreg.h> 104 #include <dev/ic/ncr53c9xvar.h> 105 106 #include <machine/viareg.h> 107 108 #include <mac68k/obio/espvar.h> 109 #include <mac68k/obio/obiovar.h> 110 111 void espattach __P((struct device *, struct device *, void *)); 112 int espmatch __P((struct device *, struct cfdata *, void *)); 113 114 /* Linkup to the rest of the kernel */ 115 CFATTACH_DECL(esp, sizeof(struct esp_softc), 116 espmatch, espattach, NULL, NULL); 117 118 /* 119 * Functions and the switch for the MI code. 120 */ 121 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 122 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 123 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 124 void esp_dma_reset __P((struct ncr53c9x_softc *)); 125 int esp_dma_intr __P((struct ncr53c9x_softc *)); 126 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 127 size_t *, int, size_t *)); 128 void esp_dma_go __P((struct ncr53c9x_softc *)); 129 void esp_dma_stop __P((struct ncr53c9x_softc *)); 130 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 131 void esp_quick_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 132 int esp_quick_dma_intr __P((struct ncr53c9x_softc *)); 133 int esp_quick_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 134 size_t *, int, size_t *)); 135 void esp_quick_dma_go __P((struct ncr53c9x_softc *)); 136 137 void esp_intr __P((void *sc)); 138 void esp_dualbus_intr __P((void *sc)); 139 static struct esp_softc *esp0 = NULL, *esp1 = NULL; 140 141 static __inline__ int esp_dafb_have_dreq __P((struct esp_softc *esc)); 142 static __inline__ int esp_iosb_have_dreq __P((struct esp_softc *esc)); 143 int (*esp_have_dreq) __P((struct esp_softc *esc)); 144 145 struct ncr53c9x_glue esp_glue = { 146 esp_read_reg, 147 esp_write_reg, 148 esp_dma_isintr, 149 esp_dma_reset, 150 esp_dma_intr, 151 esp_dma_setup, 152 esp_dma_go, 153 esp_dma_stop, 154 esp_dma_isactive, 155 NULL, /* gl_clear_latched_intr */ 156 }; 157 158 int 159 espmatch(parent, cf, aux) 160 struct device *parent; 161 struct cfdata *cf; 162 void *aux; 163 { 164 int found = 0; 165 166 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) { 167 found = 1; 168 } 169 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) { 170 found = 1; 171 } 172 173 return found; 174 } 175 176 /* 177 * Attach this instance, and then all the sub-devices 178 */ 179 void 180 espattach(parent, self, aux) 181 struct device *parent, *self; 182 void *aux; 183 { 184 struct obio_attach_args *oa = (struct obio_attach_args *)aux; 185 extern vaddr_t SCSIBase; 186 struct esp_softc *esc = (void *)self; 187 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 188 int quick = 0; 189 unsigned long reg_offset; 190 191 reg_offset = SCSIBase - IOBase; 192 esc->sc_tag = oa->oa_tag; 193 /* 194 * For Wombat, Primus and Optimus motherboards, DREQ is 195 * visible on bit 0 of the IOSB's emulated VIA2 vIFR (and 196 * the scsi registers are offset 0x1000 bytes from IOBase). 197 * 198 * For the Q700/900/950 it's at f9800024 for bus 0 and 199 * f9800028 for bus 1 (900/950). For these machines, that is also 200 * a (12-bit) configuration register for DAFB's control of the 201 * pseudo-DMA timing. The default value is 0x1d1. 202 */ 203 esp_have_dreq = esp_dafb_have_dreq; 204 if (sc->sc_dev.dv_unit == 0) { 205 if (reg_offset == 0x10000) { 206 quick = 1; 207 esp_have_dreq = esp_iosb_have_dreq; 208 } else if (reg_offset == 0x18000) { 209 quick = 0; 210 } else { 211 if (bus_space_map(esc->sc_tag, 0xf9800024, 212 4, 0, &esc->sc_bsh)) { 213 printf("failed to map 4 at 0xf9800024.\n"); 214 } else { 215 quick = 1; 216 bus_space_write_4(esc->sc_tag, 217 esc->sc_bsh, 0, 0x1d1); 218 } 219 } 220 } else { 221 if (bus_space_map(esc->sc_tag, 0xf9800028, 222 4, 0, &esc->sc_bsh)) { 223 printf("failed to map 4 at 0xf9800028.\n"); 224 } else { 225 quick = 1; 226 bus_space_write_4(esc->sc_tag, esc->sc_bsh, 0, 0x1d1); 227 } 228 } 229 if (quick) { 230 esp_glue.gl_write_reg = esp_quick_write_reg; 231 esp_glue.gl_dma_intr = esp_quick_dma_intr; 232 esp_glue.gl_dma_setup = esp_quick_dma_setup; 233 esp_glue.gl_dma_go = esp_quick_dma_go; 234 } 235 236 /* 237 * Set up the glue for MI code early; we use some of it here. 238 */ 239 sc->sc_glue = &esp_glue; 240 241 /* 242 * Save the regs 243 */ 244 if (sc->sc_dev.dv_unit == 0) { 245 esp0 = esc; 246 247 esc->sc_reg = (volatile u_char *) SCSIBase; 248 via2_register_irq(VIA2_SCSIIRQ, esp_intr, esc); 249 esc->irq_mask = V2IF_SCSIIRQ; 250 if (reg_offset == 0x10000) { 251 /* From the Q650 developer's note */ 252 sc->sc_freq = 16500000; 253 } else { 254 sc->sc_freq = 25000000; 255 } 256 257 if (esp_glue.gl_dma_go == esp_quick_dma_go) { 258 printf(" (quick)"); 259 } 260 } else { 261 esp1 = esc; 262 263 esc->sc_reg = (volatile u_char *) SCSIBase + 0x402; 264 via2_register_irq(VIA2_SCSIIRQ, esp_dualbus_intr, NULL); 265 esc->irq_mask = 0; 266 sc->sc_freq = 25000000; 267 268 if (esp_glue.gl_dma_go == esp_quick_dma_go) { 269 printf(" (quick)"); 270 } 271 } 272 273 printf(": address %p", esc->sc_reg); 274 275 sc->sc_id = 7; 276 277 /* gimme Mhz */ 278 sc->sc_freq /= 1000000; 279 280 /* 281 * It is necessary to try to load the 2nd config register here, 282 * to find out what rev the esp chip is, else the esp_reset 283 * will not set up the defaults correctly. 284 */ 285 sc->sc_cfg1 = sc->sc_id; /* | NCRCFG1_PARENB; */ 286 sc->sc_cfg2 = NCRCFG2_SCSI2; 287 sc->sc_cfg3 = 0; 288 sc->sc_rev = NCR_VARIANT_NCR53C96; 289 290 /* 291 * This is the value used to start sync negotiations 292 * Note that the NCR register "SYNCTP" is programmed 293 * in "clocks per byte", and has a minimum value of 4. 294 * The SCSI period used in negotiation is one-fourth 295 * of the time (in nanoseconds) needed to transfer one byte. 296 * Since the chip's clock is given in MHz, we have the following 297 * formula: 4 * period = (1000 / freq) * 4 298 */ 299 sc->sc_minsync = 1000 / sc->sc_freq; 300 301 /* We need this to fit into the TCR... */ 302 sc->sc_maxxfer = 64 * 1024; 303 304 if (!quick) { 305 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */ 306 sc->sc_maxxfer = 8 * 1024; 307 } 308 309 /* 310 * Configure interrupts. 311 */ 312 if (esc->irq_mask) { 313 via2_reg(vPCR) = 0x22; 314 via2_reg(vIFR) = esc->irq_mask; 315 via2_reg(vIER) = 0x80 | esc->irq_mask; 316 } 317 318 /* 319 * Now try to attach all the sub-devices 320 */ 321 sc->sc_adapter.adapt_minphys = minphys; 322 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 323 ncr53c9x_attach(sc); 324 } 325 326 /* 327 * Glue functions. 328 */ 329 330 u_char 331 esp_read_reg(sc, reg) 332 struct ncr53c9x_softc *sc; 333 int reg; 334 { 335 struct esp_softc *esc = (struct esp_softc *)sc; 336 337 return esc->sc_reg[reg * 16]; 338 } 339 340 void 341 esp_write_reg(sc, reg, val) 342 struct ncr53c9x_softc *sc; 343 int reg; 344 u_char val; 345 { 346 struct esp_softc *esc = (struct esp_softc *)sc; 347 u_char v = val; 348 349 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 350 v = NCRCMD_TRANS; 351 } 352 esc->sc_reg[reg * 16] = v; 353 } 354 355 void 356 esp_dma_stop(sc) 357 struct ncr53c9x_softc *sc; 358 { 359 } 360 361 int 362 esp_dma_isactive(sc) 363 struct ncr53c9x_softc *sc; 364 { 365 struct esp_softc *esc = (struct esp_softc *)sc; 366 367 return esc->sc_active; 368 } 369 370 int 371 esp_dma_isintr(sc) 372 struct ncr53c9x_softc *sc; 373 { 374 struct esp_softc *esc = (struct esp_softc *)sc; 375 376 return esc->sc_reg[NCR_STAT * 16] & 0x80; 377 } 378 379 void 380 esp_dma_reset(sc) 381 struct ncr53c9x_softc *sc; 382 { 383 struct esp_softc *esc = (struct esp_softc *)sc; 384 385 esc->sc_active = 0; 386 esc->sc_tc = 0; 387 } 388 389 int 390 esp_dma_intr(sc) 391 struct ncr53c9x_softc *sc; 392 { 393 struct esp_softc *esc = (struct esp_softc *)sc; 394 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 395 u_char *p; 396 u_int espphase, espstat, espintr; 397 int cnt, s; 398 399 if (esc->sc_active == 0) { 400 printf("dma_intr--inactive DMA\n"); 401 return -1; 402 } 403 404 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 405 esc->sc_active = 0; 406 return 0; 407 } 408 409 cnt = *esc->sc_dmalen; 410 if (*esc->sc_dmalen == 0) { 411 printf("data interrupt, but no count left."); 412 } 413 414 p = *esc->sc_dmaaddr; 415 espphase = sc->sc_phase; 416 espstat = (u_int) sc->sc_espstat; 417 espintr = (u_int) sc->sc_espintr; 418 cmdreg = esc->sc_reg + NCR_CMD * 16; 419 fiforeg = esc->sc_reg + NCR_FIFO * 16; 420 statreg = esc->sc_reg + NCR_STAT * 16; 421 intrreg = esc->sc_reg + NCR_INTR * 16; 422 do { 423 if (esc->sc_datain) { 424 *p++ = *fiforeg; 425 cnt--; 426 if (espphase == DATA_IN_PHASE) { 427 *cmdreg = NCRCMD_TRANS; 428 } else { 429 esc->sc_active = 0; 430 } 431 } else { 432 if ( (espphase == DATA_OUT_PHASE) 433 || (espphase == MESSAGE_OUT_PHASE)) { 434 *fiforeg = *p++; 435 cnt--; 436 *cmdreg = NCRCMD_TRANS; 437 } else { 438 esc->sc_active = 0; 439 } 440 } 441 442 if (esc->sc_active) { 443 while (!(*statreg & 0x80)); 444 s = splhigh(); 445 espstat = *statreg; 446 espintr = *intrreg; 447 espphase = (espintr & NCRINTR_DIS) 448 ? /* Disconnected */ BUSFREE_PHASE 449 : espstat & PHASE_MASK; 450 splx(s); 451 } 452 } while (esc->sc_active && (espintr & NCRINTR_BS)); 453 sc->sc_phase = espphase; 454 sc->sc_espstat = (u_char) espstat; 455 sc->sc_espintr = (u_char) espintr; 456 *esc->sc_dmaaddr = p; 457 *esc->sc_dmalen = cnt; 458 459 if (*esc->sc_dmalen == 0) { 460 esc->sc_tc = NCRSTAT_TC; 461 } 462 sc->sc_espstat |= esc->sc_tc; 463 return 0; 464 } 465 466 int 467 esp_dma_setup(sc, addr, len, datain, dmasize) 468 struct ncr53c9x_softc *sc; 469 caddr_t *addr; 470 size_t *len; 471 int datain; 472 size_t *dmasize; 473 { 474 struct esp_softc *esc = (struct esp_softc *)sc; 475 476 esc->sc_dmaaddr = addr; 477 esc->sc_dmalen = len; 478 esc->sc_datain = datain; 479 esc->sc_dmasize = *dmasize; 480 esc->sc_tc = 0; 481 482 return 0; 483 } 484 485 void 486 esp_dma_go(sc) 487 struct ncr53c9x_softc *sc; 488 { 489 struct esp_softc *esc = (struct esp_softc *)sc; 490 491 if (esc->sc_datain == 0) { 492 esc->sc_reg[NCR_FIFO * 16] = **esc->sc_dmaaddr; 493 (*esc->sc_dmalen)--; 494 (*esc->sc_dmaaddr)++; 495 } 496 esc->sc_active = 1; 497 } 498 499 void 500 esp_quick_write_reg(sc, reg, val) 501 struct ncr53c9x_softc *sc; 502 int reg; 503 u_char val; 504 { 505 struct esp_softc *esc = (struct esp_softc *)sc; 506 507 esc->sc_reg[reg * 16] = val; 508 } 509 510 #if DEBUG 511 int mac68k_esp_debug=0; 512 #endif 513 514 int 515 esp_quick_dma_intr(sc) 516 struct ncr53c9x_softc *sc; 517 { 518 struct esp_softc *esc = (struct esp_softc *)sc; 519 int trans=0, resid=0; 520 521 if (esc->sc_active == 0) 522 panic("dma_intr--inactive DMA"); 523 524 esc->sc_active = 0; 525 526 if (esc->sc_dmasize == 0) { 527 int res; 528 529 res = NCR_READ_REG(sc, NCR_TCL); 530 res += NCR_READ_REG(sc, NCR_TCM) << 8; 531 /* This can happen in the case of a TRPAD operation */ 532 /* Pretend that it was complete */ 533 sc->sc_espstat |= NCRSTAT_TC; 534 #if DEBUG 535 if (mac68k_esp_debug) { 536 printf("dmaintr: DMA xfer of zero xferred %d\n", 537 65536 - res); 538 } 539 #endif 540 return 0; 541 } 542 543 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 544 if (esc->sc_datain == 0) { 545 resid = NCR_READ_REG(sc, NCR_FFLAG) & 0x1f; 546 #if DEBUG 547 if (mac68k_esp_debug) { 548 printf("Write FIFO residual %d bytes\n", resid); 549 } 550 #endif 551 } 552 resid += NCR_READ_REG(sc, NCR_TCL); 553 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 554 if (resid == 0) 555 resid = 65536; 556 } 557 558 trans = esc->sc_dmasize - resid; 559 if (trans < 0) { 560 printf("dmaintr: trans < 0????"); 561 trans = *esc->sc_dmalen; 562 } 563 564 NCR_DMA(("dmaintr: trans %d, resid %d.\n", trans, resid)); 565 #if DEBUG 566 if (mac68k_esp_debug) { 567 printf("eqd_intr: trans %d, resid %d.\n", trans, resid); 568 } 569 #endif 570 *esc->sc_dmaaddr += trans; 571 *esc->sc_dmalen -= trans; 572 573 return 0; 574 } 575 576 int 577 esp_quick_dma_setup(sc, addr, len, datain, dmasize) 578 struct ncr53c9x_softc *sc; 579 caddr_t *addr; 580 size_t *len; 581 int datain; 582 size_t *dmasize; 583 { 584 struct esp_softc *esc = (struct esp_softc *)sc; 585 586 esc->sc_dmaaddr = addr; 587 esc->sc_dmalen = len; 588 589 if (*len & 1) { 590 esc->sc_pad = 1; 591 } else { 592 esc->sc_pad = 0; 593 } 594 595 esc->sc_datain = datain; 596 esc->sc_dmasize = *dmasize; 597 598 #if DIAGNOSTIC 599 if (esc->sc_dmasize == 0) { 600 /* This can happen in the case of a TRPAD operation */ 601 } 602 #endif 603 #if DEBUG 604 if (mac68k_esp_debug) { 605 printf("eqd_setup: addr %lx, len %lx, in? %d, dmasize %lx\n", 606 (long) *addr, (long) *len, datain, (long) esc->sc_dmasize); 607 } 608 #endif 609 610 return 0; 611 } 612 613 static __inline__ int 614 esp_dafb_have_dreq(esc) 615 struct esp_softc *esc; 616 { 617 return (*(volatile u_int32_t *)(esc->sc_bsh.base) & 0x200); 618 } 619 620 static __inline__ int 621 esp_iosb_have_dreq(esc) 622 struct esp_softc *esc; 623 { 624 return (via2_reg(vIFR) & V2IF_SCSIDRQ); 625 } 626 627 static volatile int espspl=-1; 628 629 /* 630 * Apple "DMA" is weird. 631 * 632 * Basically, the CPU acts like the DMA controller. The DREQ/ off the 633 * chip goes to a register that we've mapped at attach time (on the 634 * IOSB or DAFB, depending on the machine). Apple also provides some 635 * space for which the memory controller handshakes data to/from the 636 * NCR chip with the DACK/ line. This space appears to be mapped over 637 * and over, every 4 bytes, but only the lower 16 bits are valid (but 638 * reading the upper 16 bits will handshake DACK/ just fine, so if you 639 * read *u_int16_t++ = *u_int16_t++ in a loop, you'll get 640 * <databyte><databyte>0xff0xff<databyte><databyte>0xff0xff... 641 * 642 * When you're attempting to read or write memory to this DACK/ed space, 643 * and the NCR is not ready for some timeout period, the system will 644 * generate a bus error. This might be for one of several reasons: 645 * 646 * 1) (on write) The FIFO is full and is not draining. 647 * 2) (on read) The FIFO is empty and is not filling. 648 * 3) An interrupt condition has occurred. 649 * 4) Anything else? 650 * 651 * So if a bus error occurs, we first turn off the nofault bus error handler, 652 * then we check for an interrupt (which would render the first two 653 * possibilities moot). If there's no interrupt, check for a DREQ/. If we 654 * have that, then attempt to resume stuffing (or unstuffing) the FIFO. If 655 * neither condition holds, pause briefly and check again. 656 * 657 * NOTE!!! In order to make allowances for the hardware structure of 658 * the mac, spl values in here are hardcoded!!!!!!!!! 659 * This is done to allow serial interrupts to get in during 660 * scsi transfers. This is ugly. 661 */ 662 void 663 esp_quick_dma_go(sc) 664 struct ncr53c9x_softc *sc; 665 { 666 struct esp_softc *esc = (struct esp_softc *)sc; 667 extern long mac68k_a2_fromfault; 668 extern int *nofault; 669 label_t faultbuf; 670 u_int16_t volatile *pdma; 671 u_int16_t *addr; 672 int len, res; 673 u_short cnt32, cnt2; 674 u_char volatile *statreg; 675 676 esc->sc_active = 1; 677 678 espspl = splhigh(); 679 680 addr = (u_int16_t *) *esc->sc_dmaaddr; 681 len = esc->sc_dmasize; 682 683 restart_dmago: 684 #if DEBUG 685 if (mac68k_esp_debug) { 686 printf("eqdg: a %lx, l %lx, in? %d ... ", 687 (long) addr, (long) len, esc->sc_datain); 688 } 689 #endif 690 nofault = (int *) &faultbuf; 691 if (setjmp((label_t *) nofault)) { 692 int i=0; 693 694 nofault = (int *) 0; 695 #if DEBUG 696 if (mac68k_esp_debug) { 697 printf("be\n"); 698 } 699 #endif 700 /* 701 * Bus error... 702 * So, we first check for an interrupt. If we have 703 * one, go handle it. Next we check for DREQ/. If 704 * we have it, then we restart the transfer. If 705 * neither, then loop until we get one or the other. 706 */ 707 statreg = esc->sc_reg + NCR_STAT * 16; 708 for (;;) { 709 spl2(); /* Give serial a chance... */ 710 splhigh(); /* That's enough... */ 711 712 if (*statreg & 0x80) { 713 goto gotintr; 714 } 715 716 if (esp_have_dreq(esc)) { 717 /* 718 * Get the remaining length from the address 719 * differential. 720 */ 721 addr = (u_int16_t *) mac68k_a2_fromfault; 722 len = esc->sc_dmasize - 723 ((long) addr - (long) *esc->sc_dmaaddr); 724 725 if (esc->sc_datain == 0) { 726 /* 727 * Let the FIFO drain before we read 728 * the transfer count. 729 * Do we need to do this? 730 * Can we do this? 731 */ 732 while (NCR_READ_REG(sc, NCR_FFLAG) 733 & 0x1f); 734 /* 735 * Get the length from the transfer 736 * counters. 737 */ 738 res = NCR_READ_REG(sc, NCR_TCL); 739 res += NCR_READ_REG(sc, NCR_TCM) << 8; 740 /* 741 * If they don't agree, 742 * adjust accordingly. 743 */ 744 while (res > len) { 745 len+=2; addr--; 746 } 747 if (res != len) { 748 panic("esp_quick_dma_go: res %d != len %d", 749 res, len); 750 } 751 } 752 break; 753 } 754 755 DELAY(1); 756 if (i++ > 1000000) 757 panic("esp_dma_go: Bus error, but no condition! Argh!"); 758 } 759 goto restart_dmago; 760 } 761 762 len &= ~1; 763 764 statreg = esc->sc_reg + NCR_STAT * 16; 765 pdma = (u_int16_t *) (esc->sc_reg + 0x100); 766 767 /* 768 * These loops are unrolled into assembly for two reasons: 769 * 1) We can make sure that they are as efficient as possible, and 770 * 2) (more importantly) we need the address that we are reading 771 * from or writing to to be in a2. 772 */ 773 cnt32 = len / 32; 774 cnt2 = (len % 32) / 2; 775 if (esc->sc_datain == 0) { 776 /* while (cnt32--) { 16 instances of *pdma = *addr++; } */ 777 /* while (cnt2--) { *pdma = *addr++; } */ 778 __asm __volatile ( 779 " movl %1, %%a2 \n" 780 " movl %2, %%a3 \n" 781 " movw %3, %%d2 \n" 782 " cmpw #0, %%d2 \n" 783 " beq 2f \n" 784 " subql #1, %%d2 \n" 785 "1: movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n" 786 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n" 787 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n" 788 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n" 789 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n" 790 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n" 791 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n" 792 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n" 793 " movw #8704,%%sr \n" 794 " movw #9728,%%sr \n" 795 " dbra %%d2, 1b \n" 796 "2: movw %4, %%d2 \n" 797 " cmpw #0, %%d2 \n" 798 " beq 4f \n" 799 " subql #1, %%d2 \n" 800 "3: movw %%a2@+,%%a3@ \n" 801 " dbra %%d2, 3b \n" 802 "4: movl %%a2, %0" 803 : "=g" (addr) 804 : "0" (addr), "g" (pdma), "g" (cnt32), "g" (cnt2) 805 : "a2", "a3", "d2"); 806 if (esc->sc_pad) { 807 unsigned char *c; 808 c = (unsigned char *) addr; 809 /* Wait for DREQ */ 810 while (!esp_have_dreq(esc)) { 811 if (*statreg & 0x80) { 812 nofault = (int *) 0; 813 goto gotintr; 814 } 815 } 816 *(unsigned char *)pdma = *c; 817 } 818 } else { 819 /* while (cnt32--) { 16 instances of *addr++ = *pdma; } */ 820 /* while (cnt2--) { *addr++ = *pdma; } */ 821 __asm __volatile ( 822 " movl %1, %%a2 \n" 823 " movl %2, %%a3 \n" 824 " movw %3, %%d2 \n" 825 " cmpw #0, %%d2 \n" 826 " beq 6f \n" 827 " subql #1, %%d2 \n" 828 "5: movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n" 829 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n" 830 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n" 831 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n" 832 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n" 833 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n" 834 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n" 835 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n" 836 " movw #8704,%%sr \n" 837 " movw #9728,%%sr \n" 838 " dbra %%d2, 5b \n" 839 "6: movw %4, %%d2 \n" 840 " cmpw #0, %%d2 \n" 841 " beq 8f \n" 842 " subql #1, %%d2 \n" 843 "7: movw %%a3@,%%a2@+ \n" 844 " dbra %%d2, 7b \n" 845 "8: movl %%a2, %0" 846 : "=g" (addr) 847 : "0" (addr), "g" (pdma), "g" (cnt32), "g" (cnt2) 848 : "a2", "a3", "d2"); 849 if (esc->sc_pad) { 850 unsigned char *c; 851 c = (unsigned char *) addr; 852 /* Wait for DREQ */ 853 while (!esp_have_dreq(esc)) { 854 if (*statreg & 0x80) { 855 nofault = (int *) 0; 856 goto gotintr; 857 } 858 } 859 *c = *(unsigned char *)pdma; 860 } 861 } 862 863 nofault = (int *) 0; 864 865 /* 866 * If we have not received an interrupt yet, we should shortly, 867 * and we can't prevent it, so return and wait for it. 868 */ 869 if ((*statreg & 0x80) == 0) { 870 #if DEBUG 871 if (mac68k_esp_debug) { 872 printf("g.\n"); 873 } 874 #endif 875 if (espspl != -1) splx(espspl); espspl = -1; 876 return; 877 } 878 879 gotintr: 880 #if DEBUG 881 if (mac68k_esp_debug) { 882 printf("g!\n"); 883 } 884 #endif 885 ncr53c9x_intr(sc); 886 if (espspl != -1) splx(espspl); espspl = -1; 887 } 888 889 void 890 esp_intr(sc) 891 void *sc; 892 { 893 struct esp_softc *esc = (struct esp_softc *)sc; 894 895 if (esc->sc_reg[NCR_STAT * 16] & 0x80) { 896 ncr53c9x_intr((struct ncr53c9x_softc *) esp0); 897 } 898 } 899 900 void 901 esp_dualbus_intr(sc) 902 void *sc; 903 { 904 if (esp0 && (esp0->sc_reg[NCR_STAT * 16] & 0x80)) { 905 ncr53c9x_intr((struct ncr53c9x_softc *) esp0); 906 } 907 908 if (esp1 && (esp1->sc_reg[NCR_STAT * 16] & 0x80)) { 909 ncr53c9x_intr((struct ncr53c9x_softc *) esp1); 910 } 911 } 912
Indexes created Sun Sep 28 07:09:56 GMT 2025