esp.c revision 1.4
1 /* $NetBSD: esp.c,v 1.4 1996/11/04 21:20:01 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <scsi/scsi_all.h> 85 #include <scsi/scsiconf.h> 86 #include <scsi/scsi_message.h> 87 88 #include <machine/cpu.h> 89 #include <machine/param.h> 90 91 #if defined(__sparc__) 92 #define SPARC_DRIVER 93 #include <machine/autoconf.h> 94 #include <sparc/dev/sbusvar.h> 95 #include <sparc/dev/dmareg.h> 96 #include <sparc/dev/dmavar.h> 97 #include <sparc/dev/espreg.h> 98 #include <sparc/dev/espvar.h> 99 #else 100 #if (_MACHINE == mac68k) 101 #define MAC68K_DRIVER 102 #include <machine/viareg.h> 103 104 struct dma_softc { 105 struct esp_softc *sc_esp; 106 int sc_active; 107 int sc_tc; 108 int sc_datain; 109 size_t sc_dmasize; 110 size_t sc_dmatrans; 111 char **sc_dmaaddr; 112 size_t *sc_pdmalen; 113 }; 114 115 #include <mac68k/dev/espreg.h> 116 #include <mac68k/dev/espvar.h> 117 #undef ESPCMD_DMA 118 #define ESPCMD_DMA 0 /* No DMA */ 119 #undef ESPCMD_TRPAD 120 #define ESPCMD_TRPAD 0x98 /* TRPAD needs DMA flag*/ 121 122 static __inline__ void dma_intr __P((struct dma_softc *sc)); 123 124 static __inline__ void 125 dma_intr(sc) 126 struct dma_softc *sc; 127 { 128 register struct esp_softc *sc_esp; 129 register u_char *p; 130 register u_int espphase, espstat, espintr; 131 register int cnt; 132 133 if (sc->sc_active == 0) { 134 printf("dma_intr--inactive DMA\n"); 135 return; 136 } 137 138 if ((sc->sc_esp->sc_espintr & ESPINTR_BS) == 0) { 139 sc->sc_active = 0; 140 return; 141 } 142 143 cnt = *sc->sc_pdmalen; 144 if (*sc->sc_pdmalen == 0) { 145 printf("data interrupt, but no count left."); 146 } 147 148 p = *sc->sc_dmaaddr; 149 sc_esp = sc->sc_esp; 150 espphase = sc_esp->sc_phase; 151 espstat = (u_int) sc_esp->sc_espstat; 152 espintr = (u_int) sc_esp->sc_espintr; 153 do { 154 if (sc->sc_datain) { 155 *p++ = ESP_READ_REG(sc_esp, ESP_FIFO); 156 cnt--; 157 if (espphase == DATA_IN_PHASE) { 158 ESPCMD(sc_esp, ESPCMD_TRANS); 159 } else { 160 sc->sc_active = 0; 161 } 162 } else { 163 if ( (espphase == DATA_OUT_PHASE) 164 || (espphase == MESSAGE_OUT_PHASE)) { 165 ESP_WRITE_REG(sc_esp, ESP_FIFO, *p++); 166 cnt--; 167 ESPCMD(sc_esp, ESPCMD_TRANS); 168 } else { 169 sc->sc_active = 0; 170 } 171 } 172 173 if (sc->sc_active) { 174 while (!DMA_ISINTR(sc)); 175 espstat = ESP_READ_REG(sc_esp, ESP_STAT); 176 espintr = ESP_READ_REG(sc_esp, ESP_INTR); 177 espphase = (espintr & ESPINTR_DIS) 178 ? /* Disconnected */ BUSFREE_PHASE 179 : espstat & ESPSTAT_PHASE; 180 } 181 } while (sc->sc_active && (espintr & ESPINTR_BS)); 182 sc_esp->sc_phase = espphase; 183 sc_esp->sc_espstat = (u_char) espstat; 184 sc_esp->sc_espintr = (u_char) espintr; 185 *sc->sc_dmaaddr = p; 186 *sc->sc_pdmalen = cnt; 187 188 if (*sc->sc_pdmalen == 0) { 189 sc->sc_tc = ESPSTAT_TC; 190 } 191 sc->sc_esp->sc_espstat |= sc->sc_tc; 192 } 193 #else 194 #include <dev/tc/tcvar.h> 195 #include <alpha/tc/tcdsvar.h> 196 #include <alpha/tc/espreg.h> 197 #include <alpha/tc/espvar.h> 198 #endif 199 #endif 200 201 int esp_debug = 0; /*ESP_SHOWPHASE|ESP_SHOWMISC|ESP_SHOWTRAC|ESP_SHOWCMDS;*/ 202 203 /*static*/ void espattach __P((struct device *, struct device *, void *)); 204 /*static*/ int espmatch __P((struct device *, void *, void *)); 205 /*static*/ u_int esp_adapter_info __P((struct esp_softc *)); 206 /*static*/ void espreadregs __P((struct esp_softc *)); 207 /*static*/ void esp_select __P((struct esp_softc *, struct esp_ecb *)); 208 /*static*/ int esp_reselect __P((struct esp_softc *, int)); 209 /*static*/ void esp_scsi_reset __P((struct esp_softc *)); 210 /*static*/ void esp_reset __P((struct esp_softc *)); 211 /*static*/ void esp_init __P((struct esp_softc *, int)); 212 /*static*/ int esp_scsi_cmd __P((struct scsi_xfer *)); 213 /*static*/ int esp_poll __P((struct esp_softc *, struct scsi_xfer *, int)); 214 /*static*/ void esp_sched __P((struct esp_softc *)); 215 /*static*/ void esp_done __P((struct esp_softc *, struct esp_ecb *)); 216 /*static*/ void esp_msgin __P((struct esp_softc *)); 217 /*static*/ void esp_msgout __P((struct esp_softc *)); 218 /*static*/ int espintr __P((struct esp_softc *)); 219 /*static*/ void esp_timeout __P((void *arg)); 220 /*static*/ void esp_abort __P((struct esp_softc *, struct esp_ecb *)); 221 /*static*/ void esp_dequeue __P((struct esp_softc *, struct esp_ecb *)); 222 void esp_sense __P((struct esp_softc *, struct esp_ecb *)); 223 void esp_free_ecb __P((struct esp_softc *, struct esp_ecb *, int)); 224 struct esp_ecb *esp_get_ecb __P((struct esp_softc *, int)); 225 static inline int esp_stp2cpb __P((struct esp_softc *, int)); 226 static inline int esp_cpb2stp __P((struct esp_softc *, int)); 227 static inline void esp_setsync __P((struct esp_softc *, struct esp_tinfo *)); 228 229 /* Linkup to the rest of the kernel */ 230 struct cfattach esp_ca = { 231 sizeof(struct esp_softc), espmatch, espattach 232 }; 233 234 struct cfdriver esp_cd = { 235 NULL, "esp", DV_DULL 236 }; 237 238 struct scsi_adapter esp_switch = { 239 esp_scsi_cmd, 240 minphys, /* no max at this level; handled by DMA code */ 241 NULL, 242 NULL, 243 }; 244 245 struct scsi_device esp_dev = { 246 NULL, /* Use default error handler */ 247 NULL, /* have a queue, served by this */ 248 NULL, /* have no async handler */ 249 NULL, /* Use default 'done' routine */ 250 }; 251 252 int 253 espmatch(parent, vcf, aux) 254 struct device *parent; 255 void *vcf, *aux; 256 { 257 struct cfdata *cf = vcf; 258 #ifdef SPARC_DRIVER 259 register struct confargs *ca = aux; 260 register struct romaux *ra = &ca->ca_ra; 261 262 if (strcmp(cf->cf_driver->cd_name, ra->ra_name)) 263 return (0); 264 if (ca->ca_bustype == BUS_SBUS) 265 return (1); 266 ra->ra_len = NBPG; 267 return (probeget(ra->ra_vaddr, 1) != -1); 268 #else 269 #ifdef MAC68K_DRIVER 270 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) 271 return (1); 272 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) 273 return (1); 274 return (0); 275 #else 276 struct tcdsdev_attach_args *tcdsdev = aux; 277 278 if (strncmp(tcdsdev->tcdsda_modname, "PMAZ-AA ", TC_ROM_LLEN)) 279 return (0); 280 return (!tc_badaddr(tcdsdev->tcdsda_addr)); 281 #endif 282 #endif 283 } 284 285 /* 286 * Attach this instance, and then all the sub-devices 287 */ 288 void 289 espattach(parent, self, aux) 290 struct device *parent, *self; 291 void *aux; 292 { 293 #ifdef SPARC_DRIVER 294 register struct confargs *ca = aux; 295 #else 296 #ifdef MAC68K_DRIVER 297 extern vm_offset_t SCSIBase; 298 #else 299 register struct tcdsdev_attach_args *tcdsdev = aux; 300 #endif 301 #endif 302 struct esp_softc *sc = (void *)self; 303 #ifdef SPARC_DRIVER 304 struct bootpath *bp; 305 int dmachild = strncmp(parent->dv_xname, "dma", 3) == 0; 306 #endif 307 308 #ifdef SPARC_DRIVER 309 /* 310 * Make sure things are sane. I don't know if this is ever 311 * necessary, but it seem to be in all of Torek's code. 312 */ 313 if (ca->ca_ra.ra_nintr != 1) { 314 printf(": expected 1 interrupt, got %d\n", ca->ca_ra.ra_nintr); 315 return; 316 } 317 318 sc->sc_pri = ca->ca_ra.ra_intr[0].int_pri; 319 printf(" pri %d", sc->sc_pri); 320 321 /* 322 * Map my registers in, if they aren't already in virtual 323 * address space. 324 */ 325 if (ca->ca_ra.ra_vaddr) 326 sc->sc_reg = (volatile u_char *) ca->ca_ra.ra_vaddr; 327 else { 328 sc->sc_reg = (volatile u_char *) 329 mapiodev(ca->ca_ra.ra_reg, 0, ca->ca_ra.ra_len, ca->ca_bustype); 330 } 331 #else 332 #ifdef MAC68K_DRIVER 333 if (sc->sc_dev.dv_unit == 0) { 334 unsigned long reg_offset; 335 336 sc->sc_reg = (volatile u_char *) SCSIBase; 337 mac68k_register_scsi_irq((void (*)(void *)) espintr, sc); 338 sc->irq_mask = V2IF_SCSIIRQ; 339 reg_offset = SCSIBase - IOBase; 340 if (reg_offset == 0x10000) { 341 sc->sc_freq = 16500000; 342 } else { 343 sc->sc_freq = 25000000; 344 } 345 } else { 346 sc->sc_reg = (volatile u_char *) SCSIBase + 0x402; 347 mac68k_register_scsi_b_irq((void (*)(void *)) espintr, sc); 348 sc->irq_mask = V2IF_SCSIDRQ; 349 sc->sc_freq = 25000000; 350 } 351 sc->sc_dma = &sc->_sc_dma; 352 printf(": address %p", sc->sc_reg); 353 354 sc->sc_id = 7; 355 #else 356 sc->sc_reg = (volatile u_int32_t *)tcdsdev->tcdsda_addr; 357 sc->sc_cookie = tcdsdev->tcdsda_cookie; 358 sc->sc_dma = tcdsdev->tcdsda_sc; 359 360 printf(": address %x", sc->sc_reg); 361 tcds_intr_establish(parent, sc->sc_cookie, TC_IPL_BIO, 362 (int (*)(void *))espintr, sc); 363 #endif 364 #endif 365 366 #ifdef SPARC_DRIVER 367 /* Other settings */ 368 sc->sc_node = ca->ca_ra.ra_node; 369 if (ca->ca_bustype == BUS_SBUS) { 370 sc->sc_id = getpropint(sc->sc_node, "initiator-id", 7); 371 sc->sc_freq = getpropint(sc->sc_node, "clock-frequency", -1); 372 } else { 373 sc->sc_id = 7; 374 sc->sc_freq = 24000000; 375 } 376 if (sc->sc_freq < 0) 377 sc->sc_freq = ((struct sbus_softc *) 378 sc->sc_dev.dv_parent)->sc_clockfreq; 379 #else 380 #ifdef MAC68K_DRIVER 381 #else 382 if (parent->dv_cfdata->cf_driver == &tcds_cd) { 383 sc->sc_id = tcdsdev->tcdsda_id; 384 sc->sc_freq = tcdsdev->tcdsda_freq; 385 } else { 386 /* XXX */ 387 sc->sc_id = 7; 388 sc->sc_freq = 24000000; 389 } 390 #endif 391 #endif 392 393 /* gimme Mhz */ 394 sc->sc_freq /= 1000000; 395 396 #ifdef SPARC_DRIVER 397 if (dmachild) { 398 sc->sc_dma = (struct dma_softc *)parent; 399 sc->sc_dma->sc_esp = sc; 400 } else { 401 /* 402 * find the DMA by poking around the dma device structures 403 * 404 * What happens here is that if the dma driver has not been 405 * configured, then this returns a NULL pointer. Then when the 406 * dma actually gets configured, it does the opposing test, and 407 * if the sc->sc_esp field in it's softc is NULL, then tries to 408 * find the matching esp driver. 409 * 410 */ 411 sc->sc_dma = (struct dma_softc *) 412 getdevunit("dma", sc->sc_dev.dv_unit); 413 414 /* 415 * and a back pointer to us, for DMA 416 */ 417 if (sc->sc_dma) 418 sc->sc_dma->sc_esp = sc; 419 else 420 panic("espattach: no dma found"); 421 } 422 #else 423 sc->sc_dma->sc_esp = sc; /* XXX */ 424 #endif 425 426 /* 427 * It is necessary to try to load the 2nd config register here, 428 * to find out what rev the esp chip is, else the esp_reset 429 * will not set up the defaults correctly. 430 */ 431 sc->sc_cfg1 = sc->sc_id | ESPCFG1_PARENB; 432 #ifdef SPARC_DRIVER 433 sc->sc_cfg2 = ESPCFG2_SCSI2 | ESPCFG2_RPE; 434 sc->sc_cfg3 = ESPCFG3_CDB; 435 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 436 437 if ((ESP_READ_REG(sc, ESP_CFG2) & ~ESPCFG2_RSVD) != (ESPCFG2_SCSI2 | ESPCFG2_RPE)) { 438 printf(": ESP100"); 439 sc->sc_rev = ESP100; 440 } else { 441 sc->sc_cfg2 = ESPCFG2_SCSI2; 442 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 443 sc->sc_cfg3 = 0; 444 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 445 sc->sc_cfg3 = (ESPCFG3_CDB | ESPCFG3_FCLK); 446 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 447 if (ESP_READ_REG(sc, ESP_CFG3) != (ESPCFG3_CDB | ESPCFG3_FCLK)) { 448 printf(": ESP100A"); 449 sc->sc_rev = ESP100A; 450 } else { 451 /* ESPCFG2_FE enables > 64K transfers */ 452 sc->sc_cfg2 |= ESPCFG2_FE; 453 sc->sc_cfg3 = 0; 454 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 455 printf(": ESP200"); 456 sc->sc_rev = ESP200; 457 } 458 } 459 #else 460 #ifdef MAC68K_DRIVER 461 sc->sc_cfg2 = ESPCFG2_SCSI2; 462 sc->sc_cfg3 = 0; 463 printf(": NCR53C96"); 464 sc->sc_rev = NCR53C96; 465 #else 466 sc->sc_cfg2 = ESPCFG2_SCSI2; 467 sc->sc_cfg3 = 0x4; /* Save residual byte. XXX??? */ 468 printf(": NCR53C94"); 469 sc->sc_rev = NCR53C94; 470 #endif 471 #endif 472 473 /* 474 * This is the value used to start sync negotiations 475 * Note that the ESP register "SYNCTP" is programmed 476 * in "clocks per byte", and has a minimum value of 4. 477 * The SCSI period used in negotiation is one-fourth 478 * of the time (in nanoseconds) needed to transfer one byte. 479 * Since the chip's clock is given in MHz, we have the following 480 * formula: 4 * period = (1000 / freq) * 4 481 */ 482 sc->sc_minsync = 1000 / sc->sc_freq; 483 484 #ifdef SPARC_DRIVER 485 /* 486 * Alas, we must now modify the value a bit, because it's 487 * only valid when can switch on FASTCLK and FASTSCSI bits 488 * in config register 3... 489 */ 490 switch (sc->sc_rev) { 491 case ESP100: 492 sc->sc_maxxfer = 64 * 1024; 493 sc->sc_minsync = 0; /* No synch on old chip? */ 494 break; 495 case ESP100A: 496 sc->sc_maxxfer = 64 * 1024; 497 sc->sc_minsync = esp_cpb2stp(sc, 5); /* Min clocks/byte is 5 */ 498 break; 499 case ESP200: 500 sc->sc_maxxfer = 16 * 1024 * 1024; 501 /* XXX - do actually set FAST* bits */ 502 } 503 #else 504 #ifdef MAC68K_DRIVER 505 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */ 506 /* Really no limit, but since we want to fit into the TCR... */ 507 sc->sc_maxxfer = 64 * 1024; 508 #else 509 sc->sc_maxxfer = 64 * 1024; 510 #endif 511 #endif 512 513 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 514 515 /* The value *must not* be == 1. Make it 2 */ 516 if (sc->sc_ccf == 1) 517 sc->sc_ccf = 2; 518 519 /* 520 * The recommended timeout is 250ms. This register is loaded 521 * with a value calculated as follows, from the docs: 522 * 523 * (timout period) x (CLK frequency) 524 * reg = ------------------------------------- 525 * 8192 x (Clock Conversion Factor) 526 * 527 * Since CCF has a linear relation to CLK, this generally computes 528 * to the constant of 153. 529 */ 530 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 531 532 /* CCF register only has 3 bits; 0 is actually 8 */ 533 sc->sc_ccf &= 7; 534 535 /* Reset state & bus */ 536 sc->sc_state = 0; 537 esp_init(sc, 1); 538 539 printf(" %dMhz, target %d\n", sc->sc_freq, sc->sc_id); 540 541 #ifdef SPARC_DRIVER 542 /* add me to the sbus structures */ 543 sc->sc_sd.sd_reset = (void *) esp_reset; 544 #if defined(SUN4C) || defined(SUN4M) 545 if (ca->ca_bustype == BUS_SBUS) { 546 if (dmachild) 547 sbus_establish(&sc->sc_sd, sc->sc_dev.dv_parent); 548 else 549 sbus_establish(&sc->sc_sd, &sc->sc_dev); 550 } 551 #endif /* SUN4C || SUN4M */ 552 #endif 553 554 #ifdef SPARC_DRIVER 555 /* and the interuppts */ 556 sc->sc_ih.ih_fun = (void *) espintr; 557 sc->sc_ih.ih_arg = sc; 558 intr_establish(sc->sc_pri, &sc->sc_ih); 559 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 560 #endif 561 562 /* 563 * fill in the prototype scsi_link. 564 */ 565 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 566 sc->sc_link.adapter_softc = sc; 567 sc->sc_link.adapter_target = sc->sc_id; 568 sc->sc_link.adapter = &esp_switch; 569 sc->sc_link.device = &esp_dev; 570 sc->sc_link.openings = 2; 571 572 /* 573 * If the boot path is "esp" at the moment and it's me, then 574 * walk our pointer to the sub-device, ready for the config 575 * below. 576 */ 577 #ifdef SPARC_DRIVER 578 bp = ca->ca_ra.ra_bp; 579 switch (ca->ca_bustype) { 580 case BUS_SBUS: 581 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 582 SAME_ESP(sc, bp, ca)) 583 bootpath_store(1, bp + 1); 584 break; 585 default: 586 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 587 bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit) 588 bootpath_store(1, bp + 1); 589 break; 590 } 591 #endif 592 593 /* 594 * Now try to attach all the sub-devices 595 */ 596 config_found(self, &sc->sc_link, scsiprint); 597 598 #ifdef MAC68K_DRIVER 599 via2_reg(vPCR) = 0x22; 600 via2_reg(vIFR) = sc->irq_mask; 601 via2_reg(vIER) = 0x80 | sc->irq_mask; 602 #endif 603 #ifdef SPARC_DRIVER 604 bootpath_store(1, NULL); 605 #endif 606 } 607 608 /* 609 * This is the generic esp reset function. It does not reset the SCSI bus, 610 * only this controllers, but kills any on-going commands, and also stops 611 * and resets the DMA. 612 * 613 * After reset, registers are loaded with the defaults from the attach 614 * routine above. 615 */ 616 void 617 esp_reset(sc) 618 struct esp_softc *sc; 619 { 620 621 /* reset DMA first */ 622 DMA_RESET(sc->sc_dma); 623 624 /* reset SCSI chip */ 625 ESPCMD(sc, ESPCMD_RSTCHIP); 626 ESPCMD(sc, ESPCMD_NOP); 627 DELAY(500); 628 629 /* do these backwards, and fall through */ 630 switch (sc->sc_rev) { 631 #ifndef SPARC_DRIVER 632 case NCR53C96: 633 case NCR53C94: 634 #endif 635 case ESP200: 636 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 637 case ESP100A: 638 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 639 case ESP100: 640 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 641 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 642 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 643 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 644 break; 645 default: 646 printf("%s: unknown revision code, assuming ESP100\n", 647 sc->sc_dev.dv_xname); 648 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 649 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 650 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 651 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 652 } 653 } 654 655 /* 656 * Reset the SCSI bus, but not the chip 657 */ 658 void 659 esp_scsi_reset(sc) 660 struct esp_softc *sc; 661 { 662 #ifdef SPARC_DRIVER 663 /* stop DMA first, as the chip will return to Bus Free phase */ 664 DMACSR(sc->sc_dma) &= ~D_EN_DMA; 665 #else 666 /* 667 * XXX STOP DMA FIRST 668 */ 669 #endif 670 671 printf("esp: resetting SCSI bus\n"); 672 ESPCMD(sc, ESPCMD_RSTSCSI); 673 } 674 675 /* 676 * Initialize esp state machine 677 */ 678 void 679 esp_init(sc, doreset) 680 struct esp_softc *sc; 681 int doreset; 682 { 683 struct esp_ecb *ecb; 684 int r; 685 686 ESP_TRACE(("[ESP_INIT(%d)] ", doreset)); 687 688 if (sc->sc_state == 0) { 689 /* First time through; initialize. */ 690 TAILQ_INIT(&sc->ready_list); 691 TAILQ_INIT(&sc->nexus_list); 692 TAILQ_INIT(&sc->free_list); 693 sc->sc_nexus = NULL; 694 ecb = sc->sc_ecb; 695 bzero(ecb, sizeof(sc->sc_ecb)); 696 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 697 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 698 ecb++; 699 } 700 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 701 } else { 702 /* Cancel any active commands. */ 703 sc->sc_state = ESP_CLEANING; 704 if ((ecb = sc->sc_nexus) != NULL) { 705 ecb->xs->error = XS_DRIVER_STUFFUP; 706 untimeout(esp_timeout, ecb); 707 esp_done(sc, ecb); 708 } 709 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 710 ecb->xs->error = XS_DRIVER_STUFFUP; 711 untimeout(esp_timeout, ecb); 712 esp_done(sc, ecb); 713 } 714 } 715 716 /* 717 * reset the chip to a known state 718 */ 719 esp_reset(sc); 720 721 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 722 for (r = 0; r < 8; r++) { 723 struct esp_tinfo *ti = &sc->sc_tinfo[r]; 724 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 725 int fl = sc->sc_dev.dv_cfdata->cf_flags; 726 727 ti->flags = ((sc->sc_minsync && !(fl & (1<<(r+8)))) 728 ? T_NEGOTIATE : 0) | 729 ((fl & (1<<r)) ? T_RSELECTOFF : 0) | 730 T_NEED_TO_RESET; 731 ti->period = sc->sc_minsync; 732 ti->offset = 0; 733 } 734 735 if (doreset) { 736 sc->sc_state = ESP_SBR; 737 ESPCMD(sc, ESPCMD_RSTSCSI); 738 } else { 739 sc->sc_state = ESP_IDLE; 740 } 741 } 742 743 /* 744 * Read the ESP registers, and save their contents for later use. 745 * ESP_STAT, ESP_STEP & ESP_INTR are mostly zeroed out when reading 746 * ESP_INTR - so make sure it is the last read. 747 * 748 * I think that (from reading the docs) most bits in these registers 749 * only make sense when he DMA CSR has an interrupt showing. Call only 750 * if an interrupt is pending. 751 */ 752 void 753 espreadregs(sc) 754 struct esp_softc *sc; 755 { 756 757 sc->sc_espstat = ESP_READ_REG(sc, ESP_STAT); 758 /* Only the stepo bits are of interest */ 759 sc->sc_espstep = ESP_READ_REG(sc, ESP_STEP) & ESPSTEP_MASK; 760 sc->sc_espintr = ESP_READ_REG(sc, ESP_INTR); 761 762 #if !defined(SPARC_DRIVER) && !defined(MAC68K_DRIVER) 763 /* Clear the TCDS interrupt bit. */ 764 (void)tcds_scsi_isintr(sc->sc_dma, 1); 765 #endif 766 767 /* 768 * Determine the SCSI bus phase, return either a real SCSI bus phase 769 * or some pseudo phase we use to detect certain exceptions. 770 */ 771 772 sc->sc_phase = (sc->sc_espintr & ESPINTR_DIS) 773 ? /* Disconnected */ BUSFREE_PHASE 774 : sc->sc_espstat & ESPSTAT_PHASE; 775 776 ESP_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 777 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 778 } 779 780 /* 781 * Convert chip register Clock Per Byte value to Synchronous Transfer Period. 782 */ 783 static inline int 784 esp_cpb2stp(sc, cpb) 785 struct esp_softc *sc; 786 int cpb; 787 { 788 return ((250 * cpb) / sc->sc_freq); 789 } 790 791 /* 792 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 793 */ 794 static inline int 795 esp_stp2cpb(sc, period) 796 struct esp_softc *sc; 797 int period; 798 { 799 int v; 800 v = (sc->sc_freq * period) / 250; 801 if (esp_cpb2stp(sc, v) < period) 802 /* Correct round-down error */ 803 v++; 804 return v; 805 } 806 807 static inline void 808 esp_setsync(sc, ti) 809 struct esp_softc *sc; 810 struct esp_tinfo *ti; 811 { 812 813 if (ti->flags & T_SYNCMODE) { 814 ESP_WRITE_REG(sc, ESP_SYNCOFF, ti->offset); 815 ESP_WRITE_REG(sc, ESP_SYNCTP, esp_stp2cpb(sc, ti->period)); 816 } else { 817 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 818 ESP_WRITE_REG(sc, ESP_SYNCTP, 0); 819 } 820 } 821 822 /* 823 * Send a command to a target, set the driver state to ESP_SELECTING 824 * and let the caller take care of the rest. 825 * 826 * Keeping this as a function allows me to say that this may be done 827 * by DMA instead of programmed I/O soon. 828 */ 829 void 830 esp_select(sc, ecb) 831 struct esp_softc *sc; 832 struct esp_ecb *ecb; 833 { 834 struct scsi_link *sc_link = ecb->xs->sc_link; 835 int target = sc_link->target; 836 struct esp_tinfo *ti = &sc->sc_tinfo[target]; 837 u_char *cmd; 838 int clen; 839 840 ESP_TRACE(("[esp_select(t%d,l%d,cmd:%x)] ", sc_link->target, sc_link->lun, ecb->cmd.opcode)); 841 842 /* new state ESP_SELECTING */ 843 sc->sc_state = ESP_SELECTING; 844 845 ESPCMD(sc, ESPCMD_FLUSH); 846 847 /* 848 * The docs say the target register is never reset, and I 849 * can't think of a better place to set it 850 */ 851 ESP_WRITE_REG(sc, ESP_SELID, target); 852 esp_setsync(sc, ti); 853 854 /* 855 * Who am I. This is where we tell the target that we are 856 * happy for it to disconnect etc. 857 */ 858 ESP_WRITE_REG(sc, ESP_FIFO, 859 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 860 861 if (ti->flags & T_NEGOTIATE) { 862 /* Arbitrate, select and stop after IDENTIFY message */ 863 ESPCMD(sc, ESPCMD_SELATNS); 864 return; 865 } 866 867 /* Now the command into the FIFO */ 868 cmd = (u_char *)&ecb->cmd; 869 clen = ecb->clen; 870 while (clen--) 871 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 872 873 /* And get the targets attention */ 874 ESPCMD(sc, ESPCMD_SELATN); 875 } 876 877 void 878 esp_free_ecb(sc, ecb, flags) 879 struct esp_softc *sc; 880 struct esp_ecb *ecb; 881 int flags; 882 { 883 int s; 884 885 s = splbio(); 886 887 ecb->flags = 0; 888 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 889 890 /* 891 * If there were none, wake anybody waiting for one to come free, 892 * starting with queued entries. 893 */ 894 if (ecb->chain.tqe_next == 0) 895 wakeup(&sc->free_list); 896 897 splx(s); 898 } 899 900 struct esp_ecb * 901 esp_get_ecb(sc, flags) 902 struct esp_softc *sc; 903 int flags; 904 { 905 struct esp_ecb *ecb; 906 int s; 907 908 s = splbio(); 909 910 while ((ecb = sc->free_list.tqh_first) == NULL && 911 (flags & SCSI_NOSLEEP) == 0) 912 tsleep(&sc->free_list, PRIBIO, "especb", 0); 913 if (ecb) { 914 TAILQ_REMOVE(&sc->free_list, ecb, chain); 915 ecb->flags |= ECB_ALLOC; 916 } 917 918 splx(s); 919 return ecb; 920 } 921 922 /* 923 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 924 */ 925 926 /* 927 * Start a SCSI-command 928 * This function is called by the higher level SCSI-driver to queue/run 929 * SCSI-commands. 930 */ 931 int 932 esp_scsi_cmd(xs) 933 struct scsi_xfer *xs; 934 { 935 struct scsi_link *sc_link = xs->sc_link; 936 struct esp_softc *sc = sc_link->adapter_softc; 937 struct esp_ecb *ecb; 938 int s, flags; 939 940 ESP_TRACE(("[esp_scsi_cmd] ")); 941 ESP_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 942 sc_link->target)); 943 944 flags = xs->flags; 945 if ((ecb = esp_get_ecb(sc, flags)) == NULL) { 946 xs->error = XS_DRIVER_STUFFUP; 947 return TRY_AGAIN_LATER; 948 } 949 950 /* Initialize ecb */ 951 ecb->xs = xs; 952 ecb->timeout = xs->timeout; 953 954 if (xs->flags & SCSI_RESET) { 955 ecb->flags |= ECB_RESET; 956 ecb->clen = 0; 957 ecb->dleft = 0; 958 } else { 959 bcopy(xs->cmd, &ecb->cmd, xs->cmdlen); 960 ecb->clen = xs->cmdlen; 961 ecb->daddr = xs->data; 962 ecb->dleft = xs->datalen; 963 } 964 ecb->stat = 0; 965 966 s = splbio(); 967 968 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 969 if (sc->sc_state == ESP_IDLE) 970 esp_sched(sc); 971 972 splx(s); 973 974 if ((flags & SCSI_POLL) == 0) 975 return SUCCESSFULLY_QUEUED; 976 977 /* Not allowed to use interrupts, use polling instead */ 978 if (esp_poll(sc, xs, ecb->timeout)) { 979 esp_timeout(ecb); 980 if (esp_poll(sc, xs, ecb->timeout)) 981 esp_timeout(ecb); 982 } 983 return COMPLETE; 984 } 985 986 /* 987 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 988 */ 989 int 990 esp_poll(sc, xs, count) 991 struct esp_softc *sc; 992 struct scsi_xfer *xs; 993 int count; 994 { 995 996 ESP_TRACE(("[esp_poll] ")); 997 while (count) { 998 if (DMA_ISINTR(sc->sc_dma)) { 999 espintr(sc); 1000 } 1001 #if alternatively 1002 if (ESP_READ_REG(sc, ESP_STAT) & ESPSTAT_INT) 1003 espintr(sc); 1004 #endif 1005 if ((xs->flags & ITSDONE) != 0) 1006 return 0; 1007 if (sc->sc_state == ESP_IDLE) { 1008 ESP_TRACE(("[esp_poll: rescheduling] ")); 1009 esp_sched(sc); 1010 } 1011 DELAY(1000); 1012 count--; 1013 } 1014 return 1; 1015 } 1016 1017 1018 /* 1019 * LOW LEVEL SCSI UTILITIES 1020 */ 1021 1022 /* 1023 * Schedule a scsi operation. This has now been pulled out of the interrupt 1024 * handler so that we may call it from esp_scsi_cmd and esp_done. This may 1025 * save us an unecessary interrupt just to get things going. Should only be 1026 * called when state == ESP_IDLE and at bio pl. 1027 */ 1028 void 1029 esp_sched(sc) 1030 struct esp_softc *sc; 1031 { 1032 struct esp_ecb *ecb; 1033 struct scsi_link *sc_link; 1034 struct esp_tinfo *ti; 1035 1036 ESP_TRACE(("[esp_sched] ")); 1037 if (sc->sc_state != ESP_IDLE) 1038 panic("esp_sched: not IDLE (state=%d)", sc->sc_state); 1039 1040 /* 1041 * Find first ecb in ready queue that is for a target/lunit 1042 * combinations that is not busy. 1043 */ 1044 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 1045 sc_link = ecb->xs->sc_link; 1046 ti = &sc->sc_tinfo[sc_link->target]; 1047 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 1048 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1049 sc->sc_nexus = ecb; 1050 esp_select(sc, ecb); 1051 break; 1052 } else 1053 ESP_MISC(("%d:%d busy\n", 1054 sc_link->target, sc_link->lun)); 1055 } 1056 } 1057 1058 void 1059 esp_sense(sc, ecb) 1060 struct esp_softc *sc; 1061 struct esp_ecb *ecb; 1062 { 1063 struct scsi_xfer *xs = ecb->xs; 1064 struct scsi_link *sc_link = xs->sc_link; 1065 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1066 struct scsi_sense *ss = (void *)&ecb->cmd; 1067 1068 ESP_MISC(("requesting sense ")); 1069 /* Next, setup a request sense command block */ 1070 bzero(ss, sizeof(*ss)); 1071 ss->opcode = REQUEST_SENSE; 1072 ss->byte2 = sc_link->lun << 5; 1073 ss->length = sizeof(struct scsi_sense_data); 1074 ecb->clen = sizeof(*ss); 1075 ecb->daddr = (char *)&xs->sense; 1076 ecb->dleft = sizeof(struct scsi_sense_data); 1077 ecb->flags |= ECB_SENSE; 1078 ti->senses++; 1079 if (ecb->flags & ECB_NEXUS) 1080 ti->lubusy &= ~(1 << sc_link->lun); 1081 if (ecb == sc->sc_nexus) { 1082 esp_select(sc, ecb); 1083 } else { 1084 esp_dequeue(sc, ecb); 1085 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1086 if (sc->sc_state == ESP_IDLE) 1087 esp_sched(sc); 1088 } 1089 } 1090 1091 /* 1092 * POST PROCESSING OF SCSI_CMD (usually current) 1093 */ 1094 void 1095 esp_done(sc, ecb) 1096 struct esp_softc *sc; 1097 struct esp_ecb *ecb; 1098 { 1099 struct scsi_xfer *xs = ecb->xs; 1100 struct scsi_link *sc_link = xs->sc_link; 1101 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1102 1103 ESP_TRACE(("[esp_done(error:%x)] ", xs->error)); 1104 1105 /* 1106 * Now, if we've come here with no error code, i.e. we've kept the 1107 * initial XS_NOERROR, and the status code signals that we should 1108 * check sense, we'll need to set up a request sense cmd block and 1109 * push the command back into the ready queue *before* any other 1110 * commands for this target/lunit, else we lose the sense info. 1111 * We don't support chk sense conditions for the request sense cmd. 1112 */ 1113 if (xs->error == XS_NOERROR) { 1114 if ((ecb->flags & ECB_ABORT) != 0) { 1115 xs->error = XS_DRIVER_STUFFUP; 1116 } else if ((ecb->flags & ECB_SENSE) != 0) { 1117 xs->error = XS_SENSE; 1118 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 1119 /* First, save the return values */ 1120 xs->resid = ecb->dleft; 1121 xs->status = ecb->stat; 1122 esp_sense(sc, ecb); 1123 return; 1124 } else { 1125 xs->resid = ecb->dleft; 1126 } 1127 } 1128 1129 xs->flags |= ITSDONE; 1130 1131 #if ESP_DEBUG > 0 1132 if (esp_debug & ESP_SHOWMISC) { 1133 if (xs->resid != 0) 1134 printf("resid=%d ", xs->resid); 1135 if (xs->error == XS_SENSE) 1136 printf("sense=0x%02x\n", xs->sense.error_code); 1137 else 1138 printf("error=%d\n", xs->error); 1139 } 1140 #endif 1141 1142 /* 1143 * Remove the ECB from whatever queue it's on. 1144 */ 1145 if (ecb->flags & ECB_NEXUS) 1146 ti->lubusy &= ~(1 << sc_link->lun); 1147 if (ecb == sc->sc_nexus) { 1148 sc->sc_nexus = NULL; 1149 sc->sc_state = ESP_IDLE; 1150 esp_sched(sc); 1151 } else 1152 esp_dequeue(sc, ecb); 1153 1154 esp_free_ecb(sc, ecb, xs->flags); 1155 ti->cmds++; 1156 scsi_done(xs); 1157 } 1158 1159 void 1160 esp_dequeue(sc, ecb) 1161 struct esp_softc *sc; 1162 struct esp_ecb *ecb; 1163 { 1164 1165 if (ecb->flags & ECB_NEXUS) { 1166 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1167 } else { 1168 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1169 } 1170 } 1171 1172 /* 1173 * INTERRUPT/PROTOCOL ENGINE 1174 */ 1175 1176 /* 1177 * Schedule an outgoing message by prioritizing it, and asserting 1178 * attention on the bus. We can only do this when we are the initiator 1179 * else there will be an illegal command interrupt. 1180 */ 1181 #define esp_sched_msgout(m) \ 1182 do { \ 1183 ESP_MISC(("esp_sched_msgout %d ", m)); \ 1184 ESPCMD(sc, ESPCMD_SETATN); \ 1185 sc->sc_flags |= ESP_ATN; \ 1186 sc->sc_msgpriq |= (m); \ 1187 } while (0) 1188 1189 int 1190 esp_reselect(sc, message) 1191 struct esp_softc *sc; 1192 int message; 1193 { 1194 u_char selid, target, lun; 1195 struct esp_ecb *ecb; 1196 struct scsi_link *sc_link; 1197 struct esp_tinfo *ti; 1198 1199 /* 1200 * The SCSI chip made a snapshot of the data bus while the reselection 1201 * was being negotiated. This enables us to determine which target did 1202 * the reselect. 1203 */ 1204 selid = sc->sc_selid & ~(1 << sc->sc_id); 1205 if (selid & (selid - 1)) { 1206 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 1207 sc->sc_dev.dv_xname, selid); 1208 goto reset; 1209 } 1210 1211 /* 1212 * Search wait queue for disconnected cmd 1213 * The list should be short, so I haven't bothered with 1214 * any more sophisticated structures than a simple 1215 * singly linked list. 1216 */ 1217 target = ffs(selid) - 1; 1218 lun = message & 0x07; 1219 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 1220 ecb = ecb->chain.tqe_next) { 1221 sc_link = ecb->xs->sc_link; 1222 if (sc_link->target == target && sc_link->lun == lun) 1223 break; 1224 } 1225 if (ecb == NULL) { 1226 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 1227 sc->sc_dev.dv_xname, target, lun); 1228 goto abort; 1229 } 1230 1231 /* Make this nexus active again. */ 1232 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1233 sc->sc_state = ESP_CONNECTED; 1234 sc->sc_nexus = ecb; 1235 ti = &sc->sc_tinfo[target]; 1236 ti->lubusy |= (1 << lun); 1237 esp_setsync(sc, ti); 1238 1239 if (ecb->flags & ECB_RESET) 1240 esp_sched_msgout(SEND_DEV_RESET); 1241 else if (ecb->flags & ECB_ABORT) 1242 esp_sched_msgout(SEND_ABORT); 1243 1244 /* Do an implicit RESTORE POINTERS. */ 1245 sc->sc_dp = ecb->daddr; 1246 sc->sc_dleft = ecb->dleft; 1247 1248 return (0); 1249 1250 reset: 1251 esp_sched_msgout(SEND_DEV_RESET); 1252 return (1); 1253 1254 abort: 1255 esp_sched_msgout(SEND_ABORT); 1256 return (1); 1257 } 1258 1259 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 1260 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1261 #define ISEXTMSG(m) ((m) == 1) 1262 1263 /* 1264 * Get an incoming message as initiator. 1265 * 1266 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1267 * byte in the FIFO 1268 */ 1269 void 1270 esp_msgin(sc) 1271 register struct esp_softc *sc; 1272 { 1273 register int v; 1274 1275 ESP_TRACE(("[esp_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1276 1277 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) == 0) { 1278 printf("%s: msgin: no msg byte available\n", 1279 sc->sc_dev.dv_xname); 1280 return; 1281 } 1282 1283 /* 1284 * Prepare for a new message. A message should (according 1285 * to the SCSI standard) be transmitted in one single 1286 * MESSAGE_IN_PHASE. If we have been in some other phase, 1287 * then this is a new message. 1288 */ 1289 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1290 sc->sc_flags &= ~ESP_DROP_MSGI; 1291 sc->sc_imlen = 0; 1292 } 1293 1294 v = ESP_READ_REG(sc, ESP_FIFO); 1295 ESP_MISC(("<msgbyte:0x%02x>", v)); 1296 1297 #if 0 1298 if (sc->sc_state == ESP_RESELECTED && sc->sc_imlen == 0) { 1299 /* 1300 * Which target is reselecting us? (The ID bit really) 1301 */ 1302 sc->sc_selid = v; 1303 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1304 return; 1305 } 1306 #endif 1307 1308 sc->sc_imess[sc->sc_imlen] = v; 1309 1310 /* 1311 * If we're going to reject the message, don't bother storing 1312 * the incoming bytes. But still, we need to ACK them. 1313 */ 1314 1315 if ((sc->sc_flags & ESP_DROP_MSGI)) { 1316 ESPCMD(sc, ESPCMD_MSGOK); 1317 printf("<dropping msg byte %x>", 1318 sc->sc_imess[sc->sc_imlen]); 1319 return; 1320 } 1321 1322 if (sc->sc_imlen >= ESP_MAX_MSG_LEN) { 1323 esp_sched_msgout(SEND_REJECT); 1324 sc->sc_flags |= ESP_DROP_MSGI; 1325 } else { 1326 sc->sc_imlen++; 1327 /* 1328 * This testing is suboptimal, but most 1329 * messages will be of the one byte variety, so 1330 * it should not effect performance 1331 * significantly. 1332 */ 1333 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1334 goto gotit; 1335 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1336 goto gotit; 1337 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1338 sc->sc_imlen == sc->sc_imess[1] + 2) 1339 goto gotit; 1340 } 1341 /* Ack what we have so far */ 1342 ESPCMD(sc, ESPCMD_MSGOK); 1343 return; 1344 1345 gotit: 1346 ESP_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1347 /* 1348 * Now we should have a complete message (1 byte, 2 byte 1349 * and moderately long extended messages). We only handle 1350 * extended messages which total length is shorter than 1351 * ESP_MAX_MSG_LEN. Longer messages will be amputated. 1352 */ 1353 switch (sc->sc_state) { 1354 struct esp_ecb *ecb; 1355 struct esp_tinfo *ti; 1356 1357 case ESP_CONNECTED: 1358 ecb = sc->sc_nexus; 1359 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1360 1361 switch (sc->sc_imess[0]) { 1362 case MSG_CMDCOMPLETE: 1363 ESP_MSGS(("cmdcomplete ")); 1364 if (sc->sc_dleft < 0) { 1365 struct scsi_link *sc_link = ecb->xs->sc_link; 1366 printf("%s: %d extra bytes from %d:%d\n", 1367 sc->sc_dev.dv_xname, -sc->sc_dleft, 1368 sc_link->target, sc_link->lun); 1369 sc->sc_dleft = 0; 1370 } 1371 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 1372 sc->sc_state = ESP_CMDCOMPLETE; 1373 break; 1374 1375 case MSG_MESSAGE_REJECT: 1376 if (esp_debug & ESP_SHOWMSGS) 1377 printf("%s: our msg rejected by target\n", 1378 sc->sc_dev.dv_xname); 1379 switch (sc->sc_msgout) { 1380 case SEND_SDTR: 1381 sc->sc_flags &= ~ESP_SYNCHNEGO; 1382 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1383 esp_setsync(sc, ti); 1384 break; 1385 case SEND_INIT_DET_ERR: 1386 goto abort; 1387 } 1388 break; 1389 1390 case MSG_NOOP: 1391 ESP_MSGS(("noop ")); 1392 break; 1393 1394 case MSG_DISCONNECT: 1395 ESP_MSGS(("disconnect ")); 1396 ti->dconns++; 1397 sc->sc_state = ESP_DISCONNECT; 1398 if ((ecb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1399 break; 1400 /*FALLTHROUGH*/ 1401 1402 case MSG_SAVEDATAPOINTER: 1403 ESP_MSGS(("save datapointer ")); 1404 ecb->daddr = sc->sc_dp; 1405 ecb->dleft = sc->sc_dleft; 1406 break; 1407 1408 case MSG_RESTOREPOINTERS: 1409 ESP_MSGS(("restore datapointer ")); 1410 sc->sc_dp = ecb->daddr; 1411 sc->sc_dleft = ecb->dleft; 1412 break; 1413 1414 case MSG_EXTENDED: 1415 ESP_MSGS(("extended(%x) ", sc->sc_imess[2])); 1416 switch (sc->sc_imess[2]) { 1417 case MSG_EXT_SDTR: 1418 ESP_MSGS(("SDTR period %d, offset %d ", 1419 sc->sc_imess[3], sc->sc_imess[4])); 1420 if (sc->sc_imess[1] != 3) 1421 goto reject; 1422 ti->period = sc->sc_imess[3]; 1423 ti->offset = sc->sc_imess[4]; 1424 ti->flags &= ~T_NEGOTIATE; 1425 if (sc->sc_minsync == 0 || 1426 ti->offset == 0 || 1427 ti->period > 124) { 1428 printf("%s:%d: async\n", "esp", 1429 ecb->xs->sc_link->target); 1430 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1431 /* target initiated negotiation */ 1432 ti->offset = 0; 1433 ti->flags &= ~T_SYNCMODE; 1434 esp_sched_msgout(SEND_SDTR); 1435 } else { 1436 /* we are async */ 1437 ti->flags &= ~T_SYNCMODE; 1438 } 1439 } else { 1440 int r = 250/ti->period; 1441 int s = (100*250)/ti->period - 100*r; 1442 int p; 1443 1444 p = esp_stp2cpb(sc, ti->period); 1445 ti->period = esp_cpb2stp(sc, p); 1446 #ifdef ESP_DEBUG 1447 sc_print_addr(ecb->xs->sc_link); 1448 printf("max sync rate %d.%02dMb/s\n", 1449 r, s); 1450 #endif 1451 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1452 /* target initiated negotiation */ 1453 if (ti->period < sc->sc_minsync) 1454 ti->period = sc->sc_minsync; 1455 if (ti->offset > 15) 1456 ti->offset = 15; 1457 ti->flags &= ~T_SYNCMODE; 1458 esp_sched_msgout(SEND_SDTR); 1459 } else { 1460 /* we are sync */ 1461 ti->flags |= T_SYNCMODE; 1462 } 1463 } 1464 sc->sc_flags &= ~ESP_SYNCHNEGO; 1465 esp_setsync(sc, ti); 1466 break; 1467 1468 default: 1469 printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n", 1470 sc->sc_dev.dv_xname); 1471 goto reject; 1472 } 1473 break; 1474 1475 default: 1476 ESP_MSGS(("ident ")); 1477 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1478 sc->sc_dev.dv_xname); 1479 reject: 1480 esp_sched_msgout(SEND_REJECT); 1481 break; 1482 } 1483 break; 1484 1485 case ESP_RESELECTED: 1486 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1487 printf("%s: reselect without IDENTIFY; sending DEVICE RESET\n", 1488 sc->sc_dev.dv_xname); 1489 goto reset; 1490 } 1491 1492 (void) esp_reselect(sc, sc->sc_imess[0]); 1493 break; 1494 1495 default: 1496 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1497 sc->sc_dev.dv_xname); 1498 reset: 1499 esp_sched_msgout(SEND_DEV_RESET); 1500 break; 1501 1502 abort: 1503 esp_sched_msgout(SEND_ABORT); 1504 break; 1505 } 1506 1507 /* Ack last message byte */ 1508 ESPCMD(sc, ESPCMD_MSGOK); 1509 1510 /* Done, reset message pointer. */ 1511 sc->sc_flags &= ~ESP_DROP_MSGI; 1512 sc->sc_imlen = 0; 1513 } 1514 1515 1516 /* 1517 * Send the highest priority, scheduled message 1518 */ 1519 void 1520 esp_msgout(sc) 1521 register struct esp_softc *sc; 1522 { 1523 struct esp_tinfo *ti; 1524 struct esp_ecb *ecb; 1525 size_t size; 1526 1527 ESP_TRACE(("[esp_msgout(priq:%x, prevphase:%x)]", sc->sc_msgpriq, sc->sc_prevphase)); 1528 1529 if (sc->sc_flags & ESP_ATN) { 1530 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1531 new: 1532 ESPCMD(sc, ESPCMD_FLUSH); 1533 DELAY(1); 1534 sc->sc_msgoutq = 0; 1535 sc->sc_omlen = 0; 1536 } 1537 } else { 1538 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1539 esp_sched_msgout(sc->sc_msgoutq); 1540 goto new; 1541 } else { 1542 printf("esp at line %d: unexpected MESSAGE OUT phase\n", __LINE__); 1543 } 1544 } 1545 1546 if (sc->sc_omlen == 0) { 1547 /* Pick up highest priority message */ 1548 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1549 sc->sc_msgoutq |= sc->sc_msgout; 1550 sc->sc_msgpriq &= ~sc->sc_msgout; 1551 sc->sc_omlen = 1; /* "Default" message len */ 1552 switch (sc->sc_msgout) { 1553 case SEND_SDTR: 1554 ecb = sc->sc_nexus; 1555 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1556 sc->sc_omess[0] = MSG_EXTENDED; 1557 sc->sc_omess[1] = 3; 1558 sc->sc_omess[2] = MSG_EXT_SDTR; 1559 sc->sc_omess[3] = ti->period; 1560 sc->sc_omess[4] = ti->offset; 1561 sc->sc_omlen = 5; 1562 if ((sc->sc_flags & ESP_SYNCHNEGO) == 0) { 1563 ti->flags |= T_SYNCMODE; 1564 esp_setsync(sc, ti); 1565 } 1566 break; 1567 case SEND_IDENTIFY: 1568 if (sc->sc_state != ESP_CONNECTED) { 1569 printf("esp at line %d: no nexus\n", __LINE__); 1570 } 1571 ecb = sc->sc_nexus; 1572 sc->sc_omess[0] = MSG_IDENTIFY(ecb->xs->sc_link->lun,0); 1573 break; 1574 case SEND_DEV_RESET: 1575 sc->sc_flags |= ESP_ABORTING; 1576 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1577 ecb = sc->sc_nexus; 1578 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1579 ti->flags &= ~T_SYNCMODE; 1580 ti->flags |= T_NEGOTIATE; 1581 break; 1582 case SEND_PARITY_ERROR: 1583 sc->sc_omess[0] = MSG_PARITY_ERROR; 1584 break; 1585 case SEND_ABORT: 1586 sc->sc_flags |= ESP_ABORTING; 1587 sc->sc_omess[0] = MSG_ABORT; 1588 break; 1589 case SEND_INIT_DET_ERR: 1590 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1591 break; 1592 case SEND_REJECT: 1593 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1594 break; 1595 default: 1596 ESPCMD(sc, ESPCMD_RSTATN); 1597 sc->sc_flags &= ~ESP_ATN; 1598 sc->sc_omess[0] = MSG_NOOP; 1599 break; 1600 } 1601 sc->sc_omp = sc->sc_omess; 1602 } 1603 1604 #if 1 1605 /* (re)send the message */ 1606 size = min(sc->sc_omlen, sc->sc_maxxfer); 1607 DMA_SETUP(sc->sc_dma, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1608 #ifndef MAC68K_DRIVER 1609 /* Program the SCSI counter */ 1610 ESP_WRITE_REG(sc, ESP_TCL, size); 1611 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 1612 if (sc->sc_cfg2 & ESPCFG2_FE) { 1613 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 1614 } 1615 /* load the count in */ 1616 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 1617 #endif 1618 ESPCMD(sc, ESPCMD_TRANS|ESPCMD_DMA); 1619 DMA_GO(sc->sc_dma); 1620 #else 1621 { int i; 1622 for (i = 0; i < sc->sc_omlen; i++) 1623 ESP_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1624 ESPCMD(sc, ESPCMD_TRANS); 1625 sc->sc_omlen = 0; 1626 } 1627 #endif 1628 } 1629 1630 /* 1631 * This is the most critical part of the driver, and has to know 1632 * how to deal with *all* error conditions and phases from the SCSI 1633 * bus. If there are no errors and the DMA was active, then call the 1634 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1635 * and we can return from here without further processing. 1636 * 1637 * Most of this needs verifying. 1638 */ 1639 int 1640 espintr(sc) 1641 register struct esp_softc *sc; 1642 { 1643 register struct esp_ecb *ecb; 1644 register struct scsi_link *sc_link; 1645 struct esp_tinfo *ti; 1646 int loop; 1647 size_t size; 1648 1649 ESP_TRACE(("[espintr]")); 1650 1651 /* 1652 * I have made some (maybe seriously flawed) assumptions here, 1653 * but basic testing (uncomment the printf() below), show that 1654 * certainly something happens when this loop is here. 1655 * 1656 * The idea is that many of the SCSI operations take very little 1657 * time, and going away and getting interrupted is too high an 1658 * overhead to pay. For example, selecting, sending a message 1659 * and command and then doing some work can be done in one "pass". 1660 * 1661 * The DELAY is not variable because I do not understand that the 1662 * DELAY loop should be fixed-time regardless of CPU speed, but 1663 * I am *assuming* that the faster SCSI processors get things done 1664 * quicker (sending a command byte etc), and so there is no 1665 * need to be too slow. 1666 * 1667 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1668 * at 40Mhz. This needs testing. 1669 */ 1670 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1671 /* a feeling of deja-vu */ 1672 if (!DMA_ISINTR(sc->sc_dma)) 1673 return (loop != 0); 1674 #if 0 1675 if (loop) 1676 printf("*"); 1677 #endif 1678 1679 /* and what do the registers say... */ 1680 espreadregs(sc); 1681 1682 errintr: 1683 sc->sc_intrcnt.ev_count++; 1684 1685 /* 1686 * At the moment, only a SCSI Bus Reset or Illegal 1687 * Command are classed as errors. A disconnect is a 1688 * valid condition, and we let the code check is the 1689 * "ESP_BUSFREE_OK" flag was set before declaring it 1690 * and error. 1691 * 1692 * Also, the status register tells us about "Gross 1693 * Errors" and "Parity errors". Only the Gross Error 1694 * is really bad, and the parity errors are dealt 1695 * with later 1696 * 1697 * TODO 1698 * If there are too many parity error, go to slow 1699 * cable mode ? 1700 */ 1701 1702 /* SCSI Reset */ 1703 if (sc->sc_espintr & ESPINTR_SBR) { 1704 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1705 ESPCMD(sc, ESPCMD_FLUSH); 1706 DELAY(1); 1707 } 1708 if (sc->sc_state != ESP_SBR) { 1709 printf("%s: SCSI bus reset\n", 1710 sc->sc_dev.dv_xname); 1711 esp_init(sc, 0); /* Restart everything */ 1712 return 1; 1713 } 1714 #if 0 1715 /*XXX*/ printf("<expected bus reset: " 1716 "[intr %x, stat %x, step %d]>\n", 1717 sc->sc_espintr, sc->sc_espstat, 1718 sc->sc_espstep); 1719 #endif 1720 if (sc->sc_nexus) 1721 panic("%s: nexus in reset state", 1722 sc->sc_dev.dv_xname); 1723 goto sched; 1724 } 1725 1726 ecb = sc->sc_nexus; 1727 1728 #define ESPINTR_ERR (ESPINTR_SBR|ESPINTR_ILL) 1729 if (sc->sc_espintr & ESPINTR_ERR || 1730 sc->sc_espstat & ESPSTAT_GE) { 1731 1732 if (sc->sc_espstat & ESPSTAT_GE) { 1733 /* no target ? */ 1734 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1735 ESPCMD(sc, ESPCMD_FLUSH); 1736 DELAY(1); 1737 } 1738 if (sc->sc_state == ESP_CONNECTED || 1739 sc->sc_state == ESP_SELECTING) { 1740 ecb->xs->error = XS_DRIVER_STUFFUP; 1741 esp_done(sc, ecb); 1742 } 1743 return 1; 1744 } 1745 1746 if (sc->sc_espintr & ESPINTR_ILL) { 1747 /* illegal command, out of sync ? */ 1748 printf("%s: illegal command: 0x%x (state %d, phase %x, prevphase %x)\n", 1749 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1750 sc->sc_state, sc->sc_phase, 1751 sc->sc_prevphase); 1752 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1753 ESPCMD(sc, ESPCMD_FLUSH); 1754 DELAY(1); 1755 } 1756 esp_init(sc, 0); /* Restart everything */ 1757 return 1; 1758 } 1759 } 1760 1761 /* 1762 * Call if DMA is active. 1763 * 1764 * If DMA_INTR returns true, then maybe go 'round the loop 1765 * again in case there is no more DMA queued, but a phase 1766 * change is expected. 1767 */ 1768 if (DMA_ISACTIVE(sc->sc_dma)) { 1769 DMA_INTR(sc->sc_dma); 1770 /* If DMA active here, then go back to work... */ 1771 if ( (sc->sc_espstat & ESPSTAT_GE) 1772 || (sc->sc_espintr & ESPINTR_ERR)) 1773 goto errintr; 1774 if (DMA_ISACTIVE(sc->sc_dma)) 1775 return 1; 1776 1777 if (sc->sc_dleft == 0 && 1778 (sc->sc_espstat & ESPSTAT_TC) == 0) 1779 printf("%s: !TC [intr %x, stat %x, step %d]" 1780 " prevphase %x, resid %x\n", 1781 sc->sc_dev.dv_xname, 1782 sc->sc_espintr, 1783 sc->sc_espstat, 1784 sc->sc_espstep, 1785 sc->sc_prevphase, 1786 ecb?ecb->dleft:-1); 1787 } 1788 1789 #if 0 /* Unreliable on some ESP revisions? */ 1790 if ((sc->sc_espstat & ESPSTAT_INT) == 0) { 1791 printf("%s: spurious interrupt\n", sc->sc_dev.dv_xname); 1792 return 1; 1793 } 1794 #endif 1795 1796 /* 1797 * check for less serious errors 1798 */ 1799 if (sc->sc_espstat & ESPSTAT_PE) { 1800 printf("%s: SCSI bus parity error\n", 1801 sc->sc_dev.dv_xname); 1802 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1803 esp_sched_msgout(SEND_PARITY_ERROR); 1804 else 1805 esp_sched_msgout(SEND_INIT_DET_ERR); 1806 } 1807 1808 if (sc->sc_espintr & ESPINTR_DIS) { 1809 ESP_MISC(("<DISC [intr %x, stat %x, step %d]>", 1810 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1811 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1812 ESPCMD(sc, ESPCMD_FLUSH); 1813 DELAY(1); 1814 } 1815 /* 1816 * This command must (apparently) be issued within 1817 * 250mS of a disconnect. So here you are... 1818 */ 1819 ESPCMD(sc, ESPCMD_ENSEL); 1820 switch (sc->sc_state) { 1821 case ESP_RESELECTED: 1822 goto sched; 1823 1824 case ESP_SELECTING: 1825 ecb->xs->error = XS_SELTIMEOUT; 1826 goto finish; 1827 1828 case ESP_CONNECTED: 1829 if ((sc->sc_flags & ESP_SYNCHNEGO)) { 1830 #ifdef ESP_DEBUG 1831 if (ecb) 1832 sc_print_addr(ecb->xs->sc_link); 1833 printf("sync nego not completed!\n"); 1834 #endif 1835 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1836 sc->sc_flags &= ~ESP_SYNCHNEGO; 1837 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1838 } 1839 1840 /* it may be OK to disconnect */ 1841 if ((sc->sc_flags & ESP_ABORTING) == 0) { 1842 /* 1843 * Section 5.1.1 of the SCSI 2 spec 1844 * suggests issuing a REQUEST SENSE 1845 * following an unexpected disconnect. 1846 * Some devices go into a contingent 1847 * allegiance condition when 1848 * disconnecting, and this is necessary 1849 * to clean up their state. 1850 */ 1851 printf("%s: unexpected disconnect; ", 1852 sc->sc_dev.dv_xname); 1853 if (ecb->flags & ECB_SENSE) { 1854 printf("resetting\n"); 1855 goto reset; 1856 } 1857 printf("sending REQUEST SENSE\n"); 1858 esp_sense(sc, ecb); 1859 goto out; 1860 } 1861 1862 ecb->xs->error = XS_DRIVER_STUFFUP; 1863 goto finish; 1864 1865 case ESP_DISCONNECT: 1866 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1867 sc->sc_nexus = NULL; 1868 goto sched; 1869 1870 case ESP_CMDCOMPLETE: 1871 goto finish; 1872 } 1873 } 1874 1875 switch (sc->sc_state) { 1876 1877 case ESP_SBR: 1878 printf("%s: waiting for SCSI Bus Reset to happen\n", 1879 sc->sc_dev.dv_xname); 1880 return 1; 1881 1882 case ESP_RESELECTED: 1883 /* 1884 * we must be continuing a message ? 1885 */ 1886 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1887 printf("%s: target didn't identify\n", 1888 sc->sc_dev.dv_xname); 1889 esp_init(sc, 1); 1890 return 1; 1891 } 1892 printf("<<RESELECT CONT'd>>"); 1893 #if XXXX 1894 esp_msgin(sc); 1895 if (sc->sc_state != ESP_CONNECTED) { 1896 /* IDENTIFY fail?! */ 1897 printf("%s: identify failed\n", 1898 sc->sc_dev.dv_xname); 1899 esp_init(sc, 1); 1900 return 1; 1901 } 1902 #endif 1903 break; 1904 1905 case ESP_IDLE: 1906 if (sc->sc_flags & ESP_ICCS) printf("[[esp: BUMMER]]"); 1907 case ESP_SELECTING: 1908 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1909 sc->sc_flags = 0; 1910 1911 if (sc->sc_espintr & ESPINTR_RESEL) { 1912 /* 1913 * If we're trying to select a 1914 * target ourselves, push our command 1915 * back into the ready list. 1916 */ 1917 if (sc->sc_state == ESP_SELECTING) { 1918 ESP_MISC(("backoff selector ")); 1919 sc_link = sc->sc_nexus->xs->sc_link; 1920 ti = &sc->sc_tinfo[sc_link->target]; 1921 TAILQ_INSERT_HEAD(&sc->ready_list, 1922 sc->sc_nexus, chain); 1923 ecb = sc->sc_nexus = NULL; 1924 } 1925 sc->sc_state = ESP_RESELECTED; 1926 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1927 /* 1928 * Things are seriously fucked up. 1929 * Pull the brakes, i.e. reset 1930 */ 1931 printf("%s: target didn't identify\n", 1932 sc->sc_dev.dv_xname); 1933 esp_init(sc, 1); 1934 return 1; 1935 } 1936 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 1937 printf("%s: RESELECT: %d bytes in FIFO!\n", 1938 sc->sc_dev.dv_xname, 1939 ESP_READ_REG(sc, ESP_FFLAG) & 1940 ESPFIFO_FF); 1941 esp_init(sc, 1); 1942 return 1; 1943 } 1944 sc->sc_selid = ESP_READ_REG(sc, ESP_FIFO); 1945 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1946 esp_msgin(sc); /* Handle identify message */ 1947 if (sc->sc_state != ESP_CONNECTED) { 1948 /* IDENTIFY fail?! */ 1949 printf("%s: identify failed\n", 1950 sc->sc_dev.dv_xname); 1951 esp_init(sc, 1); 1952 return 1; 1953 } 1954 continue; /* ie. next phase expected soon */ 1955 } 1956 1957 #define ESPINTR_DONE (ESPINTR_FC|ESPINTR_BS) 1958 if ((sc->sc_espintr & ESPINTR_DONE) == ESPINTR_DONE) { 1959 ecb = sc->sc_nexus; 1960 if (!ecb) 1961 panic("esp: not nexus at sc->sc_nexus"); 1962 1963 sc_link = ecb->xs->sc_link; 1964 ti = &sc->sc_tinfo[sc_link->target]; 1965 1966 switch (sc->sc_espstep) { 1967 case 0: 1968 printf("%s: select timeout/no disconnect\n", 1969 sc->sc_dev.dv_xname); 1970 ecb->xs->error = XS_SELTIMEOUT; 1971 goto finish; 1972 case 1: 1973 if ((ti->flags & T_NEGOTIATE) == 0) { 1974 printf("%s: step 1 & !NEG\n", 1975 sc->sc_dev.dv_xname); 1976 goto reset; 1977 } 1978 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1979 printf("%s: !MSGOUT\n", 1980 sc->sc_dev.dv_xname); 1981 goto reset; 1982 } 1983 /* Start negotiating */ 1984 ti->period = sc->sc_minsync; 1985 ti->offset = 15; 1986 sc->sc_flags |= ESP_SYNCHNEGO; 1987 esp_sched_msgout(SEND_SDTR); 1988 break; 1989 case 3: 1990 /* 1991 * Grr, this is supposed to mean 1992 * "target left command phase 1993 * prematurely". It seems to happen 1994 * regularly when sync mode is on. 1995 * Look at FIFO to see if command 1996 * went out. 1997 * (Timing problems?) 1998 */ 1999 if ((ESP_READ_REG(sc, ESP_FFLAG)&ESPFIFO_FF) == 0) { 2000 /* Hope for the best.. */ 2001 break; 2002 } 2003 printf("(%s:%d:%d): selection failed;" 2004 " %d left in FIFO " 2005 "[intr %x, stat %x, step %d]\n", 2006 sc->sc_dev.dv_xname, 2007 sc_link->target, 2008 sc_link->lun, 2009 ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF, 2010 sc->sc_espintr, sc->sc_espstat, 2011 sc->sc_espstep); 2012 ESPCMD(sc, ESPCMD_FLUSH); 2013 esp_sched_msgout(SEND_ABORT); 2014 return 1; 2015 case 2: 2016 /* Select stuck at Command Phase */ 2017 ESPCMD(sc, ESPCMD_FLUSH); 2018 case 4: 2019 /* So far, everything went fine */ 2020 break; 2021 } 2022 #if 0 2023 if (ecb->xs->flags & SCSI_RESET) 2024 esp_sched_msgout(SEND_DEV_RESET); 2025 else if (ti->flags & T_NEGOTIATE) 2026 esp_sched_msgout( 2027 SEND_IDENTIFY | SEND_SDTR); 2028 else 2029 esp_sched_msgout(SEND_IDENTIFY); 2030 #endif 2031 2032 ecb->flags |= ECB_NEXUS; 2033 ti->lubusy |= (1 << sc_link->lun); 2034 2035 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 2036 /* Do an implicit RESTORE POINTERS. */ 2037 sc->sc_dp = ecb->daddr; 2038 sc->sc_dleft = ecb->dleft; 2039 2040 /* On our first connection, schedule a timeout. */ 2041 if ((ecb->xs->flags & SCSI_POLL) == 0) 2042 timeout(esp_timeout, ecb, (ecb->timeout * hz) / 1000); 2043 2044 sc->sc_state = ESP_CONNECTED; 2045 break; 2046 } else { 2047 printf("%s: unexpected status after select" 2048 ": [intr %x, stat %x, step %x]\n", 2049 sc->sc_dev.dv_xname, 2050 sc->sc_espintr, sc->sc_espstat, 2051 sc->sc_espstep); 2052 ESPCMD(sc, ESPCMD_FLUSH); 2053 DELAY(1); 2054 goto reset; 2055 } 2056 if (sc->sc_state == ESP_IDLE) { 2057 printf("%s: stray interrupt\n", sc->sc_dev.dv_xname); 2058 return 0; 2059 } 2060 break; 2061 2062 case ESP_CONNECTED: 2063 if (sc->sc_flags & ESP_ICCS) { 2064 u_char msg; 2065 2066 sc->sc_flags &= ~ESP_ICCS; 2067 2068 if (!(sc->sc_espintr & ESPINTR_DONE)) { 2069 printf("%s: ICCS: " 2070 ": [intr %x, stat %x, step %x]\n", 2071 sc->sc_dev.dv_xname, 2072 sc->sc_espintr, sc->sc_espstat, 2073 sc->sc_espstep); 2074 } 2075 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 2076 int i = (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) - 2; 2077 while (i--) 2078 (void) ESP_READ_REG(sc, ESP_FIFO); 2079 } 2080 ecb->stat = ESP_READ_REG(sc, ESP_FIFO); 2081 msg = ESP_READ_REG(sc, ESP_FIFO); 2082 ESP_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 2083 if (msg == MSG_CMDCOMPLETE) { 2084 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 2085 sc->sc_state = ESP_CMDCOMPLETE; 2086 } else 2087 printf("%s: STATUS_PHASE: msg %d\n", 2088 sc->sc_dev.dv_xname, msg); 2089 ESPCMD(sc, ESPCMD_MSGOK); 2090 continue; /* ie. wait for disconnect */ 2091 } 2092 break; 2093 default: 2094 panic("%s: invalid state: %d", 2095 sc->sc_dev.dv_xname, 2096 sc->sc_state); 2097 } 2098 2099 /* 2100 * Driver is now in state ESP_CONNECTED, i.e. we 2101 * have a current command working the SCSI bus. 2102 */ 2103 if (sc->sc_state != ESP_CONNECTED || ecb == NULL) { 2104 panic("esp no nexus"); 2105 } 2106 2107 switch (sc->sc_phase) { 2108 case MESSAGE_OUT_PHASE: 2109 ESP_PHASE(("MESSAGE_OUT_PHASE ")); 2110 esp_msgout(sc); 2111 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2112 break; 2113 case MESSAGE_IN_PHASE: 2114 ESP_PHASE(("MESSAGE_IN_PHASE ")); 2115 if (sc->sc_espintr & ESPINTR_BS) { 2116 ESPCMD(sc, ESPCMD_FLUSH); 2117 sc->sc_flags |= ESP_WAITI; 2118 ESPCMD(sc, ESPCMD_TRANS); 2119 } else if (sc->sc_espintr & ESPINTR_FC) { 2120 if ((sc->sc_flags & ESP_WAITI) == 0) { 2121 printf("%s: MSGIN: unexpected FC bit: " 2122 "[intr %x, stat %x, step %x]\n", 2123 sc->sc_dev.dv_xname, 2124 sc->sc_espintr, sc->sc_espstat, 2125 sc->sc_espstep); 2126 } 2127 sc->sc_flags &= ~ESP_WAITI; 2128 esp_msgin(sc); 2129 } else { 2130 printf("%s: MSGIN: weird bits: " 2131 "[intr %x, stat %x, step %x]\n", 2132 sc->sc_dev.dv_xname, 2133 sc->sc_espintr, sc->sc_espstat, 2134 sc->sc_espstep); 2135 } 2136 sc->sc_prevphase = MESSAGE_IN_PHASE; 2137 break; 2138 case COMMAND_PHASE: { 2139 /* well, this means send the command again */ 2140 u_char *cmd = (u_char *)&ecb->cmd; 2141 int i; 2142 2143 ESP_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2144 ecb->cmd.opcode, ecb->clen)); 2145 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 2146 ESPCMD(sc, ESPCMD_FLUSH); 2147 DELAY(1); 2148 } 2149 /* Now the command into the FIFO */ 2150 for (i = 0; i < ecb->clen; i++) 2151 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 2152 ESPCMD(sc, ESPCMD_TRANS); 2153 sc->sc_prevphase = COMMAND_PHASE; 2154 } 2155 break; 2156 case DATA_OUT_PHASE: 2157 ESP_PHASE(("DATA_OUT_PHASE [%d] ", sc->sc_dleft)); 2158 ESPCMD(sc, ESPCMD_FLUSH); 2159 size = min(sc->sc_dleft, sc->sc_maxxfer); 2160 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2161 0, &size); 2162 sc->sc_prevphase = DATA_OUT_PHASE; 2163 goto setup_xfer; 2164 case DATA_IN_PHASE: 2165 ESP_PHASE(("DATA_IN_PHASE ")); 2166 if (sc->sc_rev == ESP100) 2167 ESPCMD(sc, ESPCMD_FLUSH); 2168 size = min(sc->sc_dleft, sc->sc_maxxfer); 2169 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2170 1, &size); 2171 sc->sc_prevphase = DATA_IN_PHASE; 2172 setup_xfer: 2173 #ifdef MAC68K_DRIVER 2174 if (!size) { 2175 #endif 2176 /* Program the SCSI counter */ 2177 ESP_WRITE_REG(sc, ESP_TCL, size); 2178 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 2179 if (sc->sc_cfg2 & ESPCFG2_FE) { 2180 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 2181 } 2182 /* load the count in */ 2183 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 2184 #ifdef MAC68K_DRIVER 2185 } 2186 #endif 2187 2188 /* 2189 * Note that if `size' is 0, we've already transceived 2190 * all the bytes we want but we're still in DATA PHASE. 2191 * Apparently, the device needs padding. Also, a 2192 * transfer size of 0 means "maximum" to the chip 2193 * DMA logic. 2194 */ 2195 ESPCMD(sc, 2196 (size==0?ESPCMD_TRPAD:ESPCMD_TRANS)|ESPCMD_DMA); 2197 DMA_GO(sc->sc_dma); 2198 return 1; 2199 case STATUS_PHASE: 2200 ESP_PHASE(("STATUS_PHASE ")); 2201 sc->sc_flags |= ESP_ICCS; 2202 ESPCMD(sc, ESPCMD_ICCS); 2203 sc->sc_prevphase = STATUS_PHASE; 2204 break; 2205 case INVALID_PHASE: 2206 break; 2207 default: 2208 printf("%s: unexpected bus phase; resetting\n", 2209 sc->sc_dev.dv_xname); 2210 goto reset; 2211 } 2212 } 2213 panic("esp: should not get here.."); 2214 2215 reset: 2216 esp_init(sc, 1); 2217 return 1; 2218 2219 finish: 2220 untimeout(esp_timeout, ecb); 2221 esp_done(sc, ecb); 2222 goto out; 2223 2224 sched: 2225 sc->sc_state = ESP_IDLE; 2226 esp_sched(sc); 2227 goto out; 2228 2229 out: 2230 return 1; 2231 } 2232 2233 void 2234 esp_abort(sc, ecb) 2235 struct esp_softc *sc; 2236 struct esp_ecb *ecb; 2237 { 2238 2239 /* 2 secs for the abort */ 2240 ecb->timeout = ESP_ABORT_TIMEOUT; 2241 ecb->flags |= ECB_ABORT; 2242 2243 if (ecb == sc->sc_nexus) { 2244 /* 2245 * If we're still selecting, the message will be scheduled 2246 * after selection is complete. 2247 */ 2248 if (sc->sc_state == ESP_CONNECTED) 2249 esp_sched_msgout(SEND_ABORT); 2250 } else { 2251 esp_dequeue(sc, ecb); 2252 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2253 if (sc->sc_state == ESP_IDLE) 2254 esp_sched(sc); 2255 } 2256 } 2257 2258 void 2259 esp_timeout(arg) 2260 void *arg; 2261 { 2262 struct esp_ecb *ecb = arg; 2263 struct scsi_xfer *xs = ecb->xs; 2264 struct scsi_link *sc_link = xs->sc_link; 2265 struct esp_softc *sc = sc_link->adapter_softc; 2266 int s; 2267 2268 sc_print_addr(sc_link); 2269 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2270 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) %s>", 2271 sc->sc_dev.dv_xname, 2272 ecb, ecb->flags, ecb->dleft, ecb->stat, 2273 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2274 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2275 DMA_ISACTIVE(sc->sc_dma) ? "DMA active" : ""); 2276 #if ESP_DEBUG > 0 2277 printf("TRACE: %s.", ecb->trace); 2278 #endif 2279 2280 s = splbio(); 2281 2282 if (ecb->flags & ECB_ABORT) { 2283 /* abort timed out */ 2284 printf(" AGAIN\n"); 2285 esp_init(sc, 1); 2286 } else { 2287 /* abort the operation that has timed out */ 2288 printf("\n"); 2289 xs->error = XS_TIMEOUT; 2290 esp_abort(sc, ecb); 2291 } 2292 2293 splx(s); 2294 } 2295
Indexes created Wed Oct 22 13:09:56 GMT 2025