esp.c revision 1.5
1 /* $NetBSD: esp.c,v 1.5 1996/12/10 21:27:39 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <scsi/scsi_all.h> 85 #include <scsi/scsiconf.h> 86 #include <scsi/scsi_message.h> 87 88 #include <machine/cpu.h> 89 #include <machine/param.h> 90 91 #if defined(__sparc__) 92 #define SPARC_DRIVER 93 #include <machine/autoconf.h> 94 #include <sparc/dev/sbusvar.h> 95 #include <sparc/dev/dmareg.h> 96 #include <sparc/dev/dmavar.h> 97 #include <sparc/dev/espreg.h> 98 #include <sparc/dev/espvar.h> 99 #else 100 #if (_MACHINE == mac68k) 101 #define MAC68K_DRIVER 102 #include <machine/viareg.h> 103 104 struct dma_softc { 105 struct esp_softc *sc_esp; 106 int sc_active; 107 int sc_tc; 108 int sc_datain; 109 size_t sc_dmasize; 110 size_t sc_dmatrans; 111 char **sc_dmaaddr; 112 size_t *sc_pdmalen; 113 }; 114 115 #include <mac68k/dev/espreg.h> 116 #include <mac68k/dev/espvar.h> 117 #undef ESPCMD_DMA 118 #define ESPCMD_DMA 0 /* No DMA */ 119 #undef ESPCMD_TRPAD 120 #define ESPCMD_TRPAD 0x98 /* TRPAD needs DMA flag*/ 121 122 static __inline__ void dma_intr __P((struct dma_softc *sc)); 123 124 static __inline__ void 125 dma_intr(sc) 126 struct dma_softc *sc; 127 { 128 register struct esp_softc *sc_esp; 129 register u_char *p; 130 register u_int espphase, espstat, espintr; 131 register int cnt; 132 133 if (sc->sc_active == 0) { 134 printf("dma_intr--inactive DMA\n"); 135 return; 136 } 137 138 if ((sc->sc_esp->sc_espintr & ESPINTR_BS) == 0) { 139 sc->sc_active = 0; 140 return; 141 } 142 143 cnt = *sc->sc_pdmalen; 144 if (*sc->sc_pdmalen == 0) { 145 printf("data interrupt, but no count left."); 146 } 147 148 p = *sc->sc_dmaaddr; 149 sc_esp = sc->sc_esp; 150 espphase = sc_esp->sc_phase; 151 espstat = (u_int) sc_esp->sc_espstat; 152 espintr = (u_int) sc_esp->sc_espintr; 153 do { 154 if (sc->sc_datain) { 155 *p++ = ESP_READ_REG(sc_esp, ESP_FIFO); 156 cnt--; 157 if (espphase == DATA_IN_PHASE) { 158 ESPCMD(sc_esp, ESPCMD_TRANS); 159 } else { 160 sc->sc_active = 0; 161 } 162 } else { 163 if ( (espphase == DATA_OUT_PHASE) 164 || (espphase == MESSAGE_OUT_PHASE)) { 165 ESP_WRITE_REG(sc_esp, ESP_FIFO, *p++); 166 cnt--; 167 ESPCMD(sc_esp, ESPCMD_TRANS); 168 } else { 169 sc->sc_active = 0; 170 } 171 } 172 173 if (sc->sc_active) { 174 while (!DMA_ISINTR(sc)); 175 espstat = ESP_READ_REG(sc_esp, ESP_STAT); 176 espintr = ESP_READ_REG(sc_esp, ESP_INTR); 177 espphase = (espintr & ESPINTR_DIS) 178 ? /* Disconnected */ BUSFREE_PHASE 179 : espstat & ESPSTAT_PHASE; 180 } 181 } while (sc->sc_active && (espintr & ESPINTR_BS)); 182 sc_esp->sc_phase = espphase; 183 sc_esp->sc_espstat = (u_char) espstat; 184 sc_esp->sc_espintr = (u_char) espintr; 185 *sc->sc_dmaaddr = p; 186 *sc->sc_pdmalen = cnt; 187 188 if (*sc->sc_pdmalen == 0) { 189 sc->sc_tc = ESPSTAT_TC; 190 } 191 sc->sc_esp->sc_espstat |= sc->sc_tc; 192 } 193 #else 194 #include <dev/tc/tcvar.h> 195 #include <alpha/tc/tcdsvar.h> 196 #include <alpha/tc/espreg.h> 197 #include <alpha/tc/espvar.h> 198 #endif 199 #endif 200 201 int esp_debug = 0; /*ESP_SHOWPHASE|ESP_SHOWMISC|ESP_SHOWTRAC|ESP_SHOWCMDS;*/ 202 203 /*static*/ void espattach __P((struct device *, struct device *, void *)); 204 /*static*/ int espmatch __P((struct device *, void *, void *)); 205 /*static*/ u_int esp_adapter_info __P((struct esp_softc *)); 206 /*static*/ void espreadregs __P((struct esp_softc *)); 207 /*static*/ void esp_select __P((struct esp_softc *, struct esp_ecb *)); 208 /*static*/ int esp_reselect __P((struct esp_softc *, int)); 209 /*static*/ void esp_scsi_reset __P((struct esp_softc *)); 210 /*static*/ void esp_reset __P((struct esp_softc *)); 211 /*static*/ void esp_init __P((struct esp_softc *, int)); 212 /*static*/ int esp_scsi_cmd __P((struct scsi_xfer *)); 213 /*static*/ int esp_poll __P((struct esp_softc *, struct scsi_xfer *, int)); 214 /*static*/ void esp_sched __P((struct esp_softc *)); 215 /*static*/ void esp_done __P((struct esp_softc *, struct esp_ecb *)); 216 /*static*/ void esp_msgin __P((struct esp_softc *)); 217 /*static*/ void esp_msgout __P((struct esp_softc *)); 218 /*static*/ int espintr __P((struct esp_softc *)); 219 /*static*/ void esp_timeout __P((void *arg)); 220 /*static*/ void esp_abort __P((struct esp_softc *, struct esp_ecb *)); 221 /*static*/ void esp_dequeue __P((struct esp_softc *, struct esp_ecb *)); 222 void esp_sense __P((struct esp_softc *, struct esp_ecb *)); 223 void esp_free_ecb __P((struct esp_softc *, struct esp_ecb *, int)); 224 struct esp_ecb *esp_get_ecb __P((struct esp_softc *, int)); 225 static inline int esp_stp2cpb __P((struct esp_softc *, int)); 226 static inline int esp_cpb2stp __P((struct esp_softc *, int)); 227 static inline void esp_setsync __P((struct esp_softc *, struct esp_tinfo *)); 228 229 /* Linkup to the rest of the kernel */ 230 struct cfattach esp_ca = { 231 sizeof(struct esp_softc), espmatch, espattach 232 }; 233 234 struct cfdriver esp_cd = { 235 NULL, "esp", DV_DULL 236 }; 237 238 struct scsi_adapter esp_switch = { 239 esp_scsi_cmd, 240 minphys, /* no max at this level; handled by DMA code */ 241 NULL, 242 NULL, 243 }; 244 245 struct scsi_device esp_dev = { 246 NULL, /* Use default error handler */ 247 NULL, /* have a queue, served by this */ 248 NULL, /* have no async handler */ 249 NULL, /* Use default 'done' routine */ 250 }; 251 252 int 253 espmatch(parent, vcf, aux) 254 struct device *parent; 255 void *vcf, *aux; 256 { 257 struct cfdata *cf = vcf; 258 #ifdef SPARC_DRIVER 259 register struct confargs *ca = aux; 260 register struct romaux *ra = &ca->ca_ra; 261 262 if (strcmp(cf->cf_driver->cd_name, ra->ra_name)) 263 return (0); 264 if (ca->ca_bustype == BUS_SBUS) 265 return (1); 266 ra->ra_len = NBPG; 267 return (probeget(ra->ra_vaddr, 1) != -1); 268 #else 269 #ifdef MAC68K_DRIVER 270 if ((cf->cf_unit == 0) && mac68k_machine.scsi96) 271 return (1); 272 if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) 273 return (1); 274 return (0); 275 #else 276 struct tcdsdev_attach_args *tcdsdev = aux; 277 278 if (strncmp(tcdsdev->tcdsda_modname, "PMAZ-AA ", TC_ROM_LLEN)) 279 return (0); 280 return (!tc_badaddr(tcdsdev->tcdsda_addr)); 281 #endif 282 #endif 283 } 284 285 /* 286 * Attach this instance, and then all the sub-devices 287 */ 288 void 289 espattach(parent, self, aux) 290 struct device *parent, *self; 291 void *aux; 292 { 293 #ifdef SPARC_DRIVER 294 register struct confargs *ca = aux; 295 #else 296 #ifdef MAC68K_DRIVER 297 extern vm_offset_t SCSIBase; 298 #else 299 register struct tcdsdev_attach_args *tcdsdev = aux; 300 #endif 301 #endif 302 struct esp_softc *sc = (void *)self; 303 #ifdef SPARC_DRIVER 304 struct bootpath *bp; 305 int dmachild = strncmp(parent->dv_xname, "dma", 3) == 0; 306 #endif 307 308 #ifdef SPARC_DRIVER 309 /* 310 * Make sure things are sane. I don't know if this is ever 311 * necessary, but it seem to be in all of Torek's code. 312 */ 313 if (ca->ca_ra.ra_nintr != 1) { 314 printf(": expected 1 interrupt, got %d\n", ca->ca_ra.ra_nintr); 315 return; 316 } 317 318 sc->sc_pri = ca->ca_ra.ra_intr[0].int_pri; 319 printf(" pri %d", sc->sc_pri); 320 321 /* 322 * Map my registers in, if they aren't already in virtual 323 * address space. 324 */ 325 if (ca->ca_ra.ra_vaddr) 326 sc->sc_reg = (volatile u_char *) ca->ca_ra.ra_vaddr; 327 else { 328 sc->sc_reg = (volatile u_char *) 329 mapiodev(ca->ca_ra.ra_reg, 0, ca->ca_ra.ra_len, ca->ca_bustype); 330 } 331 #else 332 #ifdef MAC68K_DRIVER 333 if (sc->sc_dev.dv_unit == 0) { 334 unsigned long reg_offset; 335 336 sc->sc_reg = (volatile u_char *) SCSIBase; 337 mac68k_register_scsi_irq((void (*)(void *)) espintr, sc); 338 sc->irq_mask = V2IF_SCSIIRQ; 339 reg_offset = SCSIBase - IOBase; 340 if (reg_offset == 0x10000) { 341 sc->sc_freq = 16500000; 342 } else { 343 sc->sc_freq = 25000000; 344 } 345 } else { 346 sc->sc_reg = (volatile u_char *) SCSIBase + 0x402; 347 mac68k_register_scsi_b_irq((void (*)(void *)) espintr, sc); 348 sc->irq_mask = V2IF_SCSIDRQ; 349 sc->sc_freq = 25000000; 350 } 351 sc->sc_dma = &sc->_sc_dma; 352 printf(": address %p", sc->sc_reg); 353 354 sc->sc_id = 7; 355 #else 356 sc->sc_reg = (volatile u_int32_t *)tcdsdev->tcdsda_addr; 357 sc->sc_cookie = tcdsdev->tcdsda_cookie; 358 sc->sc_dma = tcdsdev->tcdsda_sc; 359 360 printf(": address %x", sc->sc_reg); 361 tcds_intr_establish(parent, sc->sc_cookie, TC_IPL_BIO, 362 (int (*)(void *))espintr, sc); 363 #endif 364 #endif 365 366 #ifdef SPARC_DRIVER 367 /* Other settings */ 368 sc->sc_node = ca->ca_ra.ra_node; 369 if (ca->ca_bustype == BUS_SBUS) { 370 sc->sc_id = getpropint(sc->sc_node, "initiator-id", 7); 371 sc->sc_freq = getpropint(sc->sc_node, "clock-frequency", -1); 372 } else { 373 sc->sc_id = 7; 374 sc->sc_freq = 24000000; 375 } 376 if (sc->sc_freq < 0) 377 sc->sc_freq = ((struct sbus_softc *) 378 sc->sc_dev.dv_parent)->sc_clockfreq; 379 #else 380 #ifdef MAC68K_DRIVER 381 #else 382 if (parent->dv_cfdata->cf_driver == &tcds_cd) { 383 sc->sc_id = tcdsdev->tcdsda_id; 384 sc->sc_freq = tcdsdev->tcdsda_freq; 385 } else { 386 /* XXX */ 387 sc->sc_id = 7; 388 sc->sc_freq = 24000000; 389 } 390 #endif 391 #endif 392 393 /* gimme Mhz */ 394 sc->sc_freq /= 1000000; 395 396 #ifdef SPARC_DRIVER 397 if (dmachild) { 398 sc->sc_dma = (struct dma_softc *)parent; 399 sc->sc_dma->sc_esp = sc; 400 } else { 401 /* 402 * find the DMA by poking around the dma device structures 403 * 404 * What happens here is that if the dma driver has not been 405 * configured, then this returns a NULL pointer. Then when the 406 * dma actually gets configured, it does the opposing test, and 407 * if the sc->sc_esp field in it's softc is NULL, then tries to 408 * find the matching esp driver. 409 * 410 */ 411 sc->sc_dma = (struct dma_softc *) 412 getdevunit("dma", sc->sc_dev.dv_unit); 413 414 /* 415 * and a back pointer to us, for DMA 416 */ 417 if (sc->sc_dma) 418 sc->sc_dma->sc_esp = sc; 419 else 420 panic("espattach: no dma found"); 421 } 422 #else 423 sc->sc_dma->sc_esp = sc; /* XXX */ 424 #endif 425 426 /* 427 * It is necessary to try to load the 2nd config register here, 428 * to find out what rev the esp chip is, else the esp_reset 429 * will not set up the defaults correctly. 430 */ 431 sc->sc_cfg1 = sc->sc_id | ESPCFG1_PARENB; 432 #ifdef SPARC_DRIVER 433 sc->sc_cfg2 = ESPCFG2_SCSI2 | ESPCFG2_RPE; 434 sc->sc_cfg3 = ESPCFG3_CDB; 435 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 436 437 if ((ESP_READ_REG(sc, ESP_CFG2) & ~ESPCFG2_RSVD) != (ESPCFG2_SCSI2 | ESPCFG2_RPE)) { 438 printf(": ESP100"); 439 sc->sc_rev = ESP100; 440 } else { 441 sc->sc_cfg2 = ESPCFG2_SCSI2; 442 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 443 sc->sc_cfg3 = 0; 444 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 445 sc->sc_cfg3 = (ESPCFG3_CDB | ESPCFG3_FCLK); 446 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 447 if (ESP_READ_REG(sc, ESP_CFG3) != (ESPCFG3_CDB | ESPCFG3_FCLK)) { 448 printf(": ESP100A"); 449 sc->sc_rev = ESP100A; 450 } else { 451 /* ESPCFG2_FE enables > 64K transfers */ 452 sc->sc_cfg2 |= ESPCFG2_FE; 453 sc->sc_cfg3 = 0; 454 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 455 printf(": ESP200"); 456 sc->sc_rev = ESP200; 457 } 458 } 459 #else 460 #ifdef MAC68K_DRIVER 461 sc->sc_cfg2 = ESPCFG2_SCSI2; 462 sc->sc_cfg3 = 0; 463 printf(": NCR53C96"); 464 sc->sc_rev = NCR53C96; 465 #else 466 sc->sc_cfg2 = ESPCFG2_SCSI2; 467 sc->sc_cfg3 = 0x4; /* Save residual byte. XXX??? */ 468 printf(": NCR53C94"); 469 sc->sc_rev = NCR53C94; 470 #endif 471 #endif 472 473 /* 474 * This is the value used to start sync negotiations 475 * Note that the ESP register "SYNCTP" is programmed 476 * in "clocks per byte", and has a minimum value of 4. 477 * The SCSI period used in negotiation is one-fourth 478 * of the time (in nanoseconds) needed to transfer one byte. 479 * Since the chip's clock is given in MHz, we have the following 480 * formula: 4 * period = (1000 / freq) * 4 481 */ 482 sc->sc_minsync = 1000 / sc->sc_freq; 483 484 #ifdef SPARC_DRIVER 485 /* 486 * Alas, we must now modify the value a bit, because it's 487 * only valid when can switch on FASTCLK and FASTSCSI bits 488 * in config register 3... 489 */ 490 switch (sc->sc_rev) { 491 case ESP100: 492 sc->sc_maxxfer = 64 * 1024; 493 sc->sc_minsync = 0; /* No synch on old chip? */ 494 break; 495 case ESP100A: 496 sc->sc_maxxfer = 64 * 1024; 497 sc->sc_minsync = esp_cpb2stp(sc, 5); /* Min clocks/byte is 5 */ 498 break; 499 case ESP200: 500 sc->sc_maxxfer = 16 * 1024 * 1024; 501 /* XXX - do actually set FAST* bits */ 502 } 503 #else 504 #ifdef MAC68K_DRIVER 505 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */ 506 /* Really no limit, but since we want to fit into the TCR... */ 507 sc->sc_maxxfer = 64 * 1024; 508 #else 509 sc->sc_maxxfer = 64 * 1024; 510 #endif 511 #endif 512 513 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 514 515 /* The value *must not* be == 1. Make it 2 */ 516 if (sc->sc_ccf == 1) 517 sc->sc_ccf = 2; 518 519 /* 520 * The recommended timeout is 250ms. This register is loaded 521 * with a value calculated as follows, from the docs: 522 * 523 * (timout period) x (CLK frequency) 524 * reg = ------------------------------------- 525 * 8192 x (Clock Conversion Factor) 526 * 527 * Since CCF has a linear relation to CLK, this generally computes 528 * to the constant of 153. 529 */ 530 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 531 532 /* CCF register only has 3 bits; 0 is actually 8 */ 533 sc->sc_ccf &= 7; 534 535 /* Reset state & bus */ 536 sc->sc_state = 0; 537 esp_init(sc, 1); 538 539 printf(" %dMhz, target %d\n", sc->sc_freq, sc->sc_id); 540 541 #ifdef SPARC_DRIVER 542 /* add me to the sbus structures */ 543 sc->sc_sd.sd_reset = (void *) esp_reset; 544 #if defined(SUN4C) || defined(SUN4M) 545 if (ca->ca_bustype == BUS_SBUS) { 546 if (dmachild) 547 sbus_establish(&sc->sc_sd, sc->sc_dev.dv_parent); 548 else 549 sbus_establish(&sc->sc_sd, &sc->sc_dev); 550 } 551 #endif /* SUN4C || SUN4M */ 552 #endif 553 554 #ifdef SPARC_DRIVER 555 /* and the interuppts */ 556 sc->sc_ih.ih_fun = (void *) espintr; 557 sc->sc_ih.ih_arg = sc; 558 intr_establish(sc->sc_pri, &sc->sc_ih); 559 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 560 #endif 561 562 /* 563 * fill in the prototype scsi_link. 564 */ 565 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 566 sc->sc_link.adapter_softc = sc; 567 sc->sc_link.adapter_target = sc->sc_id; 568 sc->sc_link.adapter = &esp_switch; 569 sc->sc_link.device = &esp_dev; 570 sc->sc_link.openings = 2; 571 sc->sc_link.max_target = 7; 572 573 /* 574 * If the boot path is "esp" at the moment and it's me, then 575 * walk our pointer to the sub-device, ready for the config 576 * below. 577 */ 578 #ifdef SPARC_DRIVER 579 bp = ca->ca_ra.ra_bp; 580 switch (ca->ca_bustype) { 581 case BUS_SBUS: 582 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 583 SAME_ESP(sc, bp, ca)) 584 bootpath_store(1, bp + 1); 585 break; 586 default: 587 if (bp != NULL && strcmp(bp->name, "esp") == 0 && 588 bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit) 589 bootpath_store(1, bp + 1); 590 break; 591 } 592 #endif 593 594 /* 595 * Now try to attach all the sub-devices 596 */ 597 config_found(self, &sc->sc_link, scsiprint); 598 599 #ifdef MAC68K_DRIVER 600 via2_reg(vPCR) = 0x22; 601 via2_reg(vIFR) = sc->irq_mask; 602 via2_reg(vIER) = 0x80 | sc->irq_mask; 603 #endif 604 #ifdef SPARC_DRIVER 605 bootpath_store(1, NULL); 606 #endif 607 } 608 609 /* 610 * This is the generic esp reset function. It does not reset the SCSI bus, 611 * only this controllers, but kills any on-going commands, and also stops 612 * and resets the DMA. 613 * 614 * After reset, registers are loaded with the defaults from the attach 615 * routine above. 616 */ 617 void 618 esp_reset(sc) 619 struct esp_softc *sc; 620 { 621 622 /* reset DMA first */ 623 DMA_RESET(sc->sc_dma); 624 625 /* reset SCSI chip */ 626 ESPCMD(sc, ESPCMD_RSTCHIP); 627 ESPCMD(sc, ESPCMD_NOP); 628 DELAY(500); 629 630 /* do these backwards, and fall through */ 631 switch (sc->sc_rev) { 632 #ifndef SPARC_DRIVER 633 case NCR53C96: 634 case NCR53C94: 635 #endif 636 case ESP200: 637 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 638 case ESP100A: 639 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 640 case ESP100: 641 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 642 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 643 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 644 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 645 break; 646 default: 647 printf("%s: unknown revision code, assuming ESP100\n", 648 sc->sc_dev.dv_xname); 649 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 650 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 651 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 652 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 653 } 654 } 655 656 /* 657 * Reset the SCSI bus, but not the chip 658 */ 659 void 660 esp_scsi_reset(sc) 661 struct esp_softc *sc; 662 { 663 #ifdef SPARC_DRIVER 664 /* stop DMA first, as the chip will return to Bus Free phase */ 665 DMACSR(sc->sc_dma) &= ~D_EN_DMA; 666 #else 667 /* 668 * XXX STOP DMA FIRST 669 */ 670 #endif 671 672 printf("esp: resetting SCSI bus\n"); 673 ESPCMD(sc, ESPCMD_RSTSCSI); 674 } 675 676 /* 677 * Initialize esp state machine 678 */ 679 void 680 esp_init(sc, doreset) 681 struct esp_softc *sc; 682 int doreset; 683 { 684 struct esp_ecb *ecb; 685 int r; 686 687 ESP_TRACE(("[ESP_INIT(%d)] ", doreset)); 688 689 if (sc->sc_state == 0) { 690 /* First time through; initialize. */ 691 TAILQ_INIT(&sc->ready_list); 692 TAILQ_INIT(&sc->nexus_list); 693 TAILQ_INIT(&sc->free_list); 694 sc->sc_nexus = NULL; 695 ecb = sc->sc_ecb; 696 bzero(ecb, sizeof(sc->sc_ecb)); 697 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 698 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 699 ecb++; 700 } 701 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 702 } else { 703 /* Cancel any active commands. */ 704 sc->sc_state = ESP_CLEANING; 705 if ((ecb = sc->sc_nexus) != NULL) { 706 ecb->xs->error = XS_DRIVER_STUFFUP; 707 untimeout(esp_timeout, ecb); 708 esp_done(sc, ecb); 709 } 710 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 711 ecb->xs->error = XS_DRIVER_STUFFUP; 712 untimeout(esp_timeout, ecb); 713 esp_done(sc, ecb); 714 } 715 } 716 717 /* 718 * reset the chip to a known state 719 */ 720 esp_reset(sc); 721 722 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 723 for (r = 0; r < 8; r++) { 724 struct esp_tinfo *ti = &sc->sc_tinfo[r]; 725 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 726 int fl = sc->sc_dev.dv_cfdata->cf_flags; 727 728 ti->flags = ((sc->sc_minsync && !(fl & (1<<(r+8)))) 729 ? T_NEGOTIATE : 0) | 730 ((fl & (1<<r)) ? T_RSELECTOFF : 0) | 731 T_NEED_TO_RESET; 732 ti->period = sc->sc_minsync; 733 ti->offset = 0; 734 } 735 736 if (doreset) { 737 sc->sc_state = ESP_SBR; 738 ESPCMD(sc, ESPCMD_RSTSCSI); 739 } else { 740 sc->sc_state = ESP_IDLE; 741 } 742 } 743 744 /* 745 * Read the ESP registers, and save their contents for later use. 746 * ESP_STAT, ESP_STEP & ESP_INTR are mostly zeroed out when reading 747 * ESP_INTR - so make sure it is the last read. 748 * 749 * I think that (from reading the docs) most bits in these registers 750 * only make sense when he DMA CSR has an interrupt showing. Call only 751 * if an interrupt is pending. 752 */ 753 void 754 espreadregs(sc) 755 struct esp_softc *sc; 756 { 757 758 sc->sc_espstat = ESP_READ_REG(sc, ESP_STAT); 759 /* Only the stepo bits are of interest */ 760 sc->sc_espstep = ESP_READ_REG(sc, ESP_STEP) & ESPSTEP_MASK; 761 sc->sc_espintr = ESP_READ_REG(sc, ESP_INTR); 762 763 #if !defined(SPARC_DRIVER) && !defined(MAC68K_DRIVER) 764 /* Clear the TCDS interrupt bit. */ 765 (void)tcds_scsi_isintr(sc->sc_dma, 1); 766 #endif 767 768 /* 769 * Determine the SCSI bus phase, return either a real SCSI bus phase 770 * or some pseudo phase we use to detect certain exceptions. 771 */ 772 773 sc->sc_phase = (sc->sc_espintr & ESPINTR_DIS) 774 ? /* Disconnected */ BUSFREE_PHASE 775 : sc->sc_espstat & ESPSTAT_PHASE; 776 777 ESP_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 778 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 779 } 780 781 /* 782 * Convert chip register Clock Per Byte value to Synchronous Transfer Period. 783 */ 784 static inline int 785 esp_cpb2stp(sc, cpb) 786 struct esp_softc *sc; 787 int cpb; 788 { 789 return ((250 * cpb) / sc->sc_freq); 790 } 791 792 /* 793 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 794 */ 795 static inline int 796 esp_stp2cpb(sc, period) 797 struct esp_softc *sc; 798 int period; 799 { 800 int v; 801 v = (sc->sc_freq * period) / 250; 802 if (esp_cpb2stp(sc, v) < period) 803 /* Correct round-down error */ 804 v++; 805 return v; 806 } 807 808 static inline void 809 esp_setsync(sc, ti) 810 struct esp_softc *sc; 811 struct esp_tinfo *ti; 812 { 813 814 if (ti->flags & T_SYNCMODE) { 815 ESP_WRITE_REG(sc, ESP_SYNCOFF, ti->offset); 816 ESP_WRITE_REG(sc, ESP_SYNCTP, esp_stp2cpb(sc, ti->period)); 817 } else { 818 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 819 ESP_WRITE_REG(sc, ESP_SYNCTP, 0); 820 } 821 } 822 823 /* 824 * Send a command to a target, set the driver state to ESP_SELECTING 825 * and let the caller take care of the rest. 826 * 827 * Keeping this as a function allows me to say that this may be done 828 * by DMA instead of programmed I/O soon. 829 */ 830 void 831 esp_select(sc, ecb) 832 struct esp_softc *sc; 833 struct esp_ecb *ecb; 834 { 835 struct scsi_link *sc_link = ecb->xs->sc_link; 836 int target = sc_link->target; 837 struct esp_tinfo *ti = &sc->sc_tinfo[target]; 838 u_char *cmd; 839 int clen; 840 841 ESP_TRACE(("[esp_select(t%d,l%d,cmd:%x)] ", sc_link->target, sc_link->lun, ecb->cmd.opcode)); 842 843 /* new state ESP_SELECTING */ 844 sc->sc_state = ESP_SELECTING; 845 846 ESPCMD(sc, ESPCMD_FLUSH); 847 848 /* 849 * The docs say the target register is never reset, and I 850 * can't think of a better place to set it 851 */ 852 ESP_WRITE_REG(sc, ESP_SELID, target); 853 esp_setsync(sc, ti); 854 855 /* 856 * Who am I. This is where we tell the target that we are 857 * happy for it to disconnect etc. 858 */ 859 ESP_WRITE_REG(sc, ESP_FIFO, 860 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 861 862 if (ti->flags & T_NEGOTIATE) { 863 /* Arbitrate, select and stop after IDENTIFY message */ 864 ESPCMD(sc, ESPCMD_SELATNS); 865 return; 866 } 867 868 /* Now the command into the FIFO */ 869 cmd = (u_char *)&ecb->cmd; 870 clen = ecb->clen; 871 while (clen--) 872 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 873 874 /* And get the targets attention */ 875 ESPCMD(sc, ESPCMD_SELATN); 876 } 877 878 void 879 esp_free_ecb(sc, ecb, flags) 880 struct esp_softc *sc; 881 struct esp_ecb *ecb; 882 int flags; 883 { 884 int s; 885 886 s = splbio(); 887 888 ecb->flags = 0; 889 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 890 891 /* 892 * If there were none, wake anybody waiting for one to come free, 893 * starting with queued entries. 894 */ 895 if (ecb->chain.tqe_next == 0) 896 wakeup(&sc->free_list); 897 898 splx(s); 899 } 900 901 struct esp_ecb * 902 esp_get_ecb(sc, flags) 903 struct esp_softc *sc; 904 int flags; 905 { 906 struct esp_ecb *ecb; 907 int s; 908 909 s = splbio(); 910 911 while ((ecb = sc->free_list.tqh_first) == NULL && 912 (flags & SCSI_NOSLEEP) == 0) 913 tsleep(&sc->free_list, PRIBIO, "especb", 0); 914 if (ecb) { 915 TAILQ_REMOVE(&sc->free_list, ecb, chain); 916 ecb->flags |= ECB_ALLOC; 917 } 918 919 splx(s); 920 return ecb; 921 } 922 923 /* 924 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 925 */ 926 927 /* 928 * Start a SCSI-command 929 * This function is called by the higher level SCSI-driver to queue/run 930 * SCSI-commands. 931 */ 932 int 933 esp_scsi_cmd(xs) 934 struct scsi_xfer *xs; 935 { 936 struct scsi_link *sc_link = xs->sc_link; 937 struct esp_softc *sc = sc_link->adapter_softc; 938 struct esp_ecb *ecb; 939 int s, flags; 940 941 ESP_TRACE(("[esp_scsi_cmd] ")); 942 ESP_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 943 sc_link->target)); 944 945 flags = xs->flags; 946 if ((ecb = esp_get_ecb(sc, flags)) == NULL) { 947 xs->error = XS_DRIVER_STUFFUP; 948 return TRY_AGAIN_LATER; 949 } 950 951 /* Initialize ecb */ 952 ecb->xs = xs; 953 ecb->timeout = xs->timeout; 954 955 if (xs->flags & SCSI_RESET) { 956 ecb->flags |= ECB_RESET; 957 ecb->clen = 0; 958 ecb->dleft = 0; 959 } else { 960 bcopy(xs->cmd, &ecb->cmd, xs->cmdlen); 961 ecb->clen = xs->cmdlen; 962 ecb->daddr = xs->data; 963 ecb->dleft = xs->datalen; 964 } 965 ecb->stat = 0; 966 967 s = splbio(); 968 969 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 970 if (sc->sc_state == ESP_IDLE) 971 esp_sched(sc); 972 973 splx(s); 974 975 if ((flags & SCSI_POLL) == 0) 976 return SUCCESSFULLY_QUEUED; 977 978 /* Not allowed to use interrupts, use polling instead */ 979 if (esp_poll(sc, xs, ecb->timeout)) { 980 esp_timeout(ecb); 981 if (esp_poll(sc, xs, ecb->timeout)) 982 esp_timeout(ecb); 983 } 984 return COMPLETE; 985 } 986 987 /* 988 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 989 */ 990 int 991 esp_poll(sc, xs, count) 992 struct esp_softc *sc; 993 struct scsi_xfer *xs; 994 int count; 995 { 996 997 ESP_TRACE(("[esp_poll] ")); 998 while (count) { 999 if (DMA_ISINTR(sc->sc_dma)) { 1000 espintr(sc); 1001 } 1002 #if alternatively 1003 if (ESP_READ_REG(sc, ESP_STAT) & ESPSTAT_INT) 1004 espintr(sc); 1005 #endif 1006 if ((xs->flags & ITSDONE) != 0) 1007 return 0; 1008 if (sc->sc_state == ESP_IDLE) { 1009 ESP_TRACE(("[esp_poll: rescheduling] ")); 1010 esp_sched(sc); 1011 } 1012 DELAY(1000); 1013 count--; 1014 } 1015 return 1; 1016 } 1017 1018 1019 /* 1020 * LOW LEVEL SCSI UTILITIES 1021 */ 1022 1023 /* 1024 * Schedule a scsi operation. This has now been pulled out of the interrupt 1025 * handler so that we may call it from esp_scsi_cmd and esp_done. This may 1026 * save us an unecessary interrupt just to get things going. Should only be 1027 * called when state == ESP_IDLE and at bio pl. 1028 */ 1029 void 1030 esp_sched(sc) 1031 struct esp_softc *sc; 1032 { 1033 struct esp_ecb *ecb; 1034 struct scsi_link *sc_link; 1035 struct esp_tinfo *ti; 1036 1037 ESP_TRACE(("[esp_sched] ")); 1038 if (sc->sc_state != ESP_IDLE) 1039 panic("esp_sched: not IDLE (state=%d)", sc->sc_state); 1040 1041 /* 1042 * Find first ecb in ready queue that is for a target/lunit 1043 * combinations that is not busy. 1044 */ 1045 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 1046 sc_link = ecb->xs->sc_link; 1047 ti = &sc->sc_tinfo[sc_link->target]; 1048 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 1049 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1050 sc->sc_nexus = ecb; 1051 esp_select(sc, ecb); 1052 break; 1053 } else 1054 ESP_MISC(("%d:%d busy\n", 1055 sc_link->target, sc_link->lun)); 1056 } 1057 } 1058 1059 void 1060 esp_sense(sc, ecb) 1061 struct esp_softc *sc; 1062 struct esp_ecb *ecb; 1063 { 1064 struct scsi_xfer *xs = ecb->xs; 1065 struct scsi_link *sc_link = xs->sc_link; 1066 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1067 struct scsi_sense *ss = (void *)&ecb->cmd; 1068 1069 ESP_MISC(("requesting sense ")); 1070 /* Next, setup a request sense command block */ 1071 bzero(ss, sizeof(*ss)); 1072 ss->opcode = REQUEST_SENSE; 1073 ss->byte2 = sc_link->lun << 5; 1074 ss->length = sizeof(struct scsi_sense_data); 1075 ecb->clen = sizeof(*ss); 1076 ecb->daddr = (char *)&xs->sense; 1077 ecb->dleft = sizeof(struct scsi_sense_data); 1078 ecb->flags |= ECB_SENSE; 1079 ti->senses++; 1080 if (ecb->flags & ECB_NEXUS) 1081 ti->lubusy &= ~(1 << sc_link->lun); 1082 if (ecb == sc->sc_nexus) { 1083 esp_select(sc, ecb); 1084 } else { 1085 esp_dequeue(sc, ecb); 1086 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1087 if (sc->sc_state == ESP_IDLE) 1088 esp_sched(sc); 1089 } 1090 } 1091 1092 /* 1093 * POST PROCESSING OF SCSI_CMD (usually current) 1094 */ 1095 void 1096 esp_done(sc, ecb) 1097 struct esp_softc *sc; 1098 struct esp_ecb *ecb; 1099 { 1100 struct scsi_xfer *xs = ecb->xs; 1101 struct scsi_link *sc_link = xs->sc_link; 1102 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1103 1104 ESP_TRACE(("[esp_done(error:%x)] ", xs->error)); 1105 1106 /* 1107 * Now, if we've come here with no error code, i.e. we've kept the 1108 * initial XS_NOERROR, and the status code signals that we should 1109 * check sense, we'll need to set up a request sense cmd block and 1110 * push the command back into the ready queue *before* any other 1111 * commands for this target/lunit, else we lose the sense info. 1112 * We don't support chk sense conditions for the request sense cmd. 1113 */ 1114 if (xs->error == XS_NOERROR) { 1115 if ((ecb->flags & ECB_ABORT) != 0) { 1116 xs->error = XS_DRIVER_STUFFUP; 1117 } else if ((ecb->flags & ECB_SENSE) != 0) { 1118 xs->error = XS_SENSE; 1119 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 1120 /* First, save the return values */ 1121 xs->resid = ecb->dleft; 1122 xs->status = ecb->stat; 1123 esp_sense(sc, ecb); 1124 return; 1125 } else { 1126 xs->resid = ecb->dleft; 1127 } 1128 } 1129 1130 xs->flags |= ITSDONE; 1131 1132 #if ESP_DEBUG > 0 1133 if (esp_debug & ESP_SHOWMISC) { 1134 if (xs->resid != 0) 1135 printf("resid=%d ", xs->resid); 1136 if (xs->error == XS_SENSE) 1137 printf("sense=0x%02x\n", xs->sense.error_code); 1138 else 1139 printf("error=%d\n", xs->error); 1140 } 1141 #endif 1142 1143 /* 1144 * Remove the ECB from whatever queue it's on. 1145 */ 1146 if (ecb->flags & ECB_NEXUS) 1147 ti->lubusy &= ~(1 << sc_link->lun); 1148 if (ecb == sc->sc_nexus) { 1149 sc->sc_nexus = NULL; 1150 sc->sc_state = ESP_IDLE; 1151 esp_sched(sc); 1152 } else 1153 esp_dequeue(sc, ecb); 1154 1155 esp_free_ecb(sc, ecb, xs->flags); 1156 ti->cmds++; 1157 scsi_done(xs); 1158 } 1159 1160 void 1161 esp_dequeue(sc, ecb) 1162 struct esp_softc *sc; 1163 struct esp_ecb *ecb; 1164 { 1165 1166 if (ecb->flags & ECB_NEXUS) { 1167 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1168 } else { 1169 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1170 } 1171 } 1172 1173 /* 1174 * INTERRUPT/PROTOCOL ENGINE 1175 */ 1176 1177 /* 1178 * Schedule an outgoing message by prioritizing it, and asserting 1179 * attention on the bus. We can only do this when we are the initiator 1180 * else there will be an illegal command interrupt. 1181 */ 1182 #define esp_sched_msgout(m) \ 1183 do { \ 1184 ESP_MISC(("esp_sched_msgout %d ", m)); \ 1185 ESPCMD(sc, ESPCMD_SETATN); \ 1186 sc->sc_flags |= ESP_ATN; \ 1187 sc->sc_msgpriq |= (m); \ 1188 } while (0) 1189 1190 int 1191 esp_reselect(sc, message) 1192 struct esp_softc *sc; 1193 int message; 1194 { 1195 u_char selid, target, lun; 1196 struct esp_ecb *ecb; 1197 struct scsi_link *sc_link; 1198 struct esp_tinfo *ti; 1199 1200 /* 1201 * The SCSI chip made a snapshot of the data bus while the reselection 1202 * was being negotiated. This enables us to determine which target did 1203 * the reselect. 1204 */ 1205 selid = sc->sc_selid & ~(1 << sc->sc_id); 1206 if (selid & (selid - 1)) { 1207 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 1208 sc->sc_dev.dv_xname, selid); 1209 goto reset; 1210 } 1211 1212 /* 1213 * Search wait queue for disconnected cmd 1214 * The list should be short, so I haven't bothered with 1215 * any more sophisticated structures than a simple 1216 * singly linked list. 1217 */ 1218 target = ffs(selid) - 1; 1219 lun = message & 0x07; 1220 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 1221 ecb = ecb->chain.tqe_next) { 1222 sc_link = ecb->xs->sc_link; 1223 if (sc_link->target == target && sc_link->lun == lun) 1224 break; 1225 } 1226 if (ecb == NULL) { 1227 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 1228 sc->sc_dev.dv_xname, target, lun); 1229 goto abort; 1230 } 1231 1232 /* Make this nexus active again. */ 1233 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1234 sc->sc_state = ESP_CONNECTED; 1235 sc->sc_nexus = ecb; 1236 ti = &sc->sc_tinfo[target]; 1237 ti->lubusy |= (1 << lun); 1238 esp_setsync(sc, ti); 1239 1240 if (ecb->flags & ECB_RESET) 1241 esp_sched_msgout(SEND_DEV_RESET); 1242 else if (ecb->flags & ECB_ABORT) 1243 esp_sched_msgout(SEND_ABORT); 1244 1245 /* Do an implicit RESTORE POINTERS. */ 1246 sc->sc_dp = ecb->daddr; 1247 sc->sc_dleft = ecb->dleft; 1248 1249 return (0); 1250 1251 reset: 1252 esp_sched_msgout(SEND_DEV_RESET); 1253 return (1); 1254 1255 abort: 1256 esp_sched_msgout(SEND_ABORT); 1257 return (1); 1258 } 1259 1260 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 1261 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1262 #define ISEXTMSG(m) ((m) == 1) 1263 1264 /* 1265 * Get an incoming message as initiator. 1266 * 1267 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1268 * byte in the FIFO 1269 */ 1270 void 1271 esp_msgin(sc) 1272 register struct esp_softc *sc; 1273 { 1274 register int v; 1275 1276 ESP_TRACE(("[esp_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1277 1278 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) == 0) { 1279 printf("%s: msgin: no msg byte available\n", 1280 sc->sc_dev.dv_xname); 1281 return; 1282 } 1283 1284 /* 1285 * Prepare for a new message. A message should (according 1286 * to the SCSI standard) be transmitted in one single 1287 * MESSAGE_IN_PHASE. If we have been in some other phase, 1288 * then this is a new message. 1289 */ 1290 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1291 sc->sc_flags &= ~ESP_DROP_MSGI; 1292 sc->sc_imlen = 0; 1293 } 1294 1295 v = ESP_READ_REG(sc, ESP_FIFO); 1296 ESP_MISC(("<msgbyte:0x%02x>", v)); 1297 1298 #if 0 1299 if (sc->sc_state == ESP_RESELECTED && sc->sc_imlen == 0) { 1300 /* 1301 * Which target is reselecting us? (The ID bit really) 1302 */ 1303 sc->sc_selid = v; 1304 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1305 return; 1306 } 1307 #endif 1308 1309 sc->sc_imess[sc->sc_imlen] = v; 1310 1311 /* 1312 * If we're going to reject the message, don't bother storing 1313 * the incoming bytes. But still, we need to ACK them. 1314 */ 1315 1316 if ((sc->sc_flags & ESP_DROP_MSGI)) { 1317 ESPCMD(sc, ESPCMD_MSGOK); 1318 printf("<dropping msg byte %x>", 1319 sc->sc_imess[sc->sc_imlen]); 1320 return; 1321 } 1322 1323 if (sc->sc_imlen >= ESP_MAX_MSG_LEN) { 1324 esp_sched_msgout(SEND_REJECT); 1325 sc->sc_flags |= ESP_DROP_MSGI; 1326 } else { 1327 sc->sc_imlen++; 1328 /* 1329 * This testing is suboptimal, but most 1330 * messages will be of the one byte variety, so 1331 * it should not effect performance 1332 * significantly. 1333 */ 1334 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1335 goto gotit; 1336 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1337 goto gotit; 1338 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1339 sc->sc_imlen == sc->sc_imess[1] + 2) 1340 goto gotit; 1341 } 1342 /* Ack what we have so far */ 1343 ESPCMD(sc, ESPCMD_MSGOK); 1344 return; 1345 1346 gotit: 1347 ESP_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1348 /* 1349 * Now we should have a complete message (1 byte, 2 byte 1350 * and moderately long extended messages). We only handle 1351 * extended messages which total length is shorter than 1352 * ESP_MAX_MSG_LEN. Longer messages will be amputated. 1353 */ 1354 switch (sc->sc_state) { 1355 struct esp_ecb *ecb; 1356 struct esp_tinfo *ti; 1357 1358 case ESP_CONNECTED: 1359 ecb = sc->sc_nexus; 1360 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1361 1362 switch (sc->sc_imess[0]) { 1363 case MSG_CMDCOMPLETE: 1364 ESP_MSGS(("cmdcomplete ")); 1365 if (sc->sc_dleft < 0) { 1366 struct scsi_link *sc_link = ecb->xs->sc_link; 1367 printf("%s: %d extra bytes from %d:%d\n", 1368 sc->sc_dev.dv_xname, -sc->sc_dleft, 1369 sc_link->target, sc_link->lun); 1370 sc->sc_dleft = 0; 1371 } 1372 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 1373 sc->sc_state = ESP_CMDCOMPLETE; 1374 break; 1375 1376 case MSG_MESSAGE_REJECT: 1377 if (esp_debug & ESP_SHOWMSGS) 1378 printf("%s: our msg rejected by target\n", 1379 sc->sc_dev.dv_xname); 1380 switch (sc->sc_msgout) { 1381 case SEND_SDTR: 1382 sc->sc_flags &= ~ESP_SYNCHNEGO; 1383 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1384 esp_setsync(sc, ti); 1385 break; 1386 case SEND_INIT_DET_ERR: 1387 goto abort; 1388 } 1389 break; 1390 1391 case MSG_NOOP: 1392 ESP_MSGS(("noop ")); 1393 break; 1394 1395 case MSG_DISCONNECT: 1396 ESP_MSGS(("disconnect ")); 1397 ti->dconns++; 1398 sc->sc_state = ESP_DISCONNECT; 1399 if ((ecb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1400 break; 1401 /*FALLTHROUGH*/ 1402 1403 case MSG_SAVEDATAPOINTER: 1404 ESP_MSGS(("save datapointer ")); 1405 ecb->daddr = sc->sc_dp; 1406 ecb->dleft = sc->sc_dleft; 1407 break; 1408 1409 case MSG_RESTOREPOINTERS: 1410 ESP_MSGS(("restore datapointer ")); 1411 sc->sc_dp = ecb->daddr; 1412 sc->sc_dleft = ecb->dleft; 1413 break; 1414 1415 case MSG_EXTENDED: 1416 ESP_MSGS(("extended(%x) ", sc->sc_imess[2])); 1417 switch (sc->sc_imess[2]) { 1418 case MSG_EXT_SDTR: 1419 ESP_MSGS(("SDTR period %d, offset %d ", 1420 sc->sc_imess[3], sc->sc_imess[4])); 1421 if (sc->sc_imess[1] != 3) 1422 goto reject; 1423 ti->period = sc->sc_imess[3]; 1424 ti->offset = sc->sc_imess[4]; 1425 ti->flags &= ~T_NEGOTIATE; 1426 if (sc->sc_minsync == 0 || 1427 ti->offset == 0 || 1428 ti->period > 124) { 1429 printf("%s:%d: async\n", "esp", 1430 ecb->xs->sc_link->target); 1431 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1432 /* target initiated negotiation */ 1433 ti->offset = 0; 1434 ti->flags &= ~T_SYNCMODE; 1435 esp_sched_msgout(SEND_SDTR); 1436 } else { 1437 /* we are async */ 1438 ti->flags &= ~T_SYNCMODE; 1439 } 1440 } else { 1441 int r = 250/ti->period; 1442 int s = (100*250)/ti->period - 100*r; 1443 int p; 1444 1445 p = esp_stp2cpb(sc, ti->period); 1446 ti->period = esp_cpb2stp(sc, p); 1447 #ifdef ESP_DEBUG 1448 sc_print_addr(ecb->xs->sc_link); 1449 printf("max sync rate %d.%02dMb/s\n", 1450 r, s); 1451 #endif 1452 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1453 /* target initiated negotiation */ 1454 if (ti->period < sc->sc_minsync) 1455 ti->period = sc->sc_minsync; 1456 if (ti->offset > 15) 1457 ti->offset = 15; 1458 ti->flags &= ~T_SYNCMODE; 1459 esp_sched_msgout(SEND_SDTR); 1460 } else { 1461 /* we are sync */ 1462 ti->flags |= T_SYNCMODE; 1463 } 1464 } 1465 sc->sc_flags &= ~ESP_SYNCHNEGO; 1466 esp_setsync(sc, ti); 1467 break; 1468 1469 default: 1470 printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n", 1471 sc->sc_dev.dv_xname); 1472 goto reject; 1473 } 1474 break; 1475 1476 default: 1477 ESP_MSGS(("ident ")); 1478 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1479 sc->sc_dev.dv_xname); 1480 reject: 1481 esp_sched_msgout(SEND_REJECT); 1482 break; 1483 } 1484 break; 1485 1486 case ESP_RESELECTED: 1487 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1488 printf("%s: reselect without IDENTIFY; sending DEVICE RESET\n", 1489 sc->sc_dev.dv_xname); 1490 goto reset; 1491 } 1492 1493 (void) esp_reselect(sc, sc->sc_imess[0]); 1494 break; 1495 1496 default: 1497 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1498 sc->sc_dev.dv_xname); 1499 reset: 1500 esp_sched_msgout(SEND_DEV_RESET); 1501 break; 1502 1503 abort: 1504 esp_sched_msgout(SEND_ABORT); 1505 break; 1506 } 1507 1508 /* Ack last message byte */ 1509 ESPCMD(sc, ESPCMD_MSGOK); 1510 1511 /* Done, reset message pointer. */ 1512 sc->sc_flags &= ~ESP_DROP_MSGI; 1513 sc->sc_imlen = 0; 1514 } 1515 1516 1517 /* 1518 * Send the highest priority, scheduled message 1519 */ 1520 void 1521 esp_msgout(sc) 1522 register struct esp_softc *sc; 1523 { 1524 struct esp_tinfo *ti; 1525 struct esp_ecb *ecb; 1526 size_t size; 1527 1528 ESP_TRACE(("[esp_msgout(priq:%x, prevphase:%x)]", sc->sc_msgpriq, sc->sc_prevphase)); 1529 1530 if (sc->sc_flags & ESP_ATN) { 1531 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1532 new: 1533 ESPCMD(sc, ESPCMD_FLUSH); 1534 DELAY(1); 1535 sc->sc_msgoutq = 0; 1536 sc->sc_omlen = 0; 1537 } 1538 } else { 1539 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1540 esp_sched_msgout(sc->sc_msgoutq); 1541 goto new; 1542 } else { 1543 printf("esp at line %d: unexpected MESSAGE OUT phase\n", __LINE__); 1544 } 1545 } 1546 1547 if (sc->sc_omlen == 0) { 1548 /* Pick up highest priority message */ 1549 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1550 sc->sc_msgoutq |= sc->sc_msgout; 1551 sc->sc_msgpriq &= ~sc->sc_msgout; 1552 sc->sc_omlen = 1; /* "Default" message len */ 1553 switch (sc->sc_msgout) { 1554 case SEND_SDTR: 1555 ecb = sc->sc_nexus; 1556 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1557 sc->sc_omess[0] = MSG_EXTENDED; 1558 sc->sc_omess[1] = 3; 1559 sc->sc_omess[2] = MSG_EXT_SDTR; 1560 sc->sc_omess[3] = ti->period; 1561 sc->sc_omess[4] = ti->offset; 1562 sc->sc_omlen = 5; 1563 if ((sc->sc_flags & ESP_SYNCHNEGO) == 0) { 1564 ti->flags |= T_SYNCMODE; 1565 esp_setsync(sc, ti); 1566 } 1567 break; 1568 case SEND_IDENTIFY: 1569 if (sc->sc_state != ESP_CONNECTED) { 1570 printf("esp at line %d: no nexus\n", __LINE__); 1571 } 1572 ecb = sc->sc_nexus; 1573 sc->sc_omess[0] = MSG_IDENTIFY(ecb->xs->sc_link->lun,0); 1574 break; 1575 case SEND_DEV_RESET: 1576 sc->sc_flags |= ESP_ABORTING; 1577 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1578 ecb = sc->sc_nexus; 1579 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1580 ti->flags &= ~T_SYNCMODE; 1581 ti->flags |= T_NEGOTIATE; 1582 break; 1583 case SEND_PARITY_ERROR: 1584 sc->sc_omess[0] = MSG_PARITY_ERROR; 1585 break; 1586 case SEND_ABORT: 1587 sc->sc_flags |= ESP_ABORTING; 1588 sc->sc_omess[0] = MSG_ABORT; 1589 break; 1590 case SEND_INIT_DET_ERR: 1591 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1592 break; 1593 case SEND_REJECT: 1594 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1595 break; 1596 default: 1597 ESPCMD(sc, ESPCMD_RSTATN); 1598 sc->sc_flags &= ~ESP_ATN; 1599 sc->sc_omess[0] = MSG_NOOP; 1600 break; 1601 } 1602 sc->sc_omp = sc->sc_omess; 1603 } 1604 1605 #if 1 1606 /* (re)send the message */ 1607 size = min(sc->sc_omlen, sc->sc_maxxfer); 1608 DMA_SETUP(sc->sc_dma, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1609 #ifndef MAC68K_DRIVER 1610 /* Program the SCSI counter */ 1611 ESP_WRITE_REG(sc, ESP_TCL, size); 1612 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 1613 if (sc->sc_cfg2 & ESPCFG2_FE) { 1614 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 1615 } 1616 /* load the count in */ 1617 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 1618 #endif 1619 ESPCMD(sc, ESPCMD_TRANS|ESPCMD_DMA); 1620 DMA_GO(sc->sc_dma); 1621 #else 1622 { int i; 1623 for (i = 0; i < sc->sc_omlen; i++) 1624 ESP_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1625 ESPCMD(sc, ESPCMD_TRANS); 1626 sc->sc_omlen = 0; 1627 } 1628 #endif 1629 } 1630 1631 /* 1632 * This is the most critical part of the driver, and has to know 1633 * how to deal with *all* error conditions and phases from the SCSI 1634 * bus. If there are no errors and the DMA was active, then call the 1635 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1636 * and we can return from here without further processing. 1637 * 1638 * Most of this needs verifying. 1639 */ 1640 int 1641 espintr(sc) 1642 register struct esp_softc *sc; 1643 { 1644 register struct esp_ecb *ecb; 1645 register struct scsi_link *sc_link; 1646 struct esp_tinfo *ti; 1647 int loop; 1648 size_t size; 1649 1650 ESP_TRACE(("[espintr]")); 1651 1652 /* 1653 * I have made some (maybe seriously flawed) assumptions here, 1654 * but basic testing (uncomment the printf() below), show that 1655 * certainly something happens when this loop is here. 1656 * 1657 * The idea is that many of the SCSI operations take very little 1658 * time, and going away and getting interrupted is too high an 1659 * overhead to pay. For example, selecting, sending a message 1660 * and command and then doing some work can be done in one "pass". 1661 * 1662 * The DELAY is not variable because I do not understand that the 1663 * DELAY loop should be fixed-time regardless of CPU speed, but 1664 * I am *assuming* that the faster SCSI processors get things done 1665 * quicker (sending a command byte etc), and so there is no 1666 * need to be too slow. 1667 * 1668 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1669 * at 40Mhz. This needs testing. 1670 */ 1671 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1672 /* a feeling of deja-vu */ 1673 if (!DMA_ISINTR(sc->sc_dma)) 1674 return (loop != 0); 1675 #if 0 1676 if (loop) 1677 printf("*"); 1678 #endif 1679 1680 /* and what do the registers say... */ 1681 espreadregs(sc); 1682 1683 errintr: 1684 sc->sc_intrcnt.ev_count++; 1685 1686 /* 1687 * At the moment, only a SCSI Bus Reset or Illegal 1688 * Command are classed as errors. A disconnect is a 1689 * valid condition, and we let the code check is the 1690 * "ESP_BUSFREE_OK" flag was set before declaring it 1691 * and error. 1692 * 1693 * Also, the status register tells us about "Gross 1694 * Errors" and "Parity errors". Only the Gross Error 1695 * is really bad, and the parity errors are dealt 1696 * with later 1697 * 1698 * TODO 1699 * If there are too many parity error, go to slow 1700 * cable mode ? 1701 */ 1702 1703 /* SCSI Reset */ 1704 if (sc->sc_espintr & ESPINTR_SBR) { 1705 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1706 ESPCMD(sc, ESPCMD_FLUSH); 1707 DELAY(1); 1708 } 1709 if (sc->sc_state != ESP_SBR) { 1710 printf("%s: SCSI bus reset\n", 1711 sc->sc_dev.dv_xname); 1712 esp_init(sc, 0); /* Restart everything */ 1713 return 1; 1714 } 1715 #if 0 1716 /*XXX*/ printf("<expected bus reset: " 1717 "[intr %x, stat %x, step %d]>\n", 1718 sc->sc_espintr, sc->sc_espstat, 1719 sc->sc_espstep); 1720 #endif 1721 if (sc->sc_nexus) 1722 panic("%s: nexus in reset state", 1723 sc->sc_dev.dv_xname); 1724 goto sched; 1725 } 1726 1727 ecb = sc->sc_nexus; 1728 1729 #define ESPINTR_ERR (ESPINTR_SBR|ESPINTR_ILL) 1730 if (sc->sc_espintr & ESPINTR_ERR || 1731 sc->sc_espstat & ESPSTAT_GE) { 1732 1733 if (sc->sc_espstat & ESPSTAT_GE) { 1734 /* no target ? */ 1735 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1736 ESPCMD(sc, ESPCMD_FLUSH); 1737 DELAY(1); 1738 } 1739 if (sc->sc_state == ESP_CONNECTED || 1740 sc->sc_state == ESP_SELECTING) { 1741 ecb->xs->error = XS_DRIVER_STUFFUP; 1742 esp_done(sc, ecb); 1743 } 1744 return 1; 1745 } 1746 1747 if (sc->sc_espintr & ESPINTR_ILL) { 1748 /* illegal command, out of sync ? */ 1749 printf("%s: illegal command: 0x%x (state %d, phase %x, prevphase %x)\n", 1750 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1751 sc->sc_state, sc->sc_phase, 1752 sc->sc_prevphase); 1753 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1754 ESPCMD(sc, ESPCMD_FLUSH); 1755 DELAY(1); 1756 } 1757 esp_init(sc, 0); /* Restart everything */ 1758 return 1; 1759 } 1760 } 1761 1762 /* 1763 * Call if DMA is active. 1764 * 1765 * If DMA_INTR returns true, then maybe go 'round the loop 1766 * again in case there is no more DMA queued, but a phase 1767 * change is expected. 1768 */ 1769 if (DMA_ISACTIVE(sc->sc_dma)) { 1770 DMA_INTR(sc->sc_dma); 1771 /* If DMA active here, then go back to work... */ 1772 if ( (sc->sc_espstat & ESPSTAT_GE) 1773 || (sc->sc_espintr & ESPINTR_ERR)) 1774 goto errintr; 1775 if (DMA_ISACTIVE(sc->sc_dma)) 1776 return 1; 1777 1778 if (sc->sc_dleft == 0 && 1779 (sc->sc_espstat & ESPSTAT_TC) == 0) 1780 printf("%s: !TC [intr %x, stat %x, step %d]" 1781 " prevphase %x, resid %x\n", 1782 sc->sc_dev.dv_xname, 1783 sc->sc_espintr, 1784 sc->sc_espstat, 1785 sc->sc_espstep, 1786 sc->sc_prevphase, 1787 ecb?ecb->dleft:-1); 1788 } 1789 1790 #if 0 /* Unreliable on some ESP revisions? */ 1791 if ((sc->sc_espstat & ESPSTAT_INT) == 0) { 1792 printf("%s: spurious interrupt\n", sc->sc_dev.dv_xname); 1793 return 1; 1794 } 1795 #endif 1796 1797 /* 1798 * check for less serious errors 1799 */ 1800 if (sc->sc_espstat & ESPSTAT_PE) { 1801 printf("%s: SCSI bus parity error\n", 1802 sc->sc_dev.dv_xname); 1803 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1804 esp_sched_msgout(SEND_PARITY_ERROR); 1805 else 1806 esp_sched_msgout(SEND_INIT_DET_ERR); 1807 } 1808 1809 if (sc->sc_espintr & ESPINTR_DIS) { 1810 ESP_MISC(("<DISC [intr %x, stat %x, step %d]>", 1811 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1812 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1813 ESPCMD(sc, ESPCMD_FLUSH); 1814 DELAY(1); 1815 } 1816 /* 1817 * This command must (apparently) be issued within 1818 * 250mS of a disconnect. So here you are... 1819 */ 1820 ESPCMD(sc, ESPCMD_ENSEL); 1821 switch (sc->sc_state) { 1822 case ESP_RESELECTED: 1823 goto sched; 1824 1825 case ESP_SELECTING: 1826 ecb->xs->error = XS_SELTIMEOUT; 1827 goto finish; 1828 1829 case ESP_CONNECTED: 1830 if ((sc->sc_flags & ESP_SYNCHNEGO)) { 1831 #ifdef ESP_DEBUG 1832 if (ecb) 1833 sc_print_addr(ecb->xs->sc_link); 1834 printf("sync nego not completed!\n"); 1835 #endif 1836 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1837 sc->sc_flags &= ~ESP_SYNCHNEGO; 1838 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1839 } 1840 1841 /* it may be OK to disconnect */ 1842 if ((sc->sc_flags & ESP_ABORTING) == 0) { 1843 /* 1844 * Section 5.1.1 of the SCSI 2 spec 1845 * suggests issuing a REQUEST SENSE 1846 * following an unexpected disconnect. 1847 * Some devices go into a contingent 1848 * allegiance condition when 1849 * disconnecting, and this is necessary 1850 * to clean up their state. 1851 */ 1852 printf("%s: unexpected disconnect; ", 1853 sc->sc_dev.dv_xname); 1854 if (ecb->flags & ECB_SENSE) { 1855 printf("resetting\n"); 1856 goto reset; 1857 } 1858 printf("sending REQUEST SENSE\n"); 1859 esp_sense(sc, ecb); 1860 goto out; 1861 } 1862 1863 ecb->xs->error = XS_DRIVER_STUFFUP; 1864 goto finish; 1865 1866 case ESP_DISCONNECT: 1867 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1868 sc->sc_nexus = NULL; 1869 goto sched; 1870 1871 case ESP_CMDCOMPLETE: 1872 goto finish; 1873 } 1874 } 1875 1876 switch (sc->sc_state) { 1877 1878 case ESP_SBR: 1879 printf("%s: waiting for SCSI Bus Reset to happen\n", 1880 sc->sc_dev.dv_xname); 1881 return 1; 1882 1883 case ESP_RESELECTED: 1884 /* 1885 * we must be continuing a message ? 1886 */ 1887 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1888 printf("%s: target didn't identify\n", 1889 sc->sc_dev.dv_xname); 1890 esp_init(sc, 1); 1891 return 1; 1892 } 1893 printf("<<RESELECT CONT'd>>"); 1894 #if XXXX 1895 esp_msgin(sc); 1896 if (sc->sc_state != ESP_CONNECTED) { 1897 /* IDENTIFY fail?! */ 1898 printf("%s: identify failed\n", 1899 sc->sc_dev.dv_xname); 1900 esp_init(sc, 1); 1901 return 1; 1902 } 1903 #endif 1904 break; 1905 1906 case ESP_IDLE: 1907 if (sc->sc_flags & ESP_ICCS) printf("[[esp: BUMMER]]"); 1908 case ESP_SELECTING: 1909 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1910 sc->sc_flags = 0; 1911 1912 if (sc->sc_espintr & ESPINTR_RESEL) { 1913 /* 1914 * If we're trying to select a 1915 * target ourselves, push our command 1916 * back into the ready list. 1917 */ 1918 if (sc->sc_state == ESP_SELECTING) { 1919 ESP_MISC(("backoff selector ")); 1920 sc_link = sc->sc_nexus->xs->sc_link; 1921 ti = &sc->sc_tinfo[sc_link->target]; 1922 TAILQ_INSERT_HEAD(&sc->ready_list, 1923 sc->sc_nexus, chain); 1924 ecb = sc->sc_nexus = NULL; 1925 } 1926 sc->sc_state = ESP_RESELECTED; 1927 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1928 /* 1929 * Things are seriously fucked up. 1930 * Pull the brakes, i.e. reset 1931 */ 1932 printf("%s: target didn't identify\n", 1933 sc->sc_dev.dv_xname); 1934 esp_init(sc, 1); 1935 return 1; 1936 } 1937 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 1938 printf("%s: RESELECT: %d bytes in FIFO!\n", 1939 sc->sc_dev.dv_xname, 1940 ESP_READ_REG(sc, ESP_FFLAG) & 1941 ESPFIFO_FF); 1942 esp_init(sc, 1); 1943 return 1; 1944 } 1945 sc->sc_selid = ESP_READ_REG(sc, ESP_FIFO); 1946 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1947 esp_msgin(sc); /* Handle identify message */ 1948 if (sc->sc_state != ESP_CONNECTED) { 1949 /* IDENTIFY fail?! */ 1950 printf("%s: identify failed\n", 1951 sc->sc_dev.dv_xname); 1952 esp_init(sc, 1); 1953 return 1; 1954 } 1955 continue; /* ie. next phase expected soon */ 1956 } 1957 1958 #define ESPINTR_DONE (ESPINTR_FC|ESPINTR_BS) 1959 if ((sc->sc_espintr & ESPINTR_DONE) == ESPINTR_DONE) { 1960 ecb = sc->sc_nexus; 1961 if (!ecb) 1962 panic("esp: not nexus at sc->sc_nexus"); 1963 1964 sc_link = ecb->xs->sc_link; 1965 ti = &sc->sc_tinfo[sc_link->target]; 1966 1967 switch (sc->sc_espstep) { 1968 case 0: 1969 printf("%s: select timeout/no disconnect\n", 1970 sc->sc_dev.dv_xname); 1971 ecb->xs->error = XS_SELTIMEOUT; 1972 goto finish; 1973 case 1: 1974 if ((ti->flags & T_NEGOTIATE) == 0) { 1975 printf("%s: step 1 & !NEG\n", 1976 sc->sc_dev.dv_xname); 1977 goto reset; 1978 } 1979 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1980 printf("%s: !MSGOUT\n", 1981 sc->sc_dev.dv_xname); 1982 goto reset; 1983 } 1984 /* Start negotiating */ 1985 ti->period = sc->sc_minsync; 1986 ti->offset = 15; 1987 sc->sc_flags |= ESP_SYNCHNEGO; 1988 esp_sched_msgout(SEND_SDTR); 1989 break; 1990 case 3: 1991 /* 1992 * Grr, this is supposed to mean 1993 * "target left command phase 1994 * prematurely". It seems to happen 1995 * regularly when sync mode is on. 1996 * Look at FIFO to see if command 1997 * went out. 1998 * (Timing problems?) 1999 */ 2000 if ((ESP_READ_REG(sc, ESP_FFLAG)&ESPFIFO_FF) == 0) { 2001 /* Hope for the best.. */ 2002 break; 2003 } 2004 printf("(%s:%d:%d): selection failed;" 2005 " %d left in FIFO " 2006 "[intr %x, stat %x, step %d]\n", 2007 sc->sc_dev.dv_xname, 2008 sc_link->target, 2009 sc_link->lun, 2010 ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF, 2011 sc->sc_espintr, sc->sc_espstat, 2012 sc->sc_espstep); 2013 ESPCMD(sc, ESPCMD_FLUSH); 2014 esp_sched_msgout(SEND_ABORT); 2015 return 1; 2016 case 2: 2017 /* Select stuck at Command Phase */ 2018 ESPCMD(sc, ESPCMD_FLUSH); 2019 case 4: 2020 /* So far, everything went fine */ 2021 break; 2022 } 2023 #if 0 2024 if (ecb->xs->flags & SCSI_RESET) 2025 esp_sched_msgout(SEND_DEV_RESET); 2026 else if (ti->flags & T_NEGOTIATE) 2027 esp_sched_msgout( 2028 SEND_IDENTIFY | SEND_SDTR); 2029 else 2030 esp_sched_msgout(SEND_IDENTIFY); 2031 #endif 2032 2033 ecb->flags |= ECB_NEXUS; 2034 ti->lubusy |= (1 << sc_link->lun); 2035 2036 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 2037 /* Do an implicit RESTORE POINTERS. */ 2038 sc->sc_dp = ecb->daddr; 2039 sc->sc_dleft = ecb->dleft; 2040 2041 /* On our first connection, schedule a timeout. */ 2042 if ((ecb->xs->flags & SCSI_POLL) == 0) 2043 timeout(esp_timeout, ecb, (ecb->timeout * hz) / 1000); 2044 2045 sc->sc_state = ESP_CONNECTED; 2046 break; 2047 } else { 2048 printf("%s: unexpected status after select" 2049 ": [intr %x, stat %x, step %x]\n", 2050 sc->sc_dev.dv_xname, 2051 sc->sc_espintr, sc->sc_espstat, 2052 sc->sc_espstep); 2053 ESPCMD(sc, ESPCMD_FLUSH); 2054 DELAY(1); 2055 goto reset; 2056 } 2057 if (sc->sc_state == ESP_IDLE) { 2058 printf("%s: stray interrupt\n", sc->sc_dev.dv_xname); 2059 return 0; 2060 } 2061 break; 2062 2063 case ESP_CONNECTED: 2064 if (sc->sc_flags & ESP_ICCS) { 2065 u_char msg; 2066 2067 sc->sc_flags &= ~ESP_ICCS; 2068 2069 if (!(sc->sc_espintr & ESPINTR_DONE)) { 2070 printf("%s: ICCS: " 2071 ": [intr %x, stat %x, step %x]\n", 2072 sc->sc_dev.dv_xname, 2073 sc->sc_espintr, sc->sc_espstat, 2074 sc->sc_espstep); 2075 } 2076 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 2077 int i = (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) - 2; 2078 while (i--) 2079 (void) ESP_READ_REG(sc, ESP_FIFO); 2080 } 2081 ecb->stat = ESP_READ_REG(sc, ESP_FIFO); 2082 msg = ESP_READ_REG(sc, ESP_FIFO); 2083 ESP_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 2084 if (msg == MSG_CMDCOMPLETE) { 2085 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 2086 sc->sc_state = ESP_CMDCOMPLETE; 2087 } else 2088 printf("%s: STATUS_PHASE: msg %d\n", 2089 sc->sc_dev.dv_xname, msg); 2090 ESPCMD(sc, ESPCMD_MSGOK); 2091 continue; /* ie. wait for disconnect */ 2092 } 2093 break; 2094 default: 2095 panic("%s: invalid state: %d", 2096 sc->sc_dev.dv_xname, 2097 sc->sc_state); 2098 } 2099 2100 /* 2101 * Driver is now in state ESP_CONNECTED, i.e. we 2102 * have a current command working the SCSI bus. 2103 */ 2104 if (sc->sc_state != ESP_CONNECTED || ecb == NULL) { 2105 panic("esp no nexus"); 2106 } 2107 2108 switch (sc->sc_phase) { 2109 case MESSAGE_OUT_PHASE: 2110 ESP_PHASE(("MESSAGE_OUT_PHASE ")); 2111 esp_msgout(sc); 2112 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2113 break; 2114 case MESSAGE_IN_PHASE: 2115 ESP_PHASE(("MESSAGE_IN_PHASE ")); 2116 if (sc->sc_espintr & ESPINTR_BS) { 2117 ESPCMD(sc, ESPCMD_FLUSH); 2118 sc->sc_flags |= ESP_WAITI; 2119 ESPCMD(sc, ESPCMD_TRANS); 2120 } else if (sc->sc_espintr & ESPINTR_FC) { 2121 if ((sc->sc_flags & ESP_WAITI) == 0) { 2122 printf("%s: MSGIN: unexpected FC bit: " 2123 "[intr %x, stat %x, step %x]\n", 2124 sc->sc_dev.dv_xname, 2125 sc->sc_espintr, sc->sc_espstat, 2126 sc->sc_espstep); 2127 } 2128 sc->sc_flags &= ~ESP_WAITI; 2129 esp_msgin(sc); 2130 } else { 2131 printf("%s: MSGIN: weird bits: " 2132 "[intr %x, stat %x, step %x]\n", 2133 sc->sc_dev.dv_xname, 2134 sc->sc_espintr, sc->sc_espstat, 2135 sc->sc_espstep); 2136 } 2137 sc->sc_prevphase = MESSAGE_IN_PHASE; 2138 break; 2139 case COMMAND_PHASE: { 2140 /* well, this means send the command again */ 2141 u_char *cmd = (u_char *)&ecb->cmd; 2142 int i; 2143 2144 ESP_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2145 ecb->cmd.opcode, ecb->clen)); 2146 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 2147 ESPCMD(sc, ESPCMD_FLUSH); 2148 DELAY(1); 2149 } 2150 /* Now the command into the FIFO */ 2151 for (i = 0; i < ecb->clen; i++) 2152 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 2153 ESPCMD(sc, ESPCMD_TRANS); 2154 sc->sc_prevphase = COMMAND_PHASE; 2155 } 2156 break; 2157 case DATA_OUT_PHASE: 2158 ESP_PHASE(("DATA_OUT_PHASE [%d] ", sc->sc_dleft)); 2159 ESPCMD(sc, ESPCMD_FLUSH); 2160 size = min(sc->sc_dleft, sc->sc_maxxfer); 2161 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2162 0, &size); 2163 sc->sc_prevphase = DATA_OUT_PHASE; 2164 goto setup_xfer; 2165 case DATA_IN_PHASE: 2166 ESP_PHASE(("DATA_IN_PHASE ")); 2167 if (sc->sc_rev == ESP100) 2168 ESPCMD(sc, ESPCMD_FLUSH); 2169 size = min(sc->sc_dleft, sc->sc_maxxfer); 2170 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 2171 1, &size); 2172 sc->sc_prevphase = DATA_IN_PHASE; 2173 setup_xfer: 2174 #ifdef MAC68K_DRIVER 2175 if (!size) { 2176 #endif 2177 /* Program the SCSI counter */ 2178 ESP_WRITE_REG(sc, ESP_TCL, size); 2179 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 2180 if (sc->sc_cfg2 & ESPCFG2_FE) { 2181 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 2182 } 2183 /* load the count in */ 2184 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 2185 #ifdef MAC68K_DRIVER 2186 } 2187 #endif 2188 2189 /* 2190 * Note that if `size' is 0, we've already transceived 2191 * all the bytes we want but we're still in DATA PHASE. 2192 * Apparently, the device needs padding. Also, a 2193 * transfer size of 0 means "maximum" to the chip 2194 * DMA logic. 2195 */ 2196 ESPCMD(sc, 2197 (size==0?ESPCMD_TRPAD:ESPCMD_TRANS)|ESPCMD_DMA); 2198 DMA_GO(sc->sc_dma); 2199 return 1; 2200 case STATUS_PHASE: 2201 ESP_PHASE(("STATUS_PHASE ")); 2202 sc->sc_flags |= ESP_ICCS; 2203 ESPCMD(sc, ESPCMD_ICCS); 2204 sc->sc_prevphase = STATUS_PHASE; 2205 break; 2206 case INVALID_PHASE: 2207 break; 2208 default: 2209 printf("%s: unexpected bus phase; resetting\n", 2210 sc->sc_dev.dv_xname); 2211 goto reset; 2212 } 2213 } 2214 panic("esp: should not get here.."); 2215 2216 reset: 2217 esp_init(sc, 1); 2218 return 1; 2219 2220 finish: 2221 untimeout(esp_timeout, ecb); 2222 esp_done(sc, ecb); 2223 goto out; 2224 2225 sched: 2226 sc->sc_state = ESP_IDLE; 2227 esp_sched(sc); 2228 goto out; 2229 2230 out: 2231 return 1; 2232 } 2233 2234 void 2235 esp_abort(sc, ecb) 2236 struct esp_softc *sc; 2237 struct esp_ecb *ecb; 2238 { 2239 2240 /* 2 secs for the abort */ 2241 ecb->timeout = ESP_ABORT_TIMEOUT; 2242 ecb->flags |= ECB_ABORT; 2243 2244 if (ecb == sc->sc_nexus) { 2245 /* 2246 * If we're still selecting, the message will be scheduled 2247 * after selection is complete. 2248 */ 2249 if (sc->sc_state == ESP_CONNECTED) 2250 esp_sched_msgout(SEND_ABORT); 2251 } else { 2252 esp_dequeue(sc, ecb); 2253 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2254 if (sc->sc_state == ESP_IDLE) 2255 esp_sched(sc); 2256 } 2257 } 2258 2259 void 2260 esp_timeout(arg) 2261 void *arg; 2262 { 2263 struct esp_ecb *ecb = arg; 2264 struct scsi_xfer *xs = ecb->xs; 2265 struct scsi_link *sc_link = xs->sc_link; 2266 struct esp_softc *sc = sc_link->adapter_softc; 2267 int s; 2268 2269 sc_print_addr(sc_link); 2270 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2271 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) %s>", 2272 sc->sc_dev.dv_xname, 2273 ecb, ecb->flags, ecb->dleft, ecb->stat, 2274 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2275 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2276 DMA_ISACTIVE(sc->sc_dma) ? "DMA active" : ""); 2277 #if ESP_DEBUG > 0 2278 printf("TRACE: %s.", ecb->trace); 2279 #endif 2280 2281 s = splbio(); 2282 2283 if (ecb->flags & ECB_ABORT) { 2284 /* abort timed out */ 2285 printf(" AGAIN\n"); 2286 esp_init(sc, 1); 2287 } else { 2288 /* abort the operation that has timed out */ 2289 printf("\n"); 2290 xs->error = XS_TIMEOUT; 2291 esp_abort(sc, ecb); 2292 } 2293 2294 splx(s); 2295 } 2296
Indexes created Tue Oct 21 19:09:51 GMT 2025