espvar.h revision 1.1
1 /* $NetBSD: espvar.h,v 1.1 1996/10/29 06:09:00 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Peter Galbavy. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <machine/param.h> 33 34 #if defined(__sparc__) && !defined(SPARC_DRIVER) 35 #define SPARC_DRIVER 36 #else 37 #if (_MACHINE == mac68k) && !defined(MAC68K_DRIVER) 38 #define MAC68K_DRIVER 39 #endif 40 #endif 41 42 #define ESP_DEBUG 0 43 44 #define ESP_ABORT_TIMEOUT 2000 /* time to wait for abort */ 45 46 #define FREQTOCCF(freq) (((freq + 4) / 5)) 47 48 /* esp revisions */ 49 #define ESP100 0x01 50 #define ESP100A 0x02 51 #define ESP200 0x03 52 #define NCR53C94 0x04 53 #define NCR53C96 0x05 54 55 /* 56 * ECB. Holds additional information for each SCSI command Comments: We 57 * need a separate scsi command block because we may need to overwrite it 58 * with a request sense command. Basicly, we refrain from fiddling with 59 * the scsi_xfer struct (except do the expected updating of return values). 60 * We'll generally update: xs->{flags,resid,error,sense,status} and 61 * occasionally xs->retries. 62 */ 63 struct esp_ecb { 64 TAILQ_ENTRY(esp_ecb) chain; 65 struct scsi_xfer *xs; /* SCSI xfer ctrl block from above */ 66 int flags; 67 #define ECB_ALLOC 0x01 68 #define ECB_NEXUS 0x02 69 #define ECB_SENSE 0x04 70 #define ECB_ABORT 0x40 71 #define ECB_RESET 0x80 72 int timeout; 73 74 struct scsi_generic cmd; /* SCSI command block */ 75 int clen; 76 char *daddr; /* Saved data pointer */ 77 int dleft; /* Residue */ 78 u_char stat; /* SCSI status byte */ 79 80 #if ESP_DEBUG > 0 81 char trace[1000]; 82 #endif 83 }; 84 #if ESP_DEBUG > 0 85 #define ECB_TRACE(ecb, msg, a, b) do { \ 86 const char *f = "[" msg "]"; \ 87 int n = strlen((ecb)->trace); \ 88 if (n < (sizeof((ecb)->trace)-100)) \ 89 sprintf((ecb)->trace + n, f, a, b); \ 90 } while(0) 91 #else 92 #define ECB_TRACE(ecb, msg, a, b) 93 #endif 94 95 /* 96 * Some info about each (possible) target on the SCSI bus. This should 97 * probably have been a "per target+lunit" structure, but we'll leave it at 98 * this for now. Is there a way to reliably hook it up to sc->fordriver?? 99 */ 100 struct esp_tinfo { 101 int cmds; /* #commands processed */ 102 int dconns; /* #disconnects */ 103 int touts; /* #timeouts */ 104 int perrs; /* #parity errors */ 105 int senses; /* #request sense commands sent */ 106 ushort lubusy; /* What local units/subr. are busy? */ 107 u_char flags; 108 #define T_NEED_TO_RESET 0x01 /* Should send a BUS_DEV_RESET */ 109 #define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */ 110 #define T_BUSY 0x04 /* Target is busy, i.e. cmd in progress */ 111 #define T_SYNCMODE 0x08 /* sync mode has been negotiated */ 112 #define T_SYNCHOFF 0x10 /* .. */ 113 #define T_RSELECTOFF 0x20 /* .. */ 114 u_char period; /* Period suggestion */ 115 u_char offset; /* Offset suggestion */ 116 } tinfo_t; 117 118 /* Register a linenumber (for debugging) */ 119 #define LOGLINE(p) 120 121 #define ESP_SHOWECBS 0x01 122 #define ESP_SHOWINTS 0x02 123 #define ESP_SHOWCMDS 0x04 124 #define ESP_SHOWMISC 0x08 125 #define ESP_SHOWTRAC 0x10 126 #define ESP_SHOWSTART 0x20 127 #define ESP_SHOWPHASE 0x40 128 #define ESP_SHOWDMA 0x80 129 #define ESP_SHOWCCMDS 0x100 130 #define ESP_SHOWMSGS 0x200 131 132 #ifdef ESP_DEBUG 133 extern int esp_debug; 134 #define ESP_ECBS(str) do {if (esp_debug & ESP_SHOWECBS) printf str;} while (0) 135 #define ESP_MISC(str) do {if (esp_debug & ESP_SHOWMISC) printf str;} while (0) 136 #define ESP_INTS(str) do {if (esp_debug & ESP_SHOWINTS) printf str;} while (0) 137 #define ESP_TRACE(str) do {if (esp_debug & ESP_SHOWTRAC) printf str;} while (0) 138 #define ESP_CMDS(str) do {if (esp_debug & ESP_SHOWCMDS) printf str;} while (0) 139 #define ESP_START(str) do {if (esp_debug & ESP_SHOWSTART) printf str;}while (0) 140 #define ESP_PHASE(str) do {if (esp_debug & ESP_SHOWPHASE) printf str;}while (0) 141 #define ESP_DMA(str) do {if (esp_debug & ESP_SHOWDMA) printf str;}while (0) 142 #define ESP_MSGS(str) do {if (esp_debug & ESP_SHOWMSGS) printf str;}while (0) 143 #else 144 #define ESP_ECBS(str) 145 #define ESP_MISC(str) 146 #define ESP_INTS(str) 147 #define ESP_TRACE(str) 148 #define ESP_CMDS(str) 149 #define ESP_START(str) 150 #define ESP_PHASE(str) 151 #define ESP_DMA(str) 152 #define ESP_MSGS(str) 153 #endif 154 155 #define ESP_MAX_MSG_LEN 8 156 157 struct esp_softc { 158 struct device sc_dev; /* us as a device */ 159 #ifdef SPARC_DRIVER 160 struct sbusdev sc_sd; /* sbus device */ 161 struct intrhand sc_ih; /* intr handler */ 162 #endif 163 struct evcnt sc_intrcnt; /* intr count */ 164 struct scsi_link sc_link; /* scsi lint struct */ 165 #ifdef SPARC_DRIVER 166 volatile u_char *sc_reg; /* the registers */ 167 struct dma_softc *sc_dma; /* pointer to my dma */ 168 #else 169 #ifdef MAC68K_DRIVER 170 volatile u_char *sc_reg; /* the registers */ 171 struct dma_softc _sc_dma; /* my (fake) DMA structure */ 172 struct dma_softc *sc_dma; /* pointer to my (fake) DMA */ 173 u_char irq_mask; /* mask for clearing IRQ */ 174 #else 175 volatile u_int32_t *sc_reg; /* the registers */ 176 struct tcds_slotconfig *sc_dma; /* DMA/slot info lives here. */ 177 void *sc_cookie; /* intr. handling cookie */ 178 #endif 179 #endif 180 181 /* register defaults */ 182 u_char sc_cfg1; /* Config 1 */ 183 u_char sc_cfg2; /* Config 2, not ESP100 */ 184 u_char sc_cfg3; /* Config 3, only ESP200 */ 185 u_char sc_ccf; /* Clock Conversion */ 186 u_char sc_timeout; 187 188 /* register copies, see espreadregs() */ 189 u_char sc_espintr; 190 u_char sc_espstat; 191 u_char sc_espstep; 192 u_char sc_espfflags; 193 194 /* Lists of command blocks */ 195 TAILQ_HEAD(ecb_list, esp_ecb) free_list, 196 ready_list, 197 nexus_list; 198 199 struct esp_ecb *sc_nexus; /* current command */ 200 struct esp_ecb sc_ecb[8]; /* one per target */ 201 struct esp_tinfo sc_tinfo[8]; 202 203 /* Data about the current nexus (updated for every cmd switch) */ 204 caddr_t sc_dp; /* Current data pointer */ 205 ssize_t sc_dleft; /* Data left to transfer */ 206 207 /* Adapter state */ 208 int sc_phase; /* Copy of what bus phase we are in */ 209 int sc_prevphase; /* Copy of what bus phase we were in */ 210 u_char sc_state; /* State applicable to the adapter */ 211 u_char sc_flags; 212 u_char sc_selid; 213 u_char sc_lastcmd; 214 215 /* Message stuff */ 216 u_char sc_msgpriq; /* One or more messages to send (encoded) */ 217 u_char sc_msgout; /* What message is on its way out? */ 218 u_char sc_msgoutq; /* What messages have been sent so far? */ 219 u_char sc_omess[ESP_MAX_MSG_LEN]; 220 caddr_t sc_omp; /* Message pointer (for multibyte messages) */ 221 size_t sc_omlen; 222 u_char sc_imess[ESP_MAX_MSG_LEN + 1]; 223 caddr_t sc_imp; /* Message pointer (for multibyte messages) */ 224 size_t sc_imlen; 225 226 /* hardware/openprom stuff */ 227 int sc_node; /* PROM node ID */ 228 int sc_freq; /* Freq in HZ */ 229 #ifdef SPARC_DRIVER 230 int sc_pri; /* SBUS priority */ 231 #endif 232 int sc_id; /* our scsi id */ 233 int sc_rev; /* esp revision */ 234 int sc_minsync; /* minimum sync period / 4 */ 235 int sc_maxxfer; /* maximum transfer size */ 236 }; 237 238 /* values for sc_state */ 239 #define ESP_IDLE 1 /* waiting for something to do */ 240 #define ESP_SELECTING 2 /* SCSI command is arbiting */ 241 #define ESP_RESELECTED 3 /* Has been reselected */ 242 #define ESP_CONNECTED 4 /* Actively using the SCSI bus */ 243 #define ESP_DISCONNECT 5 /* MSG_DISCONNECT received */ 244 #define ESP_CMDCOMPLETE 6 /* MSG_CMDCOMPLETE received */ 245 #define ESP_CLEANING 7 246 #define ESP_SBR 8 /* Expect a SCSI RST because we commanded it */ 247 248 /* values for sc_flags */ 249 #define ESP_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */ 250 #define ESP_ABORTING 0x02 /* Bailing out */ 251 #define ESP_DOINGDMA 0x04 /* The FIFO data path is active! */ 252 #define ESP_SYNCHNEGO 0x08 /* Synch negotiation in progress. */ 253 #define ESP_ICCS 0x10 /* Expect status phase results */ 254 #define ESP_WAITI 0x20 /* Waiting for non-DMA data to arrive */ 255 #define ESP_ATN 0x40 /* ATN asserted */ 256 257 /* values for sc_msgout */ 258 #define SEND_DEV_RESET 0x01 259 #define SEND_PARITY_ERROR 0x02 260 #define SEND_INIT_DET_ERR 0x04 261 #define SEND_REJECT 0x08 262 #define SEND_IDENTIFY 0x10 263 #define SEND_ABORT 0x20 264 #define SEND_SDTR 0x40 265 #define SEND_WDTR 0x80 266 267 /* SCSI Status codes */ 268 #define ST_MASK 0x3e /* bit 0,6,7 is reserved */ 269 270 /* phase bits */ 271 #define IOI 0x01 272 #define CDI 0x02 273 #define MSGI 0x04 274 275 /* Information transfer phases */ 276 #define DATA_OUT_PHASE (0) 277 #define DATA_IN_PHASE (IOI) 278 #define COMMAND_PHASE (CDI) 279 #define STATUS_PHASE (CDI|IOI) 280 #define MESSAGE_OUT_PHASE (MSGI|CDI) 281 #define MESSAGE_IN_PHASE (MSGI|CDI|IOI) 282 283 #define PHASE_MASK (MSGI|CDI|IOI) 284 285 /* Some pseudo phases for getphase()*/ 286 #define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */ 287 #define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */ 288 #define PSEUDO_PHASE 0x100 /* "pseudo" bit */ 289 290 /* 291 * Macros to read and write the chip's registers. 292 */ 293 #ifdef SPARC_DRIVER 294 #define ESP_READ_REG(sc, reg) \ 295 ((sc)->sc_reg[(reg) * 4]) 296 #define ESP_WRITE_REG(sc, reg, val) \ 297 do { \ 298 u_char v = (val); \ 299 (sc)->sc_reg[(reg) * 4] = v; \ 300 } while (0) 301 #else /* ! SPARC_DRIVER */ 302 #ifdef MAC68K_DRIVER 303 #define ESP_READ_REG(sc, reg) \ 304 ((sc)->sc_reg[(reg) * 16]) 305 #define ESP_WRITE_REG(sc, reg, val) \ 306 do { \ 307 u_char v = (val); \ 308 (sc)->sc_reg[(reg) * 16] = v; \ 309 } while (0) 310 #else 311 #if 1 312 static inline u_char 313 ESP_READ_REG(sc, reg) 314 struct esp_softc *sc; 315 int reg; 316 { 317 u_char v; 318 319 v = sc->sc_reg[reg * 2] & 0xff; 320 alpha_mb(); 321 return v; 322 } 323 #else 324 #define ESP_READ_REG(sc, reg) \ 325 ((u_char)((sc)->sc_reg[(reg) * 2] & 0xff)) 326 #endif 327 #define ESP_WRITE_REG(sc, reg, val) \ 328 do { \ 329 u_char v = (val); \ 330 (sc)->sc_reg[(reg) * 2] = v; \ 331 alpha_mb(); \ 332 } while (0) 333 #endif /* MAC68K_DRIVER */ 334 #endif /* SPARC_DRIVER */ 335 336 #ifdef ESP_DEBUG 337 #define ESPCMD(sc, cmd) do { \ 338 if (esp_debug & ESP_SHOWCCMDS) \ 339 printf("<cmd:0x%x>", (unsigned)cmd); \ 340 sc->sc_lastcmd = cmd; \ 341 ESP_WRITE_REG(sc, ESP_CMD, cmd); \ 342 } while (0) 343 #else 344 #define ESPCMD(sc, cmd) ESP_WRITE_REG(sc, ESP_CMD, cmd) 345 #endif 346 347 #define SAME_ESP(sc, bp, ca) \ 348 ((bp->val[0] == ca->ca_slot && bp->val[1] == ca->ca_offset) || \ 349 (bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit)) 350 351 #ifndef SPARC_DRIVER 352 353 #ifdef MAC68K_DRIVER 354 355 /* DMA macros for ESP */ 356 #define DMA_ISINTR(sc) (ESP_READ_REG((sc)->sc_esp, ESP_STAT) & 0x80) 357 #define DMA_RESET(sc) do { (sc)->sc_active = 0; } while(0) 358 #define DMA_INTR(sc) dma_intr(sc) 359 #define DMA_SETUP(sc, paddr, plen, datain, pdmasize) \ 360 do { \ 361 (sc)->sc_dmaaddr = paddr; \ 362 (sc)->sc_pdmalen = plen; \ 363 (sc)->sc_datain = datain; \ 364 (sc)->sc_dmasize = *pdmasize; \ 365 } while (0) 366 367 #define DMA_GO(sc) \ 368 do { \ 369 if ((sc)->sc_datain == 0) { \ 370 ESP_WRITE_REG((sc)->sc_esp, \ 371 ESP_FIFO, **(sc)->sc_dmaaddr); \ 372 (*(sc)->sc_pdmalen)--; \ 373 } \ 374 (sc)->sc_active = 1; \ 375 } while (0) 376 377 #define DMA_ISACTIVE(sc) ((sc)->sc_active) 378 379 #else MAC68K_DRIVER 380 381 /* DMA macros for ESP */ 382 #define DMA_ISINTR(sc) tcds_dma_isintr(sc) 383 #define DMA_RESET(sc) tcds_dma_reset(sc) 384 #define DMA_INTR(sc) tcds_dma_intr(sc) 385 #define DMA_SETUP(sc, addr, len, datain, dmasize) \ 386 tcds_dma_setup(sc, addr, len, datain, dmasize) 387 #define DMA_GO(sc) tcds_dma_go(sc) 388 #define DMA_ISACTIVE(sc) tcds_dma_isactive(sc) 389 390 #endif /* MAC68K_DRIVER */ 391 #endif /* SPARC_DRIVER */ 392
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