if_mc_obio.c revision 1.18
1 /* $NetBSD: if_mc_obio.c,v 1.18 2012/10/27 17:18:00 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym (at) azeotrope.org> 5 * All rights reserved. 6 * 7 * Portions of this code are based on code by Denton Gentry <denny1 (at) home.com> 8 * and Yanagisawa Takeshi <yanagisw (at) aa.ap.titech.ac.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 /* 32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra 33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940 34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem 35 * Controller) for DMA to and from the MACE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_mc_obio.c,v 1.18 2012/10/27 17:18:00 chs Exp $"); 40 41 #include "opt_ddb.h" 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 49 #include <net/if.h> 50 #include <net/if_ether.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <machine/bus.h> 55 #include <machine/psc.h> 56 57 #include <mac68k/obio/obiovar.h> 58 #include <mac68k/dev/if_mcreg.h> 59 #include <mac68k/dev/if_mcvar.h> 60 61 #define MACE_REG_BASE 0x50F1C000 62 #define MACE_PROM_BASE 0x50F08000 63 64 hide int mc_obio_match(device_t, cfdata_t, void *); 65 hide void mc_obio_attach(device_t, device_t, void *); 66 hide void mc_obio_init(struct mc_softc *); 67 hide void mc_obio_put(struct mc_softc *, u_int); 68 hide int mc_dmaintr(void *); 69 hide void mc_reset_rxdma(struct mc_softc *); 70 hide void mc_reset_rxdma_set(struct mc_softc *, int); 71 hide void mc_reset_txdma(struct mc_softc *); 72 hide int mc_obio_getaddr(struct mc_softc *, u_int8_t *); 73 74 CFATTACH_DECL_NEW(mc_obio, sizeof(struct mc_softc), 75 mc_obio_match, mc_obio_attach, NULL, NULL); 76 77 hide int 78 mc_obio_match(device_t parent, cfdata_t cf, void *aux) 79 { 80 struct obio_attach_args *oa = aux; 81 bus_space_handle_t bsh; 82 int found = 0; 83 84 if (current_mac_model->class != MACH_CLASSAV) 85 return 0; 86 87 if (bus_space_map(oa->oa_tag, MACE_REG_BASE, MC_REGSIZE, 0, &bsh)) 88 return 0; 89 90 /* 91 * Make sure the MACE's I/O space is readable, and if it is, 92 * try to read the CHIPID register. A MACE will always have 93 * 0x?940, where the ? depends on the chip version. 94 */ 95 if (mac68k_bus_space_probe(oa->oa_tag, bsh, 0, 1)) { 96 if ((bus_space_read_1( 97 oa->oa_tag, bsh, MACE_REG(MACE_CHIPIDL)) == 0x40) && 98 ((bus_space_read_1( 99 oa->oa_tag, bsh, MACE_REG(MACE_CHIPIDH)) & 0xf) == 9)) 100 found = 1; 101 } 102 103 bus_space_unmap(oa->oa_tag, bsh, MC_REGSIZE); 104 105 return found; 106 } 107 108 hide void 109 mc_obio_attach(device_t parent, device_t self, void *aux) 110 { 111 struct obio_attach_args *oa = (struct obio_attach_args *)aux; 112 struct mc_softc *sc = device_private(self); 113 u_int8_t myaddr[ETHER_ADDR_LEN]; 114 int rsegs; 115 116 sc->sc_dev = self; 117 sc->sc_regt = oa->oa_tag; 118 sc->sc_biucc = XMTSP_64; 119 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 120 XMTBRST | RCVBRST; 121 sc->sc_plscc = PORTSEL_AUI; 122 123 if (bus_space_map(sc->sc_regt, MACE_REG_BASE, MC_REGSIZE, 0, 124 &sc->sc_regh)) { 125 printf(": failed to map space for MACE regs.\n"); 126 return; 127 } 128 129 if (mc_obio_getaddr(sc, myaddr)) { 130 printf(": failed to get MAC address.\n"); 131 return; 132 } 133 134 /* allocate memory for transmit and receive DMA buffers */ 135 sc->sc_dmat = oa->oa_dmat; 136 if (bus_dmamem_alloc(sc->sc_dmat, 2 * 0x800, 0, 0, &sc->sc_dmasegs_tx, 137 1, &rsegs, BUS_DMA_NOWAIT) != 0) { 138 printf(": failed to allocate TX DMA buffers.\n"); 139 return; 140 } 141 142 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dmasegs_tx, rsegs, 2 * 0x800, 143 (void*)&sc->sc_txbuf, BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 144 printf(": failed to map TX DMA buffers.\n"); 145 return; 146 } 147 148 if (bus_dmamem_alloc(sc->sc_dmat, MC_RXDMABUFS * 0x800, 0, 0, 149 &sc->sc_dmasegs_rx, 1, &rsegs, BUS_DMA_NOWAIT) != 0) { 150 printf(": failed to allocate RX DMA buffers.\n"); 151 return; 152 } 153 154 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dmasegs_rx, rsegs, 155 MC_RXDMABUFS * 0x800, (void*)&sc->sc_rxbuf, 156 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 157 printf(": failed to map RX DMA buffers.\n"); 158 return; 159 } 160 161 if (bus_dmamap_create(sc->sc_dmat, 2 * 0x800, 1, 2 * 0x800, 0, 162 BUS_DMA_NOWAIT, &sc->sc_dmam_tx) != 0) { 163 printf(": failed to allocate TX DMA map.\n"); 164 return; 165 } 166 167 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmam_tx, sc->sc_txbuf, 168 2 * 0x800, NULL, BUS_DMA_NOWAIT) != 0) { 169 printf(": failed to map TX DMA mapping.\n"); 170 return; 171 } 172 173 if (bus_dmamap_create(sc->sc_dmat, MC_RXDMABUFS * 0x800, 1, 174 MC_RXDMABUFS * 0x800, 0, BUS_DMA_NOWAIT, &sc->sc_dmam_rx) != 0) { 175 printf(": failed to allocate RX DMA map.\n"); 176 return; 177 } 178 179 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmam_rx, sc->sc_rxbuf, 180 MC_RXDMABUFS * 0x800, NULL, BUS_DMA_NOWAIT) != 0) { 181 printf(": failed to map RX DMA mapping.\n"); 182 return; 183 } 184 185 sc->sc_txbuf_phys = sc->sc_dmasegs_tx.ds_addr; 186 sc->sc_rxbuf_phys = sc->sc_dmasegs_rx.ds_addr; 187 188 sc->sc_bus_init = mc_obio_init; 189 sc->sc_putpacket = mc_obio_put; 190 191 /* disable receive DMA */ 192 psc_reg2(PSC_ENETRD_CTL) = 0x8800; 193 psc_reg2(PSC_ENETRD_CTL) = 0x1000; 194 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x1100; 195 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x1100; 196 197 /* disable transmit DMA */ 198 psc_reg2(PSC_ENETWR_CTL) = 0x8800; 199 psc_reg2(PSC_ENETWR_CTL) = 0x1000; 200 psc_reg2(PSC_ENETWR_CMD + PSC_SET0) = 0x1100; 201 psc_reg2(PSC_ENETWR_CMD + PSC_SET1) = 0x1100; 202 203 /* install interrupt handlers */ 204 add_psc_lev4_intr(PSCINTR_ENET_DMA, mc_dmaintr, sc); 205 add_psc_lev3_intr(mcintr, sc); 206 207 /* enable MACE DMA interrupts */ 208 psc_reg1(PSC_LEV4_IER) = 0x80 | (1 << PSCINTR_ENET_DMA); 209 210 /* don't know what this does */ 211 psc_reg2(PSC_ENETWR_CTL) = 0x9000; 212 psc_reg2(PSC_ENETRD_CTL) = 0x9000; 213 psc_reg2(PSC_ENETWR_CTL) = 0x0400; 214 psc_reg2(PSC_ENETRD_CTL) = 0x0400; 215 216 /* enable MACE interrupts */ 217 psc_reg1(PSC_LEV3_IER) = 0x80 | (1 << PSCINTR_ENET); 218 219 /* mcsetup returns 1 if something fails */ 220 if (mcsetup(sc, myaddr)) { 221 /* disable interrupts */ 222 psc_reg1(PSC_LEV4_IER) = (1 << PSCINTR_ENET_DMA); 223 psc_reg1(PSC_LEV3_IER) = (1 << PSCINTR_ENET); 224 /* remove interrupt handlers */ 225 remove_psc_lev4_intr(PSCINTR_ENET_DMA); 226 remove_psc_lev3_intr(); 227 228 bus_space_unmap(sc->sc_regt, sc->sc_regh, MC_REGSIZE); 229 return; 230 } 231 } 232 233 /* Bus-specific initialization */ 234 hide void 235 mc_obio_init(struct mc_softc *sc) 236 { 237 mc_reset_rxdma(sc); 238 mc_reset_txdma(sc); 239 } 240 241 hide void 242 mc_obio_put(struct mc_softc *sc, u_int len) 243 { 244 int offset = sc->sc_txset == 0 ? 0 : 0x800; 245 246 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam_tx, offset, 0x800, 247 BUS_DMASYNC_PREWRITE); 248 psc_reg4(PSC_ENETWR_ADDR + sc->sc_txset) = sc->sc_txbuf_phys + offset; 249 psc_reg4(PSC_ENETWR_LEN + sc->sc_txset) = len; 250 psc_reg2(PSC_ENETWR_CMD + sc->sc_txset) = 0x9800; 251 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam_tx, offset, 0x800, 252 BUS_DMASYNC_POSTWRITE); 253 254 sc->sc_txset ^= 0x10; 255 } 256 257 /* 258 * Interrupt handler for the MACE DMA completion interrupts 259 */ 260 int 261 mc_dmaintr(void *arg) 262 { 263 struct mc_softc *sc = arg; 264 u_int16_t status; 265 u_int32_t bufsleft, which; 266 int head; 267 268 /* 269 * Not sure what this does... figure out if this interrupt is 270 * really ours? 271 */ 272 while ((which = psc_reg4(0x804)) != psc_reg4(0x804)) 273 ; 274 if ((which & 0x60000000) == 0) 275 return 0; 276 277 /* Get the read channel status */ 278 status = psc_reg2(PSC_ENETRD_CTL); 279 if (status & 0x2000) { 280 /* I think this is an exceptional condition. Reset the DMA */ 281 mc_reset_rxdma(sc); 282 #ifdef MCDEBUG 283 printf("%s: resetting receive DMA channel (status 0x%04x)\n", 284 device_xname(sc->sc_dev), status); 285 #endif 286 } else if (status & 0x100) { 287 /* We've received some packets from the MACE */ 288 int offset; 289 290 /* Clear the interrupt */ 291 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x1100; 292 293 /* See how may receive buffers are left */ 294 bufsleft = psc_reg4(PSC_ENETRD_LEN + sc->sc_rxset); 295 head = MC_RXDMABUFS - bufsleft; 296 297 #if 0 /* I don't think this should ever happen */ 298 if (head == sc->sc_tail) { 299 #ifdef MCDEBUG 300 printf("%s: head == tail: suspending DMA?\n", 301 device_xname(sc->sc_dev)); 302 #endif 303 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9000; 304 } 305 #endif 306 307 /* Loop through, processing each of the packets */ 308 for (; sc->sc_tail < head; sc->sc_tail++) { 309 offset = sc->sc_tail * 0x800; 310 311 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam_rx, 312 PAGE_SIZE + offset, 0x800, 313 BUS_DMASYNC_PREREAD); 314 315 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[offset]; 316 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[offset+2]; 317 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[offset+4]; 318 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[offset+6]; 319 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset + 16; 320 321 mc_rint(sc); 322 323 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam_rx, 324 PAGE_SIZE + offset, 0x800, 325 BUS_DMASYNC_POSTREAD); 326 } 327 328 /* 329 * If we're out of buffers, reset this register set 330 * and switch to the other one. Otherwise, reactivate 331 * this set. 332 */ 333 if (bufsleft == 0) { 334 mc_reset_rxdma_set(sc, sc->sc_rxset); 335 sc->sc_rxset ^= 0x10; 336 } else 337 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9800; 338 } 339 340 /* Get the write channel status */ 341 status = psc_reg2(PSC_ENETWR_CTL); 342 if (status & 0x2000) { 343 /* I think this is an exceptional condition. Reset the DMA */ 344 mc_reset_txdma(sc); 345 #ifdef MCDEBUG 346 printf("%s: resetting transmit DMA channel (status 0x%04x)\n", 347 device_xname(sc->sc_dev), status); 348 #endif 349 } else if (status & 0x100) { 350 /* Clear the interrupt and switch register sets */ 351 psc_reg2(PSC_ENETWR_CMD + sc->sc_txseti) = 0x100; 352 sc->sc_txseti ^= 0x10; 353 } 354 355 return 1; 356 } 357 358 359 hide void 360 mc_reset_rxdma(struct mc_softc *sc) 361 { 362 u_int8_t maccc; 363 364 /* Disable receiver, reset the DMA channels */ 365 maccc = NIC_GET(sc, MACE_MACCC); 366 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 367 psc_reg2(PSC_ENETRD_CTL) = 0x8800; 368 mc_reset_rxdma_set(sc, 0); 369 psc_reg2(PSC_ENETRD_CTL) = 0x400; 370 371 psc_reg2(PSC_ENETRD_CTL) = 0x8800; 372 mc_reset_rxdma_set(sc, 0x10); 373 psc_reg2(PSC_ENETRD_CTL) = 0x400; 374 375 /* Reenable receiver, reenable DMA */ 376 NIC_PUT(sc, MACE_MACCC, maccc); 377 sc->sc_rxset = 0; 378 379 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x9800; 380 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x9800; 381 } 382 383 hide void 384 mc_reset_rxdma_set(struct mc_softc *sc, int set) 385 { 386 /* disable DMA while modifying the registers, then reenable DMA */ 387 psc_reg2(PSC_ENETRD_CMD + set) = 0x0100; 388 psc_reg4(PSC_ENETRD_ADDR + set) = sc->sc_rxbuf_phys; 389 psc_reg4(PSC_ENETRD_LEN + set) = MC_RXDMABUFS; 390 psc_reg2(PSC_ENETRD_CMD + set) = 0x9800; 391 sc->sc_tail = 0; 392 } 393 394 hide void 395 mc_reset_txdma(struct mc_softc *sc) 396 { 397 u_int8_t maccc; 398 399 psc_reg2(PSC_ENETWR_CTL) = 0x8800; 400 maccc = NIC_GET(sc, MACE_MACCC); 401 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 402 sc->sc_txset = sc->sc_txseti = 0; 403 psc_reg2(PSC_ENETWR_CTL) = 0x400; 404 NIC_PUT(sc, MACE_MACCC, maccc); 405 } 406 407 hide int 408 mc_obio_getaddr(struct mc_softc *sc, u_int8_t *lladdr) 409 { 410 bus_space_handle_t bsh; 411 u_char csum; 412 413 if (bus_space_map(sc->sc_regt, MACE_PROM_BASE, 8*16, 0, &bsh)) { 414 printf(": failed to map space to read MACE address.\n%s", 415 device_xname(sc->sc_dev)); 416 return (-1); 417 } 418 419 if (!mac68k_bus_space_probe(sc->sc_regt, bsh, 0, 1)) { 420 bus_space_unmap(sc->sc_regt, bsh, 8*16); 421 return (-1); 422 } 423 424 csum = mc_get_enaddr(sc->sc_regt, bsh, 1, lladdr); 425 if (csum != 0xff) 426 printf(": ethernet PROM checksum failed (0x%x != 0xff)\n%s", 427 (int)csum, device_xname(sc->sc_dev)); 428 429 bus_space_unmap(sc->sc_regt, bsh, 8*16); 430 431 return (csum == 0xff ? 0 : -1); 432 } 433
Indexes created Thu Oct 02 14:10:14 GMT 2025