cuda.c revision 1.1
1 /* $NetBSD: cuda.c,v 1.1 2007/01/17 23:25:45 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of The NetBSD Foundation nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.1 2007/01/17 23:25:45 macallan Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <dev/clock_subr.h> 44 #include <dev/i2c/i2cvar.h> 45 46 #include <macppc/dev/viareg.h> 47 #include <macppc/dev/cudavar.h> 48 49 #include <dev/ofw/openfirm.h> 50 #include <dev/adb/adbvar.h> 51 #include "opt_cuda.h" 52 53 #ifdef CUDA_DEBUG 54 #define DPRINTF printf 55 #else 56 #define DPRINTF while (0) printf 57 #endif 58 59 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 60 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 61 #define CUDA_OUT 0x3 /* sending out a command */ 62 #define CUDA_IN 0x4 /* receiving data */ 63 #define CUDA_POLLING 0x5 /* polling - II only */ 64 65 static void cuda_attach(struct device *, struct device *, void *); 66 static int cuda_match(struct device *, struct cfdata *, void *); 67 static void cuda_autopoll(void *, int); 68 69 static int cuda_intr(void *); 70 71 typedef struct _cuda_handler { 72 int (*handler)(void *, int, uint8_t *); 73 void *cookie; 74 } CudaHandler; 75 76 struct cuda_softc { 77 struct device sc_dev; 78 void *sc_ih; 79 CudaHandler sc_handlers[16]; 80 struct todr_chip_handle sc_todr; 81 struct adb_bus_accessops sc_adbops; 82 struct i2c_controller sc_i2c; 83 struct lock sc_buslock; 84 bus_space_tag_t sc_memt; 85 bus_space_handle_t sc_memh; 86 int sc_node; 87 int sc_state; 88 int sc_waiting; 89 int sc_polling; 90 int sc_sent; 91 int sc_out_length; 92 int sc_received; 93 int sc_iic_done; 94 int sc_error; 95 /* time */ 96 uint32_t sc_tod; 97 uint32_t sc_autopoll; 98 uint32_t sc_todev; 99 /* ADB */ 100 void (*sc_adb_handler)(void *, int, uint8_t *); 101 void *sc_adb_cookie; 102 uint32_t sc_i2c_read_len; 103 /* internal buffers */ 104 uint8_t sc_in[256]; 105 uint8_t sc_out[256]; 106 }; 107 108 CFATTACH_DECL(cuda, sizeof(struct cuda_softc), 109 cuda_match, cuda_attach, NULL, NULL); 110 111 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 112 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 113 static void cuda_idle(struct cuda_softc *); 114 static void cuda_tip(struct cuda_softc *); 115 static void cuda_clear_tip(struct cuda_softc *); 116 static void cuda_in(struct cuda_softc *); 117 static void cuda_out(struct cuda_softc *); 118 static void cuda_toggle_ack(struct cuda_softc *); 119 static void cuda_ack_off(struct cuda_softc *); 120 static int cuda_intr_state(struct cuda_softc *); 121 122 static void cuda_init(struct cuda_softc *); 123 124 /* 125 * send a message to Cuda. 126 */ 127 /* cookie, flags, length, data */ 128 static int cuda_send(void *, int, int, uint8_t *); 129 static void cuda_poll(void *); 130 static void cuda_adb_poll(void *); 131 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 132 133 static int cuda_error_handler(void *, int, uint8_t *); 134 135 static int cuda_todr_handler(void *, int, uint8_t *); 136 static int cuda_todr_set(todr_chip_handle_t, volatile struct timeval *); 137 static int cuda_todr_get(todr_chip_handle_t, volatile struct timeval *); 138 139 static int cuda_adb_handler(void *, int, uint8_t *); 140 static void cuda_final(struct device *); 141 142 static struct cuda_attach_args *cuda0 = NULL; 143 144 /* ADB bus attachment stuff */ 145 static int cuda_adb_send(void *, int, int, int, uint8_t *); 146 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 147 148 /* i2c stuff */ 149 static int cuda_i2c_acquire_bus(void *, int); 150 static void cuda_i2c_release_bus(void *, int); 151 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 152 void *, size_t, int); 153 154 static int 155 cuda_match(struct device *parent, struct cfdata *cf, void *aux) 156 { 157 struct confargs *ca = aux; 158 159 if (ca->ca_nreg < 8) 160 return 0; 161 162 if (ca->ca_nintr < 4) 163 return 0; 164 165 if (strcmp(ca->ca_name, "via-cuda") == 0) { 166 return 10; /* beat adb* at obio? */ 167 } 168 169 return 0; 170 } 171 172 static void 173 cuda_attach(struct device *parent, struct device *dev, void *aux) 174 { 175 struct confargs *ca = aux; 176 struct cuda_softc *sc = (struct cuda_softc *)dev; 177 struct i2cbus_attach_args iba; 178 static struct cuda_attach_args caa; 179 int irq = ca->ca_intr[0]; 180 int node, i, child; 181 char name[32]; 182 183 node = getnodebyname(OF_parent(ca->ca_node), "extint-gpio1"); 184 if (node) 185 OF_getprop(node, "interrupts", &irq, 4); 186 187 printf(" irq %d: ", irq); 188 189 sc->sc_node = ca->ca_node; 190 sc->sc_memt = ca->ca_tag; 191 192 sc->sc_sent = 0; 193 sc->sc_received = 0; 194 sc->sc_waiting = 0; 195 sc->sc_polling = 0; 196 sc->sc_state = CUDA_NOTREADY; 197 sc->sc_error = 0; 198 sc->sc_i2c_read_len = 0; 199 200 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 201 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 202 203 printf("%s: unable to map registers\n", dev->dv_xname); 204 return; 205 } 206 sc->sc_ih = intr_establish(irq, IST_LEVEL, IPL_HIGH, cuda_intr, sc); 207 printf("\n"); 208 209 for (i = 0; i < 16; i++) { 210 sc->sc_handlers[i].handler = NULL; 211 sc->sc_handlers[i].cookie = NULL; 212 } 213 214 cuda_init(sc); 215 216 /* now attach children */ 217 config_interrupts(dev, cuda_final); 218 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 219 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 220 221 child = OF_child(ca->ca_node); 222 while (child != 0) { 223 224 if (OF_getprop(child, "name", name, 32) == 0) 225 continue; 226 if (strncmp(name, "adb", 4) == 0) { 227 228 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 229 sc->sc_adbops.cookie = sc; 230 sc->sc_adbops.send = cuda_adb_send; 231 sc->sc_adbops.poll = cuda_adb_poll; 232 sc->sc_adbops.autopoll = cuda_autopoll; 233 sc->sc_adbops.set_handler = cuda_adb_set_handler; 234 config_found_ia(dev, "adb_bus", &sc->sc_adbops, 235 nadb_print); 236 } else if (strncmp(name, "rtc", 4) == 0) { 237 238 sc->sc_todr.todr_gettime = cuda_todr_get; 239 sc->sc_todr.todr_settime = cuda_todr_set; 240 sc->sc_todr.cookie = sc; 241 todr_attach(&sc->sc_todr); 242 } 243 child = OF_peer(child); 244 } 245 246 caa.cookie = sc; 247 caa.set_handler = cuda_set_handler; 248 caa.send = cuda_send; 249 caa.poll = cuda_poll; 250 // config_found(dev, &caa, cuda_print); 251 252 253 iba.iba_tag = &sc->sc_i2c; 254 sc->sc_i2c.ic_cookie = sc; 255 sc->sc_i2c.ic_acquire_bus = cuda_i2c_acquire_bus; 256 sc->sc_i2c.ic_release_bus = cuda_i2c_release_bus; 257 sc->sc_i2c.ic_send_start = NULL; 258 sc->sc_i2c.ic_send_stop = NULL; 259 sc->sc_i2c.ic_initiate_xfer = NULL; 260 sc->sc_i2c.ic_read_byte = NULL; 261 sc->sc_i2c.ic_write_byte = NULL; 262 sc->sc_i2c.ic_exec = cuda_i2c_exec; 263 config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 264 265 if (cuda0 == NULL) 266 cuda0 = &caa; 267 } 268 269 static void 270 cuda_init(struct cuda_softc *sc) 271 { 272 volatile int i; 273 uint8_t reg; 274 275 reg = cuda_read_reg(sc, vDirB); 276 reg |= 0x30; /* register B bits 4 and 5: outputs */ 277 cuda_write_reg(sc, vDirB, reg); 278 279 reg = cuda_read_reg(sc, vDirB); 280 reg &= 0xf7; /* register B bit 3: input */ 281 cuda_write_reg(sc, vDirB, reg); 282 283 reg = cuda_read_reg(sc, vACR); 284 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 285 cuda_write_reg(sc, vACR, reg); 286 287 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 288 289 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 290 291 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 292 cuda_idle(sc); /* set ADB bus state to idle */ 293 294 /* sort of a device reset */ 295 i = cuda_read_reg(sc, vSR); /* clear interrupt */ 296 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 297 cuda_idle(sc); /* reset state to idle */ 298 delay(150); 299 cuda_tip(sc); /* signal start of frame */ 300 delay(150); 301 cuda_toggle_ack(sc); 302 delay(150); 303 cuda_clear_tip(sc); 304 delay(150); 305 cuda_idle(sc); /* back to idle state */ 306 i = cuda_read_reg(sc, vSR); /* clear interrupt */ 307 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 308 } 309 310 static void 311 cuda_final(struct device *dev) 312 { 313 struct cuda_softc *sc = (struct cuda_softc *)dev; 314 315 sc->sc_polling = 0; 316 #if 0 317 { 318 int err; 319 uint8_t buffer[2], buf2[2]; 320 321 /* trying to read */ 322 printf("reading\n"); 323 buffer[0] = 0; 324 buffer[1] = 1; 325 buf2[0] = 0; 326 err = cuda_i2c_exec(sc, I2C_OP_WRITE, 0x8a, buffer, 2, buf2, 0, 0); 327 buf2[0] = 0; 328 err = cuda_i2c_exec(sc, I2C_OP_WRITE | I2C_OP_READ, 0x8a, buffer, 1, buf2, 2, 0); 329 printf("buf2: %02x\n", buf2[0]); 330 } 331 #endif 332 } 333 334 static inline void 335 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 336 { 337 338 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 339 } 340 341 static inline uint8_t 342 cuda_read_reg(struct cuda_softc *sc, int offset) 343 { 344 345 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 346 } 347 348 static int 349 cuda_set_handler(void *cookie, int type, 350 int (*handler)(void *, int, uint8_t *), void *hcookie) 351 { 352 struct cuda_softc *sc = cookie; 353 CudaHandler *me; 354 355 if ((type >= 0) && (type < 16)) { 356 me = &sc->sc_handlers[type]; 357 me->handler = handler; 358 me->cookie = hcookie; 359 return 0; 360 } 361 return -1; 362 } 363 364 static int 365 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 366 { 367 struct cuda_softc *sc = cookie; 368 int s; 369 370 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 371 if (sc->sc_state == CUDA_NOTREADY) 372 return -1; 373 374 s = splhigh(); 375 376 if ((sc->sc_state == CUDA_IDLE) /*&& 377 ((cuda_read_reg(sc, vBufB) & vPB3) == vPB3)*/) { 378 /* fine */ 379 DPRINTF("chip is idle\n"); 380 } else { 381 DPRINTF("cuda state is %d\n", sc->sc_state); 382 if (sc->sc_waiting == 0) { 383 sc->sc_waiting = 1; 384 } else { 385 splx(s); 386 return -1; 387 } 388 } 389 390 sc->sc_error = 0; 391 memcpy(sc->sc_out, msg, length); 392 sc->sc_out_length = length; 393 sc->sc_sent = 0; 394 395 if (sc->sc_waiting != 1) { 396 397 delay(150); 398 sc->sc_state = CUDA_OUT; 399 cuda_out(sc); 400 cuda_write_reg(sc, vSR, sc->sc_out[0]); 401 cuda_ack_off(sc); 402 cuda_tip(sc); 403 } 404 sc->sc_waiting = 1; 405 406 if (sc->sc_polling || poll || cold) { 407 cuda_poll(sc); 408 } 409 410 splx(s); 411 412 return 0; 413 } 414 415 static void 416 cuda_poll(void *cookie) 417 { 418 struct cuda_softc *sc = cookie; 419 420 DPRINTF("polling\n"); 421 while ((sc->sc_state != CUDA_IDLE) || 422 (cuda_intr_state(sc)) || 423 (sc->sc_waiting == 1)) { 424 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 425 cuda_intr(sc); 426 } 427 } 428 } 429 430 static void 431 cuda_adb_poll(void *cookie) 432 { 433 struct cuda_softc *sc = cookie; 434 435 cuda_intr(sc); 436 } 437 438 static void 439 cuda_idle(struct cuda_softc *sc) 440 { 441 uint8_t reg; 442 443 reg = cuda_read_reg(sc, vBufB); 444 reg |= (vPB4 | vPB5); 445 cuda_write_reg(sc, vBufB, reg); 446 } 447 448 static void 449 cuda_tip(struct cuda_softc *sc) 450 { 451 uint8_t reg; 452 453 reg = cuda_read_reg(sc, vBufB); 454 reg &= ~vPB5; 455 cuda_write_reg(sc, vBufB, reg); 456 } 457 458 static void 459 cuda_clear_tip(struct cuda_softc *sc) 460 { 461 uint8_t reg; 462 463 reg = cuda_read_reg(sc, vBufB); 464 reg |= vPB5; 465 cuda_write_reg(sc, vBufB, reg); 466 } 467 468 static void 469 cuda_in(struct cuda_softc *sc) 470 { 471 uint8_t reg; 472 473 reg = cuda_read_reg(sc, vACR); 474 reg &= ~vSR_OUT; 475 cuda_write_reg(sc, vACR, reg); 476 } 477 478 static void 479 cuda_out(struct cuda_softc *sc) 480 { 481 uint8_t reg; 482 483 reg = cuda_read_reg(sc, vACR); 484 reg |= vSR_OUT; 485 cuda_write_reg(sc, vACR, reg); 486 } 487 488 static void 489 cuda_toggle_ack(struct cuda_softc *sc) 490 { 491 uint8_t reg; 492 493 reg = cuda_read_reg(sc, vBufB); 494 reg ^= vPB4; 495 cuda_write_reg(sc, vBufB, reg); 496 } 497 498 static void 499 cuda_ack_off(struct cuda_softc *sc) 500 { 501 uint8_t reg; 502 503 reg = cuda_read_reg(sc, vBufB); 504 reg |= vPB4; 505 cuda_write_reg(sc, vBufB, reg); 506 } 507 508 static int 509 cuda_intr_state(struct cuda_softc *sc) 510 { 511 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 512 } 513 514 static int 515 cuda_intr(void *arg) 516 { 517 struct cuda_softc *sc = arg; 518 int i, ending, type; 519 unsigned int s; 520 uint8_t reg; 521 522 s = splhigh(); /* can't be too careful - might be called */ 523 /* from a routine, NOT an interrupt */ 524 525 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 526 if ((reg & 0x80) == 0) { 527 splx(s); 528 return 0; /* No interrupts to process */ 529 } 530 DPRINTF(":"); 531 532 cuda_write_reg(sc, vIFR, /*reg &*/ 0x7f); /* Clear 'em */ 533 534 //cuda_write_reg(sc, vIER, 0x04); /* disable ADB interrupt on IIs. */ 535 536 switch_start: 537 switch (sc->sc_state) { 538 case CUDA_IDLE: 539 /* 540 * This is an unexpected packet, so grab the first (dummy) 541 * byte, set up the proper vars, and tell the chip we are 542 * starting to receive the packet by setting the TIP bit. 543 */ 544 sc->sc_in[1] = cuda_read_reg(sc, vSR); 545 DPRINTF("start: %02x", sc->sc_in[1]); 546 if (cuda_intr_state(sc) == 0) { 547 /* must have been a fake start */ 548 DPRINTF(" ... fake start\n"); 549 if (sc->sc_waiting) { 550 /* start over */ 551 delay(150); 552 sc->sc_state = CUDA_OUT; 553 sc->sc_sent = 0; 554 cuda_out(sc); 555 cuda_write_reg(sc, vSR, sc->sc_out[1]); 556 cuda_ack_off(sc); 557 cuda_tip(sc); 558 } 559 break; 560 } 561 562 cuda_in(sc); 563 cuda_tip(sc); 564 565 sc->sc_received = 1; 566 sc->sc_state = CUDA_IN; 567 DPRINTF(" CUDA_IN"); 568 break; 569 570 case CUDA_IN: 571 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 572 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 573 ending = 0; 574 if (sc->sc_received > 255) { 575 /* bitch only once */ 576 if (sc->sc_received == 256) { 577 printf("%s: input overflow\n", 578 sc->sc_dev.dv_xname); 579 ending = 1; 580 } 581 } else 582 sc->sc_received++; 583 if (sc->sc_received > 3) { 584 if ((sc->sc_in[3] == CMD_IIC) && 585 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 586 ending = 1; 587 } 588 } 589 590 /* intr off means this is the last byte (end of frame) */ 591 if (cuda_intr_state(sc) == 0) { 592 ending = 1; 593 DPRINTF(".\n"); 594 } else { 595 cuda_toggle_ack(sc); 596 } 597 598 if (ending == 1) { /* end of message? */ 599 600 sc->sc_in[0] = sc->sc_received - 1; 601 602 /* reset vars and signal the end of this frame */ 603 cuda_idle(sc); 604 DPRINTF(" CUDA_IDLE"); 605 sc->sc_state = CUDA_IDLE; 606 607 /* check if we have a handler for this message */ 608 type = sc->sc_in[1]; 609 if ((type >= 0) && (type < 16)) { 610 CudaHandler *me = &sc->sc_handlers[type]; 611 612 if (me->handler != NULL) { 613 me->handler(me->cookie, 614 sc->sc_received - 1, &sc->sc_in[1]); 615 } else { 616 printf("no handler for type %02x\n", type); 617 panic("barf"); 618 } 619 } 620 621 sc->sc_received = 0; 622 623 /* 624 * If there is something waiting to be sent out, 625 * the set everything up and send the first byte. 626 */ 627 if (sc->sc_waiting == 1) { 628 629 DPRINTF("pending write\n"); 630 delay(1500); /* required */ 631 sc->sc_sent = 0; 632 sc->sc_state = CUDA_OUT; 633 634 /* 635 * If the interrupt is on, we were too slow 636 * and the chip has already started to send 637 * something to us, so back out of the write 638 * and start a read cycle. 639 */ 640 if (cuda_intr_state(sc)) { 641 cuda_in(sc); 642 cuda_idle(sc); 643 sc->sc_sent = 0; 644 sc->sc_state = CUDA_IDLE; 645 sc->sc_received = 0; 646 delay(150); 647 DPRINTF("too slow - incoming message\n"); 648 goto switch_start; 649 } 650 /* 651 * If we got here, it's ok to start sending 652 * so load the first byte and tell the chip 653 * we want to send. 654 */ 655 cuda_tip(sc); 656 cuda_out(sc); 657 cuda_write_reg(sc, vSR, 658 sc->sc_out[sc->sc_sent]); 659 } 660 } 661 break; 662 663 case CUDA_OUT: 664 i = cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 665 666 sc->sc_sent++; 667 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 668 669 DPRINTF("incoming msg during send\n"); 670 cuda_in(sc); /* make sure SR is set to IN */ 671 cuda_idle(sc); 672 sc->sc_sent = 0; /* must start all over */ 673 sc->sc_state = CUDA_IDLE; /* new state */ 674 sc->sc_received = 0; 675 sc->sc_waiting = 1; /* must retry when done with 676 * read */ 677 delay(150); 678 goto switch_start; /* process next state right 679 * now */ 680 break; 681 } 682 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 683 684 sc->sc_waiting = 0; /* done writing */ 685 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 686 cuda_in(sc); 687 cuda_idle(sc); 688 DPRINTF("done sending\n"); 689 } else { 690 /* send next byte */ 691 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 692 cuda_toggle_ack(sc); /* signal byte ready to 693 * shift */ 694 } 695 break; 696 697 case CUDA_NOTREADY: 698 DPRINTF("adb: not yet initialized\n"); 699 break; 700 701 default: 702 DPRINTF("intr: unknown ADB state\n"); 703 break; 704 } 705 706 //cuda_write_reg(sc, vIER, 0x84); /* enable ADB interrupt on IIs. */ 707 708 splx(s); /* restore */ 709 710 return 1; 711 } 712 713 static int 714 cuda_error_handler(void *cookie, int len, uint8_t *data) 715 { 716 struct cuda_softc *sc = cookie; 717 718 /* 719 * something went wrong 720 * byte 3 seems to be the failed command 721 */ 722 sc->sc_error = 1; 723 wakeup(&sc->sc_todev); 724 return 0; 725 } 726 727 728 /* real time clock */ 729 730 static int 731 cuda_todr_handler(void *cookie, int len, uint8_t *data) 732 { 733 struct cuda_softc *sc = cookie; 734 735 #ifdef CUDA_DEBUG 736 int i; 737 printf("msg: %02x", data[0]); 738 for (i = 1; i < len; i++) { 739 printf(" %02x", data[i]); 740 } 741 printf("\n"); 742 #endif 743 744 switch(data[2]) { 745 case CMD_READ_RTC: 746 memcpy(&sc->sc_tod, &data[3], 4); 747 break; 748 case CMD_WRITE_RTC: 749 sc->sc_tod = 0xffffffff; 750 break; 751 case CMD_AUTOPOLL: 752 sc->sc_autopoll = 1; 753 break; 754 case CMD_IIC: 755 sc->sc_iic_done = len; 756 break; 757 } 758 wakeup(&sc->sc_todev); 759 return 0; 760 } 761 762 #define DIFF19041970 2082844800 763 764 static int 765 cuda_todr_get(todr_chip_handle_t tch, volatile struct timeval *tvp) 766 { 767 struct cuda_softc *sc = tch->cookie; 768 int cnt = 0; 769 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 770 771 sc->sc_tod = 0; 772 cuda_send(sc, 0, 2, cmd); 773 774 while ((sc->sc_tod == 0) && (cnt < 10)) { 775 tsleep(&sc->sc_todev, 0, "todr", 10); 776 cnt++; 777 } 778 779 if (sc->sc_tod == 0) 780 return EIO; 781 782 tvp->tv_sec = sc->sc_tod - DIFF19041970; 783 DPRINTF("tod: %ld\n", tvp->tv_sec); 784 tvp->tv_usec = 0; 785 return 0; 786 } 787 788 static int 789 cuda_todr_set(todr_chip_handle_t tch, volatile struct timeval *tvp) 790 { 791 struct cuda_softc *sc = tch->cookie; 792 uint32_t sec; 793 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 794 795 sec = tvp->tv_sec + DIFF19041970; 796 memcpy(&cmd[2], &sec, 4); 797 sc->sc_tod = 0; 798 if (cuda_send(sc, 0, 6, cmd) == 0) { 799 while (sc->sc_tod == 0) { 800 tsleep(&sc->sc_todev, 0, "todr", 10); 801 } 802 return 0; 803 } 804 return -1; 805 806 } 807 808 /* poweroff and reboot */ 809 810 void 811 cuda_poweroff() 812 { 813 struct cuda_softc *sc; 814 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 815 816 if (cuda0 == NULL) 817 return; 818 sc = cuda0->cookie; 819 sc->sc_polling = 1; 820 cuda0->poll(sc); 821 if (cuda0->send(sc, 1, 2, cmd) == 0) 822 while (1); 823 } 824 825 void 826 cuda_restart() 827 { 828 struct cuda_softc *sc; 829 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 830 831 if (cuda0 == NULL) 832 return; 833 sc = cuda0->cookie; 834 sc->sc_polling = 1; 835 cuda0->poll(sc); 836 if (cuda0->send(sc, 1, 2, cmd) == 0) 837 while (1); 838 } 839 840 /* ADB message handling */ 841 842 static void 843 cuda_autopoll(void *cookie, int flag) 844 { 845 struct cuda_softc *sc = cookie; 846 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 847 848 if (cmd[2] == sc->sc_autopoll) 849 return; 850 851 sc->sc_autopoll = -1; 852 cuda_send(sc, 0, 3, cmd); 853 while(sc->sc_autopoll == -1) { 854 if (sc->sc_polling || cold) { 855 cuda_poll(sc); 856 } else 857 tsleep(&sc->sc_todev, 0, "autopoll", 100); 858 } 859 } 860 861 static int 862 cuda_adb_handler(void *cookie, int len, uint8_t *data) 863 { 864 struct cuda_softc *sc = cookie; 865 866 if (sc->sc_adb_handler != NULL) { 867 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 868 &data[1]); 869 return 0; 870 } 871 return -1; 872 } 873 874 static int 875 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 876 { 877 struct cuda_softc *sc = cookie; 878 int i, s = 0; 879 uint8_t packet[16]; 880 881 /* construct an ADB command packet and send it */ 882 packet[0] = CUDA_ADB; 883 packet[1] = command; 884 for (i = 0; i < len; i++) 885 packet[i + 2] = data[i]; 886 if (poll || cold) { 887 s = splhigh(); 888 cuda_poll(sc); 889 } 890 cuda_send(sc, poll, len + 2, packet); 891 if (poll || cold) { 892 cuda_poll(sc); 893 splx(s); 894 } 895 return 0; 896 } 897 898 static int 899 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 900 void *hcookie) 901 { 902 struct cuda_softc *sc = cookie; 903 904 /* register a callback for incoming ADB messages */ 905 sc->sc_adb_handler = handler; 906 sc->sc_adb_cookie = hcookie; 907 return 0; 908 } 909 910 /* i2c message handling */ 911 912 static int 913 cuda_i2c_acquire_bus(void *cookie, int flags) 914 { 915 /* nothing yet */ 916 return 0; 917 } 918 919 static void 920 cuda_i2c_release_bus(void *cookie, int flags) 921 { 922 /* nothing here either */ 923 } 924 925 static int 926 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 927 size_t send_len, void *_recv, size_t recv_len, int flags) 928 { 929 struct cuda_softc *sc = cookie; 930 const uint8_t *send = _send; 931 uint8_t *recv = _recv; 932 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 933 934 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 935 command[2] = addr; 936 937 memcpy(&command[3], send, min((int)send_len, 12)); 938 939 sc->sc_iic_done = 0; 940 cuda_send(sc, sc->sc_polling, send_len + 3, command); 941 942 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 943 if (sc->sc_polling || cold) { 944 cuda_poll(sc); 945 } else 946 tsleep(&sc->sc_todev, 0, "i2c", 1000); 947 } 948 949 if (sc->sc_error) { 950 sc->sc_error = 0; 951 return -1; 952 } 953 954 /* see if we're supposed to do a read */ 955 if (recv_len > 0) { 956 sc->sc_iic_done = 0; 957 command[2] |= 1; 958 command[3] = 0; 959 960 /* 961 * XXX we need to do something to limit the size of the answer 962 * - apparently the chip keeps sending until we tell it to stop 963 */ 964 sc->sc_i2c_read_len = recv_len; 965 DPRINTF("rcv_len: %d\n", recv_len); 966 cuda_send(sc, sc->sc_polling, 3, command); 967 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 968 if (sc->sc_polling || cold) { 969 cuda_poll(sc); 970 } else 971 tsleep(&sc->sc_todev, 0, "i2c", 1000); 972 } 973 974 if (sc->sc_error) { 975 printf("error trying to read\n"); 976 sc->sc_error = 0; 977 return -1; 978 } 979 } 980 981 DPRINTF("received: %d\n", sc->sc_iic_done); 982 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 983 int rlen; 984 985 /* we got an answer */ 986 rlen = min(sc->sc_iic_done - 3, recv_len); 987 memcpy(recv, &sc->sc_in[4], rlen); 988 #ifdef CUDA_DEBUG 989 { 990 int i; 991 printf("ret:"); 992 for (i = 0; i < rlen; i++) 993 printf(" %02x", recv[i]); 994 printf("\n"); 995 } 996 #endif 997 return rlen; 998 } 999 return 0; 1000 } 1001
Indexes created Fri Sep 26 08:10:20 GMT 2025