cuda.c revision 1.20
1 /* $NetBSD: cuda.c,v 1.20 2014/08/13 10:56:35 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.20 2014/08/13 10:56:35 macallan Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/mutex.h> 38 39 #include <sys/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 #include <dev/clock_subr.h> 43 #include <dev/i2c/i2cvar.h> 44 45 #include <macppc/dev/viareg.h> 46 #include <macppc/dev/cudavar.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/adb/adbvar.h> 50 #include "opt_cuda.h" 51 52 #ifdef CUDA_DEBUG 53 #define DPRINTF printf 54 #else 55 #define DPRINTF while (0) printf 56 #endif 57 58 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 59 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 60 #define CUDA_OUT 0x3 /* sending out a command */ 61 #define CUDA_IN 0x4 /* receiving data */ 62 #define CUDA_POLLING 0x5 /* polling - II only */ 63 64 static void cuda_attach(device_t, device_t, void *); 65 static int cuda_match(device_t, struct cfdata *, void *); 66 static void cuda_autopoll(void *, int); 67 68 static int cuda_intr(void *); 69 70 typedef struct _cuda_handler { 71 int (*handler)(void *, int, uint8_t *); 72 void *cookie; 73 } CudaHandler; 74 75 struct cuda_softc { 76 device_t sc_dev; 77 void *sc_ih; 78 CudaHandler sc_handlers[16]; 79 struct todr_chip_handle sc_todr; 80 struct adb_bus_accessops sc_adbops; 81 struct i2c_controller sc_i2c; 82 kmutex_t sc_buslock; 83 bus_space_tag_t sc_memt; 84 bus_space_handle_t sc_memh; 85 int sc_node; 86 int sc_state; 87 int sc_waiting; 88 int sc_polling; 89 int sc_sent; 90 int sc_out_length; 91 int sc_received; 92 int sc_iic_done; 93 int sc_error; 94 /* time */ 95 uint32_t sc_tod; 96 uint32_t sc_autopoll; 97 uint32_t sc_todev; 98 /* ADB */ 99 void (*sc_adb_handler)(void *, int, uint8_t *); 100 void *sc_adb_cookie; 101 uint32_t sc_i2c_read_len; 102 /* internal buffers */ 103 uint8_t sc_in[256]; 104 uint8_t sc_out[256]; 105 }; 106 107 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc), 108 cuda_match, cuda_attach, NULL, NULL); 109 110 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 111 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 112 static void cuda_idle(struct cuda_softc *); 113 static void cuda_tip(struct cuda_softc *); 114 static void cuda_clear_tip(struct cuda_softc *); 115 static void cuda_in(struct cuda_softc *); 116 static void cuda_out(struct cuda_softc *); 117 static void cuda_toggle_ack(struct cuda_softc *); 118 static void cuda_ack_off(struct cuda_softc *); 119 static int cuda_intr_state(struct cuda_softc *); 120 121 static void cuda_init(struct cuda_softc *); 122 123 /* 124 * send a message to Cuda. 125 */ 126 /* cookie, flags, length, data */ 127 static int cuda_send(void *, int, int, uint8_t *); 128 static void cuda_poll(void *); 129 static void cuda_adb_poll(void *); 130 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 131 132 static int cuda_error_handler(void *, int, uint8_t *); 133 134 static int cuda_todr_handler(void *, int, uint8_t *); 135 static int cuda_todr_set(todr_chip_handle_t, struct timeval *); 136 static int cuda_todr_get(todr_chip_handle_t, struct timeval *); 137 138 static int cuda_adb_handler(void *, int, uint8_t *); 139 static void cuda_final(device_t); 140 141 static struct cuda_attach_args *cuda0 = NULL; 142 143 /* ADB bus attachment stuff */ 144 static int cuda_adb_send(void *, int, int, int, uint8_t *); 145 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 146 147 /* i2c stuff */ 148 static int cuda_i2c_acquire_bus(void *, int); 149 static void cuda_i2c_release_bus(void *, int); 150 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 151 void *, size_t, int); 152 153 static int 154 cuda_match(device_t parent, struct cfdata *cf, void *aux) 155 { 156 struct confargs *ca = aux; 157 158 if (ca->ca_nreg < 8) 159 return 0; 160 161 if (ca->ca_nintr < 4) 162 return 0; 163 164 if (strcmp(ca->ca_name, "via-cuda") == 0) { 165 return 10; /* beat adb* at obio? */ 166 } 167 168 return 0; 169 } 170 171 static void 172 cuda_attach(device_t parent, device_t self, void *aux) 173 { 174 struct confargs *ca = aux; 175 struct cuda_softc *sc = device_private(self); 176 struct i2cbus_attach_args iba; 177 static struct cuda_attach_args caa; 178 int irq = ca->ca_intr[0]; 179 int node, i, child; 180 char name[32]; 181 182 sc->sc_dev = self; 183 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1"); 184 if (node) 185 OF_getprop(node, "interrupts", &irq, 4); 186 187 aprint_normal(" irq %d", irq); 188 189 sc->sc_node = ca->ca_node; 190 sc->sc_memt = ca->ca_tag; 191 192 sc->sc_sent = 0; 193 sc->sc_received = 0; 194 sc->sc_waiting = 0; 195 sc->sc_polling = 0; 196 sc->sc_state = CUDA_NOTREADY; 197 sc->sc_error = 0; 198 sc->sc_i2c_read_len = 0; 199 200 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 201 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 202 203 aprint_normal(": unable to map registers\n"); 204 return; 205 } 206 sc->sc_ih = intr_establish(irq, IST_EDGE, IPL_TTY, cuda_intr, sc); 207 printf("\n"); 208 209 for (i = 0; i < 16; i++) { 210 sc->sc_handlers[i].handler = NULL; 211 sc->sc_handlers[i].cookie = NULL; 212 } 213 214 cuda_init(sc); 215 216 /* now attach children */ 217 config_interrupts(self, cuda_final); 218 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 219 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 220 221 child = OF_child(ca->ca_node); 222 while (child != 0) { 223 224 if (OF_getprop(child, "name", name, 32) == 0) 225 continue; 226 if (strncmp(name, "adb", 4) == 0) { 227 228 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 229 sc->sc_adbops.cookie = sc; 230 sc->sc_adbops.send = cuda_adb_send; 231 sc->sc_adbops.poll = cuda_adb_poll; 232 sc->sc_adbops.autopoll = cuda_autopoll; 233 sc->sc_adbops.set_handler = cuda_adb_set_handler; 234 config_found_ia(self, "adb_bus", &sc->sc_adbops, 235 nadb_print); 236 } else if (strncmp(name, "rtc", 4) == 0) { 237 238 sc->sc_todr.todr_gettime = cuda_todr_get; 239 sc->sc_todr.todr_settime = cuda_todr_set; 240 sc->sc_todr.cookie = sc; 241 todr_attach(&sc->sc_todr); 242 } 243 child = OF_peer(child); 244 } 245 246 caa.cookie = sc; 247 caa.set_handler = cuda_set_handler; 248 caa.send = cuda_send; 249 caa.poll = cuda_poll; 250 #if notyet 251 config_found(self, &caa, cuda_print); 252 #endif 253 mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE); 254 iba.iba_tag = &sc->sc_i2c; 255 sc->sc_i2c.ic_cookie = sc; 256 sc->sc_i2c.ic_acquire_bus = cuda_i2c_acquire_bus; 257 sc->sc_i2c.ic_release_bus = cuda_i2c_release_bus; 258 sc->sc_i2c.ic_send_start = NULL; 259 sc->sc_i2c.ic_send_stop = NULL; 260 sc->sc_i2c.ic_initiate_xfer = NULL; 261 sc->sc_i2c.ic_read_byte = NULL; 262 sc->sc_i2c.ic_write_byte = NULL; 263 sc->sc_i2c.ic_exec = cuda_i2c_exec; 264 config_found_ia(self, "i2cbus", &iba, iicbus_print); 265 266 if (cuda0 == NULL) 267 cuda0 = &caa; 268 } 269 270 static void 271 cuda_init(struct cuda_softc *sc) 272 { 273 uint8_t reg; 274 275 reg = cuda_read_reg(sc, vDirB); 276 reg |= 0x30; /* register B bits 4 and 5: outputs */ 277 cuda_write_reg(sc, vDirB, reg); 278 279 reg = cuda_read_reg(sc, vDirB); 280 reg &= 0xf7; /* register B bit 3: input */ 281 cuda_write_reg(sc, vDirB, reg); 282 283 reg = cuda_read_reg(sc, vACR); 284 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 285 cuda_write_reg(sc, vACR, reg); 286 287 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 288 289 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 290 291 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 292 cuda_idle(sc); /* set ADB bus state to idle */ 293 294 /* sort of a device reset */ 295 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 296 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 297 cuda_idle(sc); /* reset state to idle */ 298 delay(150); 299 cuda_tip(sc); /* signal start of frame */ 300 delay(150); 301 cuda_toggle_ack(sc); 302 delay(150); 303 cuda_clear_tip(sc); 304 delay(150); 305 cuda_idle(sc); /* back to idle state */ 306 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 307 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 308 } 309 310 static void 311 cuda_final(device_t dev) 312 { 313 struct cuda_softc *sc = device_private(dev); 314 315 sc->sc_polling = 0; 316 } 317 318 static inline void 319 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 320 { 321 322 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 323 } 324 325 static inline uint8_t 326 cuda_read_reg(struct cuda_softc *sc, int offset) 327 { 328 329 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 330 } 331 332 static int 333 cuda_set_handler(void *cookie, int type, 334 int (*handler)(void *, int, uint8_t *), void *hcookie) 335 { 336 struct cuda_softc *sc = cookie; 337 CudaHandler *me; 338 339 if ((type >= 0) && (type < 16)) { 340 me = &sc->sc_handlers[type]; 341 me->handler = handler; 342 me->cookie = hcookie; 343 return 0; 344 } 345 return -1; 346 } 347 348 static int 349 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 350 { 351 struct cuda_softc *sc = cookie; 352 int s; 353 354 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 355 if (sc->sc_state == CUDA_NOTREADY) 356 return -1; 357 358 s = splhigh(); 359 360 if (sc->sc_state == CUDA_IDLE /*&& 361 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) { 362 /* fine */ 363 DPRINTF("chip is idle\n"); 364 } else { 365 DPRINTF("cuda state is %d\n", sc->sc_state); 366 if (sc->sc_waiting == 0) { 367 sc->sc_waiting = 1; 368 } else { 369 splx(s); 370 return -1; 371 } 372 } 373 374 sc->sc_error = 0; 375 memcpy(sc->sc_out, msg, length); 376 sc->sc_out_length = length; 377 sc->sc_sent = 0; 378 379 if (sc->sc_waiting != 1) { 380 381 delay(150); 382 sc->sc_state = CUDA_OUT; 383 cuda_out(sc); 384 cuda_write_reg(sc, vSR, sc->sc_out[0]); 385 cuda_ack_off(sc); 386 cuda_tip(sc); 387 } 388 sc->sc_waiting = 1; 389 390 if (sc->sc_polling || poll || cold) { 391 cuda_poll(sc); 392 } 393 394 splx(s); 395 396 return 0; 397 } 398 399 static void 400 cuda_poll(void *cookie) 401 { 402 struct cuda_softc *sc = cookie; 403 int s; 404 405 DPRINTF("polling\n"); 406 while ((sc->sc_state != CUDA_IDLE) || 407 (cuda_intr_state(sc)) || 408 (sc->sc_waiting == 1)) { 409 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 410 s = splhigh(); 411 cuda_intr(sc); 412 splx(s); 413 } 414 } 415 } 416 417 static void 418 cuda_adb_poll(void *cookie) 419 { 420 struct cuda_softc *sc = cookie; 421 int s; 422 423 s = splhigh(); 424 cuda_intr(sc); 425 splx(s); 426 } 427 428 static void 429 cuda_idle(struct cuda_softc *sc) 430 { 431 uint8_t reg; 432 433 reg = cuda_read_reg(sc, vBufB); 434 reg |= (vPB4 | vPB5); 435 cuda_write_reg(sc, vBufB, reg); 436 } 437 438 static void 439 cuda_tip(struct cuda_softc *sc) 440 { 441 uint8_t reg; 442 443 reg = cuda_read_reg(sc, vBufB); 444 reg &= ~vPB5; 445 cuda_write_reg(sc, vBufB, reg); 446 } 447 448 static void 449 cuda_clear_tip(struct cuda_softc *sc) 450 { 451 uint8_t reg; 452 453 reg = cuda_read_reg(sc, vBufB); 454 reg |= vPB5; 455 cuda_write_reg(sc, vBufB, reg); 456 } 457 458 static void 459 cuda_in(struct cuda_softc *sc) 460 { 461 uint8_t reg; 462 463 reg = cuda_read_reg(sc, vACR); 464 reg &= ~vSR_OUT; 465 cuda_write_reg(sc, vACR, reg); 466 } 467 468 static void 469 cuda_out(struct cuda_softc *sc) 470 { 471 uint8_t reg; 472 473 reg = cuda_read_reg(sc, vACR); 474 reg |= vSR_OUT; 475 cuda_write_reg(sc, vACR, reg); 476 } 477 478 static void 479 cuda_toggle_ack(struct cuda_softc *sc) 480 { 481 uint8_t reg; 482 483 reg = cuda_read_reg(sc, vBufB); 484 reg ^= vPB4; 485 cuda_write_reg(sc, vBufB, reg); 486 } 487 488 static void 489 cuda_ack_off(struct cuda_softc *sc) 490 { 491 uint8_t reg; 492 493 reg = cuda_read_reg(sc, vBufB); 494 reg |= vPB4; 495 cuda_write_reg(sc, vBufB, reg); 496 } 497 498 static int 499 cuda_intr_state(struct cuda_softc *sc) 500 { 501 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 502 } 503 504 static int 505 cuda_intr(void *arg) 506 { 507 struct cuda_softc *sc = arg; 508 int ending, type; 509 uint8_t reg; 510 511 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 512 DPRINTF("["); 513 if ((reg & 0x80) == 0) { 514 DPRINTF("irq %02x]", reg); 515 return 0; /* No interrupts to process */ 516 } 517 DPRINTF(":"); 518 519 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 520 521 switch_start: 522 switch (sc->sc_state) { 523 case CUDA_IDLE: 524 /* 525 * This is an unexpected packet, so grab the first (dummy) 526 * byte, set up the proper vars, and tell the chip we are 527 * starting to receive the packet by setting the TIP bit. 528 */ 529 sc->sc_in[1] = cuda_read_reg(sc, vSR); 530 DPRINTF("start: %02x", sc->sc_in[1]); 531 if (cuda_intr_state(sc) == 0) { 532 /* must have been a fake start */ 533 DPRINTF(" ... fake start\n"); 534 if (sc->sc_waiting) { 535 /* start over */ 536 delay(150); 537 sc->sc_state = CUDA_OUT; 538 sc->sc_sent = 0; 539 cuda_out(sc); 540 cuda_write_reg(sc, vSR, sc->sc_out[1]); 541 cuda_ack_off(sc); 542 cuda_tip(sc); 543 } 544 break; 545 } 546 547 cuda_in(sc); 548 cuda_tip(sc); 549 550 sc->sc_received = 1; 551 sc->sc_state = CUDA_IN; 552 DPRINTF(" CUDA_IN"); 553 break; 554 555 case CUDA_IN: 556 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 557 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 558 ending = 0; 559 if (sc->sc_received > 255) { 560 /* bitch only once */ 561 if (sc->sc_received == 256) { 562 aprint_error_dev(sc->sc_dev, 563 "input overflow\n"); 564 ending = 1; 565 } 566 } else 567 sc->sc_received++; 568 if (sc->sc_received > 3) { 569 if ((sc->sc_in[3] == CMD_IIC) && 570 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 571 ending = 1; 572 } 573 } 574 575 /* intr off means this is the last byte (end of frame) */ 576 if (cuda_intr_state(sc) == 0) { 577 ending = 1; 578 DPRINTF(".\n"); 579 } else { 580 cuda_toggle_ack(sc); 581 } 582 583 if (ending == 1) { /* end of message? */ 584 585 sc->sc_in[0] = sc->sc_received - 1; 586 587 /* reset vars and signal the end of this frame */ 588 cuda_idle(sc); 589 590 /* check if we have a handler for this message */ 591 type = sc->sc_in[1]; 592 if ((type >= 0) && (type < 16)) { 593 CudaHandler *me = &sc->sc_handlers[type]; 594 595 if (me->handler != NULL) { 596 me->handler(me->cookie, 597 sc->sc_received - 1, &sc->sc_in[1]); 598 } else { 599 aprint_error_dev(sc->sc_dev, 600 "no handler for type %02x\n", type); 601 panic("barf"); 602 } 603 } 604 605 DPRINTF("CUDA_IDLE"); 606 sc->sc_state = CUDA_IDLE; 607 608 sc->sc_received = 0; 609 610 /* 611 * If there is something waiting to be sent out, 612 * set everything up and send the first byte. 613 */ 614 if (sc->sc_waiting == 1) { 615 616 DPRINTF("pending write\n"); 617 delay(1500); /* required */ 618 sc->sc_sent = 0; 619 sc->sc_state = CUDA_OUT; 620 621 /* 622 * If the interrupt is on, we were too slow 623 * and the chip has already started to send 624 * something to us, so back out of the write 625 * and start a read cycle. 626 */ 627 if (cuda_intr_state(sc)) { 628 cuda_in(sc); 629 cuda_idle(sc); 630 sc->sc_sent = 0; 631 sc->sc_state = CUDA_IDLE; 632 sc->sc_received = 0; 633 delay(150); 634 DPRINTF("too slow - incoming message\n"); 635 goto switch_start; 636 } 637 /* 638 * If we got here, it's ok to start sending 639 * so load the first byte and tell the chip 640 * we want to send. 641 */ 642 DPRINTF("sending "); 643 644 cuda_out(sc); 645 cuda_write_reg(sc, vSR, 646 sc->sc_out[sc->sc_sent]); 647 cuda_ack_off(sc); 648 cuda_tip(sc); 649 } 650 } 651 break; 652 653 case CUDA_OUT: 654 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 655 656 sc->sc_sent++; 657 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 658 659 DPRINTF("incoming msg during send\n"); 660 cuda_in(sc); /* make sure SR is set to IN */ 661 cuda_idle(sc); 662 sc->sc_sent = 0; /* must start all over */ 663 sc->sc_state = CUDA_IDLE; /* new state */ 664 sc->sc_received = 0; 665 sc->sc_waiting = 1; /* must retry when done with 666 * read */ 667 delay(150); 668 goto switch_start; /* process next state right 669 * now */ 670 break; 671 } 672 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 673 674 sc->sc_waiting = 0; /* done writing */ 675 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 676 cuda_in(sc); 677 cuda_idle(sc); 678 DPRINTF("done sending\n"); 679 } else { 680 /* send next byte */ 681 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 682 DPRINTF("%02x", sc->sc_out[sc->sc_sent]); 683 cuda_toggle_ack(sc); /* signal byte ready to 684 * shift */ 685 } 686 break; 687 688 case CUDA_NOTREADY: 689 DPRINTF("adb: not yet initialized\n"); 690 break; 691 692 default: 693 DPRINTF("intr: unknown ADB state\n"); 694 break; 695 } 696 697 DPRINTF("]"); 698 return 1; 699 } 700 701 static int 702 cuda_error_handler(void *cookie, int len, uint8_t *data) 703 { 704 struct cuda_softc *sc = cookie; 705 706 /* 707 * something went wrong 708 * byte 3 seems to be the failed command 709 */ 710 sc->sc_error = 1; 711 wakeup(&sc->sc_todev); 712 return 0; 713 } 714 715 716 /* real time clock */ 717 718 static int 719 cuda_todr_handler(void *cookie, int len, uint8_t *data) 720 { 721 struct cuda_softc *sc = cookie; 722 723 #ifdef CUDA_DEBUG 724 int i; 725 printf("msg: %02x", data[0]); 726 for (i = 1; i < len; i++) { 727 printf(" %02x", data[i]); 728 } 729 printf("\n"); 730 #endif 731 732 switch(data[2]) { 733 case CMD_READ_RTC: 734 memcpy(&sc->sc_tod, &data[3], 4); 735 break; 736 case CMD_WRITE_RTC: 737 sc->sc_tod = 0xffffffff; 738 break; 739 case CMD_AUTOPOLL: 740 sc->sc_autopoll = 1; 741 break; 742 case CMD_IIC: 743 sc->sc_iic_done = len; 744 break; 745 } 746 wakeup(&sc->sc_todev); 747 return 0; 748 } 749 750 #define DIFF19041970 2082844800 751 752 static int 753 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp) 754 { 755 struct cuda_softc *sc = tch->cookie; 756 int cnt = 0; 757 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 758 759 sc->sc_tod = 0; 760 while (sc->sc_tod == 0) { 761 cuda_send(sc, 0, 2, cmd); 762 763 while ((sc->sc_tod == 0) && (cnt < 10)) { 764 tsleep(&sc->sc_todev, 0, "todr", 10); 765 cnt++; 766 } 767 768 if (sc->sc_tod == 0) { 769 aprint_error_dev(sc->sc_dev, 770 "unable to read a sane RTC value\n"); 771 return EIO; 772 } 773 if ((sc->sc_tod > 0xf0000000UL) || 774 (sc->sc_tod < DIFF19041970)) { 775 /* huh? try again */ 776 sc->sc_tod = 0; 777 aprint_verbose_dev(sc->sc_dev, 778 "got garbage reading RTC, trying again\n"); 779 } 780 } 781 782 tvp->tv_sec = sc->sc_tod - DIFF19041970; 783 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec); 784 tvp->tv_usec = 0; 785 return 0; 786 } 787 788 static int 789 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp) 790 { 791 struct cuda_softc *sc = tch->cookie; 792 uint32_t sec; 793 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 794 795 sec = tvp->tv_sec + DIFF19041970; 796 memcpy(&cmd[2], &sec, 4); 797 sc->sc_tod = 0; 798 if (cuda_send(sc, 0, 6, cmd) == 0) { 799 while (sc->sc_tod == 0) { 800 tsleep(&sc->sc_todev, 0, "todr", 10); 801 } 802 return 0; 803 } 804 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__); 805 return -1; 806 807 } 808 809 /* poweroff and reboot */ 810 811 void 812 cuda_poweroff(void) 813 { 814 struct cuda_softc *sc; 815 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 816 817 if (cuda0 == NULL) 818 return; 819 sc = cuda0->cookie; 820 sc->sc_polling = 1; 821 cuda0->poll(sc); 822 if (cuda0->send(sc, 1, 2, cmd) == 0) 823 while (1); 824 } 825 826 void 827 cuda_restart(void) 828 { 829 struct cuda_softc *sc; 830 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 831 832 if (cuda0 == NULL) 833 return; 834 sc = cuda0->cookie; 835 sc->sc_polling = 1; 836 cuda0->poll(sc); 837 if (cuda0->send(sc, 1, 2, cmd) == 0) 838 while (1); 839 } 840 841 /* ADB message handling */ 842 843 static void 844 cuda_autopoll(void *cookie, int flag) 845 { 846 struct cuda_softc *sc = cookie; 847 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 848 849 if (cmd[2] == sc->sc_autopoll) 850 return; 851 852 sc->sc_autopoll = -1; 853 cuda_send(sc, 0, 3, cmd); 854 while(sc->sc_autopoll == -1) { 855 if (sc->sc_polling || cold) { 856 cuda_poll(sc); 857 } else 858 tsleep(&sc->sc_todev, 0, "autopoll", 100); 859 } 860 } 861 862 static int 863 cuda_adb_handler(void *cookie, int len, uint8_t *data) 864 { 865 struct cuda_softc *sc = cookie; 866 867 if (sc->sc_adb_handler != NULL) { 868 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 869 &data[1]); 870 return 0; 871 } 872 return -1; 873 } 874 875 static int 876 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 877 { 878 struct cuda_softc *sc = cookie; 879 int i, s = 0; 880 uint8_t packet[16]; 881 882 /* construct an ADB command packet and send it */ 883 packet[0] = CUDA_ADB; 884 packet[1] = command; 885 for (i = 0; i < len; i++) 886 packet[i + 2] = data[i]; 887 if (poll || cold) { 888 s = splhigh(); 889 cuda_poll(sc); 890 } 891 cuda_send(sc, poll, len + 2, packet); 892 if (poll || cold) { 893 cuda_poll(sc); 894 splx(s); 895 } 896 return 0; 897 } 898 899 static int 900 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 901 void *hcookie) 902 { 903 struct cuda_softc *sc = cookie; 904 905 /* register a callback for incoming ADB messages */ 906 sc->sc_adb_handler = handler; 907 sc->sc_adb_cookie = hcookie; 908 return 0; 909 } 910 911 /* i2c message handling */ 912 913 static int 914 cuda_i2c_acquire_bus(void *cookie, int flags) 915 { 916 struct cuda_softc *sc = cookie; 917 918 mutex_enter(&sc->sc_buslock); 919 return 0; 920 } 921 922 static void 923 cuda_i2c_release_bus(void *cookie, int flags) 924 { 925 struct cuda_softc *sc = cookie; 926 927 mutex_exit(&sc->sc_buslock); 928 } 929 930 static int 931 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 932 size_t send_len, void *_recv, size_t recv_len, int flags) 933 { 934 struct cuda_softc *sc = cookie; 935 const uint8_t *send = _send; 936 uint8_t *recv = _recv; 937 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 938 939 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 940 command[2] = addr; 941 942 /* Copy command and output data bytes, if any, to buffer */ 943 if (send_len > 0) 944 memcpy(&command[3], send, min((int)send_len, 12)); 945 else if (I2C_OP_READ_P(op) && (recv_len == 0)) { 946 /* 947 * If no data bytes in either direction, it's a "quick" 948 * i2c operation. We don't know how to do a quick_read 949 * since that requires us to set the low bit of the 950 * address byte after it has been left-shifted. 951 */ 952 sc->sc_error = 0; 953 return -1; 954 } 955 956 sc->sc_iic_done = 0; 957 cuda_send(sc, sc->sc_polling, send_len + 3, command); 958 959 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 960 if (sc->sc_polling || cold) { 961 cuda_poll(sc); 962 } else 963 tsleep(&sc->sc_todev, 0, "i2c", 1000); 964 } 965 966 if (sc->sc_error) { 967 sc->sc_error = 0; 968 aprint_error_dev(sc->sc_dev, "error doing I2C\n"); 969 return -1; 970 } 971 972 /* see if we're supposed to do a read */ 973 if (recv_len > 0) { 974 sc->sc_iic_done = 0; 975 command[2] |= 1; 976 command[3] = 0; 977 978 /* 979 * XXX we need to do something to limit the size of the answer 980 * - apparently the chip keeps sending until we tell it to stop 981 */ 982 sc->sc_i2c_read_len = recv_len; 983 DPRINTF("rcv_len: %d\n", recv_len); 984 cuda_send(sc, sc->sc_polling, 3, command); 985 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 986 if (sc->sc_polling || cold) { 987 cuda_poll(sc); 988 } else 989 tsleep(&sc->sc_todev, 0, "i2c", 1000); 990 } 991 992 if (sc->sc_error) { 993 aprint_error_dev(sc->sc_dev, 994 "error trying to read from I2C\n"); 995 sc->sc_error = 0; 996 return -1; 997 } 998 } 999 1000 DPRINTF("received: %d\n", sc->sc_iic_done); 1001 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 1002 int rlen; 1003 1004 /* we got an answer */ 1005 rlen = min(sc->sc_iic_done - 3, recv_len); 1006 memcpy(recv, &sc->sc_in[4], rlen); 1007 #ifdef CUDA_DEBUG 1008 { 1009 int i; 1010 printf("ret:"); 1011 for (i = 0; i < rlen; i++) 1012 printf(" %02x", recv[i]); 1013 printf("\n"); 1014 } 1015 #endif 1016 return rlen; 1017 } 1018 return 0; 1019 } 1020
Indexes created Thu Sep 25 16:09:42 GMT 2025