cuda.c revision 1.22
1 /* $NetBSD: cuda.c,v 1.22 2017/09/22 04:00:58 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.22 2017/09/22 04:00:58 macallan Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/mutex.h> 38 39 #include <sys/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 #include <dev/clock_subr.h> 43 #include <dev/i2c/i2cvar.h> 44 45 #include <macppc/dev/viareg.h> 46 #include <macppc/dev/cudavar.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/adb/adbvar.h> 50 #include "opt_cuda.h" 51 52 #ifdef CUDA_DEBUG 53 #define DPRINTF printf 54 #else 55 #define DPRINTF while (0) printf 56 #endif 57 58 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 59 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 60 #define CUDA_OUT 0x3 /* sending out a command */ 61 #define CUDA_IN 0x4 /* receiving data */ 62 #define CUDA_POLLING 0x5 /* polling - II only */ 63 64 static void cuda_attach(device_t, device_t, void *); 65 static int cuda_match(device_t, struct cfdata *, void *); 66 static void cuda_autopoll(void *, int); 67 68 static int cuda_intr(void *); 69 70 typedef struct _cuda_handler { 71 int (*handler)(void *, int, uint8_t *); 72 void *cookie; 73 } CudaHandler; 74 75 struct cuda_softc { 76 device_t sc_dev; 77 void *sc_ih; 78 CudaHandler sc_handlers[16]; 79 struct todr_chip_handle sc_todr; 80 struct adb_bus_accessops sc_adbops; 81 struct i2c_controller sc_i2c; 82 kmutex_t sc_buslock; 83 bus_space_tag_t sc_memt; 84 bus_space_handle_t sc_memh; 85 int sc_node; 86 int sc_state; 87 int sc_waiting; 88 int sc_polling; 89 int sc_sent; 90 int sc_out_length; 91 int sc_received; 92 int sc_iic_done; 93 int sc_error; 94 /* time */ 95 uint32_t sc_tod; 96 uint32_t sc_autopoll; 97 uint32_t sc_todev; 98 /* ADB */ 99 void (*sc_adb_handler)(void *, int, uint8_t *); 100 void *sc_adb_cookie; 101 uint32_t sc_i2c_read_len; 102 /* internal buffers */ 103 uint8_t sc_in[256]; 104 uint8_t sc_out[256]; 105 }; 106 107 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc), 108 cuda_match, cuda_attach, NULL, NULL); 109 110 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 111 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 112 static void cuda_idle(struct cuda_softc *); 113 static void cuda_tip(struct cuda_softc *); 114 static void cuda_clear_tip(struct cuda_softc *); 115 static void cuda_in(struct cuda_softc *); 116 static void cuda_out(struct cuda_softc *); 117 static void cuda_toggle_ack(struct cuda_softc *); 118 static void cuda_ack_off(struct cuda_softc *); 119 static int cuda_intr_state(struct cuda_softc *); 120 121 static void cuda_init(struct cuda_softc *); 122 123 /* 124 * send a message to Cuda. 125 */ 126 /* cookie, flags, length, data */ 127 static int cuda_send(void *, int, int, uint8_t *); 128 static void cuda_poll(void *); 129 static void cuda_adb_poll(void *); 130 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 131 132 static int cuda_error_handler(void *, int, uint8_t *); 133 134 static int cuda_todr_handler(void *, int, uint8_t *); 135 static int cuda_todr_set(todr_chip_handle_t, struct timeval *); 136 static int cuda_todr_get(todr_chip_handle_t, struct timeval *); 137 138 static int cuda_adb_handler(void *, int, uint8_t *); 139 static void cuda_final(device_t); 140 141 static struct cuda_attach_args *cuda0 = NULL; 142 143 /* ADB bus attachment stuff */ 144 static int cuda_adb_send(void *, int, int, int, uint8_t *); 145 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 146 147 /* i2c stuff */ 148 static int cuda_i2c_acquire_bus(void *, int); 149 static void cuda_i2c_release_bus(void *, int); 150 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 151 void *, size_t, int); 152 153 static int 154 cuda_match(device_t parent, struct cfdata *cf, void *aux) 155 { 156 struct confargs *ca = aux; 157 158 if (ca->ca_nreg < 8) 159 return 0; 160 161 if (ca->ca_nintr < 4) 162 return 0; 163 164 if (strcmp(ca->ca_name, "via-cuda") == 0) { 165 return 10; /* beat adb* at obio? */ 166 } 167 168 return 0; 169 } 170 171 static void 172 cuda_attach(device_t parent, device_t self, void *aux) 173 { 174 struct confargs *ca = aux; 175 struct cuda_softc *sc = device_private(self); 176 struct i2cbus_attach_args iba; 177 static struct cuda_attach_args caa; 178 prop_dictionary_t dict = device_properties(self); 179 prop_dictionary_t dev; 180 prop_array_t cfg; 181 int irq = ca->ca_intr[0]; 182 int node, i, child; 183 char name[32]; 184 185 sc->sc_dev = self; 186 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1"); 187 if (node) 188 OF_getprop(node, "interrupts", &irq, 4); 189 190 aprint_normal(" irq %d", irq); 191 192 sc->sc_node = ca->ca_node; 193 sc->sc_memt = ca->ca_tag; 194 195 sc->sc_sent = 0; 196 sc->sc_received = 0; 197 sc->sc_waiting = 0; 198 sc->sc_polling = 0; 199 sc->sc_state = CUDA_NOTREADY; 200 sc->sc_error = 0; 201 sc->sc_i2c_read_len = 0; 202 203 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 204 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 205 206 aprint_normal(": unable to map registers\n"); 207 return; 208 } 209 sc->sc_ih = intr_establish(irq, IST_EDGE, IPL_TTY, cuda_intr, sc); 210 printf("\n"); 211 212 for (i = 0; i < 16; i++) { 213 sc->sc_handlers[i].handler = NULL; 214 sc->sc_handlers[i].cookie = NULL; 215 } 216 217 cuda_init(sc); 218 219 /* now attach children */ 220 config_interrupts(self, cuda_final); 221 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 222 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 223 224 child = OF_child(ca->ca_node); 225 while (child != 0) { 226 227 if (OF_getprop(child, "name", name, 32) == 0) 228 continue; 229 if (strncmp(name, "adb", 4) == 0) { 230 231 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 232 sc->sc_adbops.cookie = sc; 233 sc->sc_adbops.send = cuda_adb_send; 234 sc->sc_adbops.poll = cuda_adb_poll; 235 sc->sc_adbops.autopoll = cuda_autopoll; 236 sc->sc_adbops.set_handler = cuda_adb_set_handler; 237 config_found_ia(self, "adb_bus", &sc->sc_adbops, 238 nadb_print); 239 } else if (strncmp(name, "rtc", 4) == 0) { 240 241 sc->sc_todr.todr_gettime = cuda_todr_get; 242 sc->sc_todr.todr_settime = cuda_todr_set; 243 sc->sc_todr.cookie = sc; 244 todr_attach(&sc->sc_todr); 245 } 246 child = OF_peer(child); 247 } 248 249 caa.cookie = sc; 250 caa.set_handler = cuda_set_handler; 251 caa.send = cuda_send; 252 caa.poll = cuda_poll; 253 #if notyet 254 config_found(self, &caa, cuda_print); 255 #endif 256 cfg = prop_array_create(); 257 prop_dictionary_set(dict, "i2c-child-devices", cfg); 258 prop_object_release(cfg); 259 260 /* we don't have OF nodes for i2c devices so we have to make our own */ 261 262 node = OF_finddevice("/valkyrie"); 263 if (node != -1) { 264 dev = prop_dictionary_create(); 265 prop_dictionary_set_cstring(dev, "name", "videopll"); 266 prop_dictionary_set_uint32(dev, "addr", 0x50); 267 prop_array_add(cfg, dev); 268 prop_object_release(dev); 269 } 270 271 node = OF_finddevice("/perch"); 272 if (node != -1) { 273 dev = prop_dictionary_create(); 274 prop_dictionary_set_cstring(dev, "name", "sgsmix"); 275 prop_dictionary_set_uint32(dev, "addr", 0x8a); 276 prop_array_add(cfg, dev); 277 prop_object_release(dev); 278 } 279 280 mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE); 281 memset(&iba, 0, sizeof(iba)); 282 iba.iba_tag = &sc->sc_i2c; 283 sc->sc_i2c.ic_cookie = sc; 284 sc->sc_i2c.ic_acquire_bus = cuda_i2c_acquire_bus; 285 sc->sc_i2c.ic_release_bus = cuda_i2c_release_bus; 286 sc->sc_i2c.ic_send_start = NULL; 287 sc->sc_i2c.ic_send_stop = NULL; 288 sc->sc_i2c.ic_initiate_xfer = NULL; 289 sc->sc_i2c.ic_read_byte = NULL; 290 sc->sc_i2c.ic_write_byte = NULL; 291 sc->sc_i2c.ic_exec = cuda_i2c_exec; 292 config_found_ia(self, "i2cbus", &iba, iicbus_print); 293 294 if (cuda0 == NULL) 295 cuda0 = &caa; 296 } 297 298 static void 299 cuda_init(struct cuda_softc *sc) 300 { 301 uint8_t reg; 302 303 reg = cuda_read_reg(sc, vDirB); 304 reg |= 0x30; /* register B bits 4 and 5: outputs */ 305 cuda_write_reg(sc, vDirB, reg); 306 307 reg = cuda_read_reg(sc, vDirB); 308 reg &= 0xf7; /* register B bit 3: input */ 309 cuda_write_reg(sc, vDirB, reg); 310 311 reg = cuda_read_reg(sc, vACR); 312 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 313 cuda_write_reg(sc, vACR, reg); 314 315 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 316 317 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 318 319 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 320 cuda_idle(sc); /* set ADB bus state to idle */ 321 322 /* sort of a device reset */ 323 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 324 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 325 cuda_idle(sc); /* reset state to idle */ 326 delay(150); 327 cuda_tip(sc); /* signal start of frame */ 328 delay(150); 329 cuda_toggle_ack(sc); 330 delay(150); 331 cuda_clear_tip(sc); 332 delay(150); 333 cuda_idle(sc); /* back to idle state */ 334 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 335 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 336 } 337 338 static void 339 cuda_final(device_t dev) 340 { 341 struct cuda_softc *sc = device_private(dev); 342 343 sc->sc_polling = 0; 344 } 345 346 static inline void 347 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 348 { 349 350 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 351 } 352 353 static inline uint8_t 354 cuda_read_reg(struct cuda_softc *sc, int offset) 355 { 356 357 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 358 } 359 360 static int 361 cuda_set_handler(void *cookie, int type, 362 int (*handler)(void *, int, uint8_t *), void *hcookie) 363 { 364 struct cuda_softc *sc = cookie; 365 CudaHandler *me; 366 367 if ((type >= 0) && (type < 16)) { 368 me = &sc->sc_handlers[type]; 369 me->handler = handler; 370 me->cookie = hcookie; 371 return 0; 372 } 373 return -1; 374 } 375 376 static int 377 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 378 { 379 struct cuda_softc *sc = cookie; 380 int s; 381 382 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 383 if (sc->sc_state == CUDA_NOTREADY) 384 return -1; 385 386 s = splhigh(); 387 388 if (sc->sc_state == CUDA_IDLE /*&& 389 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) { 390 /* fine */ 391 DPRINTF("chip is idle\n"); 392 } else { 393 DPRINTF("cuda state is %d\n", sc->sc_state); 394 if (sc->sc_waiting == 0) { 395 sc->sc_waiting = 1; 396 } else { 397 splx(s); 398 return -1; 399 } 400 } 401 402 sc->sc_error = 0; 403 memcpy(sc->sc_out, msg, length); 404 sc->sc_out_length = length; 405 sc->sc_sent = 0; 406 407 if (sc->sc_waiting != 1) { 408 409 delay(150); 410 sc->sc_state = CUDA_OUT; 411 cuda_out(sc); 412 cuda_write_reg(sc, vSR, sc->sc_out[0]); 413 cuda_ack_off(sc); 414 cuda_tip(sc); 415 } 416 sc->sc_waiting = 1; 417 418 if (sc->sc_polling || poll || cold) { 419 cuda_poll(sc); 420 } 421 422 splx(s); 423 424 return 0; 425 } 426 427 static void 428 cuda_poll(void *cookie) 429 { 430 struct cuda_softc *sc = cookie; 431 int s; 432 433 DPRINTF("polling\n"); 434 while ((sc->sc_state != CUDA_IDLE) || 435 (cuda_intr_state(sc)) || 436 (sc->sc_waiting == 1)) { 437 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 438 s = splhigh(); 439 cuda_intr(sc); 440 splx(s); 441 } 442 } 443 } 444 445 static void 446 cuda_adb_poll(void *cookie) 447 { 448 struct cuda_softc *sc = cookie; 449 int s; 450 451 s = splhigh(); 452 cuda_intr(sc); 453 splx(s); 454 } 455 456 static void 457 cuda_idle(struct cuda_softc *sc) 458 { 459 uint8_t reg; 460 461 reg = cuda_read_reg(sc, vBufB); 462 reg |= (vPB4 | vPB5); 463 cuda_write_reg(sc, vBufB, reg); 464 } 465 466 static void 467 cuda_tip(struct cuda_softc *sc) 468 { 469 uint8_t reg; 470 471 reg = cuda_read_reg(sc, vBufB); 472 reg &= ~vPB5; 473 cuda_write_reg(sc, vBufB, reg); 474 } 475 476 static void 477 cuda_clear_tip(struct cuda_softc *sc) 478 { 479 uint8_t reg; 480 481 reg = cuda_read_reg(sc, vBufB); 482 reg |= vPB5; 483 cuda_write_reg(sc, vBufB, reg); 484 } 485 486 static void 487 cuda_in(struct cuda_softc *sc) 488 { 489 uint8_t reg; 490 491 reg = cuda_read_reg(sc, vACR); 492 reg &= ~vSR_OUT; 493 cuda_write_reg(sc, vACR, reg); 494 } 495 496 static void 497 cuda_out(struct cuda_softc *sc) 498 { 499 uint8_t reg; 500 501 reg = cuda_read_reg(sc, vACR); 502 reg |= vSR_OUT; 503 cuda_write_reg(sc, vACR, reg); 504 } 505 506 static void 507 cuda_toggle_ack(struct cuda_softc *sc) 508 { 509 uint8_t reg; 510 511 reg = cuda_read_reg(sc, vBufB); 512 reg ^= vPB4; 513 cuda_write_reg(sc, vBufB, reg); 514 } 515 516 static void 517 cuda_ack_off(struct cuda_softc *sc) 518 { 519 uint8_t reg; 520 521 reg = cuda_read_reg(sc, vBufB); 522 reg |= vPB4; 523 cuda_write_reg(sc, vBufB, reg); 524 } 525 526 static int 527 cuda_intr_state(struct cuda_softc *sc) 528 { 529 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 530 } 531 532 static int 533 cuda_intr(void *arg) 534 { 535 struct cuda_softc *sc = arg; 536 int ending, type; 537 uint8_t reg; 538 539 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 540 DPRINTF("["); 541 if ((reg & 0x80) == 0) { 542 DPRINTF("irq %02x]", reg); 543 return 0; /* No interrupts to process */ 544 } 545 DPRINTF(":"); 546 547 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 548 549 switch_start: 550 switch (sc->sc_state) { 551 case CUDA_IDLE: 552 /* 553 * This is an unexpected packet, so grab the first (dummy) 554 * byte, set up the proper vars, and tell the chip we are 555 * starting to receive the packet by setting the TIP bit. 556 */ 557 sc->sc_in[1] = cuda_read_reg(sc, vSR); 558 DPRINTF("start: %02x", sc->sc_in[1]); 559 if (cuda_intr_state(sc) == 0) { 560 /* must have been a fake start */ 561 DPRINTF(" ... fake start\n"); 562 if (sc->sc_waiting) { 563 /* start over */ 564 delay(150); 565 sc->sc_state = CUDA_OUT; 566 sc->sc_sent = 0; 567 cuda_out(sc); 568 cuda_write_reg(sc, vSR, sc->sc_out[1]); 569 cuda_ack_off(sc); 570 cuda_tip(sc); 571 } 572 break; 573 } 574 575 cuda_in(sc); 576 cuda_tip(sc); 577 578 sc->sc_received = 1; 579 sc->sc_state = CUDA_IN; 580 DPRINTF(" CUDA_IN"); 581 break; 582 583 case CUDA_IN: 584 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 585 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 586 ending = 0; 587 if (sc->sc_received > 255) { 588 /* bitch only once */ 589 if (sc->sc_received == 256) { 590 aprint_error_dev(sc->sc_dev, 591 "input overflow\n"); 592 ending = 1; 593 } 594 } else 595 sc->sc_received++; 596 if (sc->sc_received > 3) { 597 if ((sc->sc_in[3] == CMD_IIC) && 598 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 599 ending = 1; 600 } 601 } 602 603 /* intr off means this is the last byte (end of frame) */ 604 if (cuda_intr_state(sc) == 0) { 605 ending = 1; 606 DPRINTF(".\n"); 607 } else { 608 cuda_toggle_ack(sc); 609 } 610 611 if (ending == 1) { /* end of message? */ 612 613 sc->sc_in[0] = sc->sc_received - 1; 614 615 /* reset vars and signal the end of this frame */ 616 cuda_idle(sc); 617 618 /* check if we have a handler for this message */ 619 type = sc->sc_in[1]; 620 if ((type >= 0) && (type < 16)) { 621 CudaHandler *me = &sc->sc_handlers[type]; 622 623 if (me->handler != NULL) { 624 me->handler(me->cookie, 625 sc->sc_received - 1, &sc->sc_in[1]); 626 } else { 627 aprint_error_dev(sc->sc_dev, 628 "no handler for type %02x\n", type); 629 panic("barf"); 630 } 631 } 632 633 DPRINTF("CUDA_IDLE"); 634 sc->sc_state = CUDA_IDLE; 635 636 sc->sc_received = 0; 637 638 /* 639 * If there is something waiting to be sent out, 640 * set everything up and send the first byte. 641 */ 642 if (sc->sc_waiting == 1) { 643 644 DPRINTF("pending write\n"); 645 delay(1500); /* required */ 646 sc->sc_sent = 0; 647 sc->sc_state = CUDA_OUT; 648 649 /* 650 * If the interrupt is on, we were too slow 651 * and the chip has already started to send 652 * something to us, so back out of the write 653 * and start a read cycle. 654 */ 655 if (cuda_intr_state(sc)) { 656 cuda_in(sc); 657 cuda_idle(sc); 658 sc->sc_sent = 0; 659 sc->sc_state = CUDA_IDLE; 660 sc->sc_received = 0; 661 delay(150); 662 DPRINTF("too slow - incoming message\n"); 663 goto switch_start; 664 } 665 /* 666 * If we got here, it's ok to start sending 667 * so load the first byte and tell the chip 668 * we want to send. 669 */ 670 DPRINTF("sending "); 671 672 cuda_out(sc); 673 cuda_write_reg(sc, vSR, 674 sc->sc_out[sc->sc_sent]); 675 cuda_ack_off(sc); 676 cuda_tip(sc); 677 } 678 } 679 break; 680 681 case CUDA_OUT: 682 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 683 684 sc->sc_sent++; 685 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 686 687 DPRINTF("incoming msg during send\n"); 688 cuda_in(sc); /* make sure SR is set to IN */ 689 cuda_idle(sc); 690 sc->sc_sent = 0; /* must start all over */ 691 sc->sc_state = CUDA_IDLE; /* new state */ 692 sc->sc_received = 0; 693 sc->sc_waiting = 1; /* must retry when done with 694 * read */ 695 delay(150); 696 goto switch_start; /* process next state right 697 * now */ 698 break; 699 } 700 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 701 702 sc->sc_waiting = 0; /* done writing */ 703 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 704 cuda_in(sc); 705 cuda_idle(sc); 706 DPRINTF("done sending\n"); 707 } else { 708 /* send next byte */ 709 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 710 DPRINTF("%02x", sc->sc_out[sc->sc_sent]); 711 cuda_toggle_ack(sc); /* signal byte ready to 712 * shift */ 713 } 714 break; 715 716 case CUDA_NOTREADY: 717 DPRINTF("adb: not yet initialized\n"); 718 break; 719 720 default: 721 DPRINTF("intr: unknown ADB state\n"); 722 break; 723 } 724 725 DPRINTF("]"); 726 return 1; 727 } 728 729 static int 730 cuda_error_handler(void *cookie, int len, uint8_t *data) 731 { 732 struct cuda_softc *sc = cookie; 733 734 /* 735 * something went wrong 736 * byte 3 seems to be the failed command 737 */ 738 sc->sc_error = 1; 739 wakeup(&sc->sc_todev); 740 return 0; 741 } 742 743 744 /* real time clock */ 745 746 static int 747 cuda_todr_handler(void *cookie, int len, uint8_t *data) 748 { 749 struct cuda_softc *sc = cookie; 750 751 #ifdef CUDA_DEBUG 752 int i; 753 printf("msg: %02x", data[0]); 754 for (i = 1; i < len; i++) { 755 printf(" %02x", data[i]); 756 } 757 printf("\n"); 758 #endif 759 760 switch(data[2]) { 761 case CMD_READ_RTC: 762 memcpy(&sc->sc_tod, &data[3], 4); 763 break; 764 case CMD_WRITE_RTC: 765 sc->sc_tod = 0xffffffff; 766 break; 767 case CMD_AUTOPOLL: 768 sc->sc_autopoll = 1; 769 break; 770 case CMD_IIC: 771 sc->sc_iic_done = len; 772 break; 773 } 774 wakeup(&sc->sc_todev); 775 return 0; 776 } 777 778 #define DIFF19041970 2082844800 779 780 static int 781 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp) 782 { 783 struct cuda_softc *sc = tch->cookie; 784 int cnt = 0; 785 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 786 787 sc->sc_tod = 0; 788 while (sc->sc_tod == 0) { 789 cuda_send(sc, 0, 2, cmd); 790 791 while ((sc->sc_tod == 0) && (cnt < 10)) { 792 tsleep(&sc->sc_todev, 0, "todr", 10); 793 cnt++; 794 } 795 796 if (sc->sc_tod == 0) { 797 aprint_error_dev(sc->sc_dev, 798 "unable to read a sane RTC value\n"); 799 return EIO; 800 } 801 if ((sc->sc_tod > 0xf0000000UL) || 802 (sc->sc_tod < DIFF19041970)) { 803 /* huh? try again */ 804 sc->sc_tod = 0; 805 aprint_verbose_dev(sc->sc_dev, 806 "got garbage reading RTC, trying again\n"); 807 } 808 } 809 810 tvp->tv_sec = sc->sc_tod - DIFF19041970; 811 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec); 812 tvp->tv_usec = 0; 813 return 0; 814 } 815 816 static int 817 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp) 818 { 819 struct cuda_softc *sc = tch->cookie; 820 uint32_t sec; 821 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 822 823 sec = tvp->tv_sec + DIFF19041970; 824 memcpy(&cmd[2], &sec, 4); 825 sc->sc_tod = 0; 826 if (cuda_send(sc, 0, 6, cmd) == 0) { 827 while (sc->sc_tod == 0) { 828 tsleep(&sc->sc_todev, 0, "todr", 10); 829 } 830 return 0; 831 } 832 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__); 833 return -1; 834 835 } 836 837 /* poweroff and reboot */ 838 839 void 840 cuda_poweroff(void) 841 { 842 struct cuda_softc *sc; 843 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 844 845 if (cuda0 == NULL) 846 return; 847 sc = cuda0->cookie; 848 sc->sc_polling = 1; 849 cuda0->poll(sc); 850 if (cuda0->send(sc, 1, 2, cmd) == 0) 851 while (1); 852 } 853 854 void 855 cuda_restart(void) 856 { 857 struct cuda_softc *sc; 858 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 859 860 if (cuda0 == NULL) 861 return; 862 sc = cuda0->cookie; 863 sc->sc_polling = 1; 864 cuda0->poll(sc); 865 if (cuda0->send(sc, 1, 2, cmd) == 0) 866 while (1); 867 } 868 869 /* ADB message handling */ 870 871 static void 872 cuda_autopoll(void *cookie, int flag) 873 { 874 struct cuda_softc *sc = cookie; 875 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 876 877 if (cmd[2] == sc->sc_autopoll) 878 return; 879 880 sc->sc_autopoll = -1; 881 cuda_send(sc, 0, 3, cmd); 882 while(sc->sc_autopoll == -1) { 883 if (sc->sc_polling || cold) { 884 cuda_poll(sc); 885 } else 886 tsleep(&sc->sc_todev, 0, "autopoll", 100); 887 } 888 } 889 890 static int 891 cuda_adb_handler(void *cookie, int len, uint8_t *data) 892 { 893 struct cuda_softc *sc = cookie; 894 895 if (sc->sc_adb_handler != NULL) { 896 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 897 &data[1]); 898 return 0; 899 } 900 return -1; 901 } 902 903 static int 904 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 905 { 906 struct cuda_softc *sc = cookie; 907 int i, s = 0; 908 uint8_t packet[16]; 909 910 /* construct an ADB command packet and send it */ 911 packet[0] = CUDA_ADB; 912 packet[1] = command; 913 for (i = 0; i < len; i++) 914 packet[i + 2] = data[i]; 915 if (poll || cold) { 916 s = splhigh(); 917 cuda_poll(sc); 918 } 919 cuda_send(sc, poll, len + 2, packet); 920 if (poll || cold) { 921 cuda_poll(sc); 922 splx(s); 923 } 924 return 0; 925 } 926 927 static int 928 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 929 void *hcookie) 930 { 931 struct cuda_softc *sc = cookie; 932 933 /* register a callback for incoming ADB messages */ 934 sc->sc_adb_handler = handler; 935 sc->sc_adb_cookie = hcookie; 936 return 0; 937 } 938 939 /* i2c message handling */ 940 941 static int 942 cuda_i2c_acquire_bus(void *cookie, int flags) 943 { 944 struct cuda_softc *sc = cookie; 945 946 mutex_enter(&sc->sc_buslock); 947 return 0; 948 } 949 950 static void 951 cuda_i2c_release_bus(void *cookie, int flags) 952 { 953 struct cuda_softc *sc = cookie; 954 955 mutex_exit(&sc->sc_buslock); 956 } 957 958 static int 959 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 960 size_t send_len, void *_recv, size_t recv_len, int flags) 961 { 962 struct cuda_softc *sc = cookie; 963 const uint8_t *send = _send; 964 uint8_t *recv = _recv; 965 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 966 967 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 968 command[2] = addr; 969 970 /* Copy command and output data bytes, if any, to buffer */ 971 if (send_len > 0) 972 memcpy(&command[3], send, min((int)send_len, 12)); 973 else if (I2C_OP_READ_P(op) && (recv_len == 0)) { 974 /* 975 * If no data bytes in either direction, it's a "quick" 976 * i2c operation. We don't know how to do a quick_read 977 * since that requires us to set the low bit of the 978 * address byte after it has been left-shifted. 979 */ 980 sc->sc_error = 0; 981 return -1; 982 } 983 984 sc->sc_iic_done = 0; 985 cuda_send(sc, sc->sc_polling, send_len + 3, command); 986 987 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 988 if (sc->sc_polling || cold) { 989 cuda_poll(sc); 990 } else 991 tsleep(&sc->sc_todev, 0, "i2c", 1000); 992 } 993 994 if (sc->sc_error) { 995 sc->sc_error = 0; 996 aprint_error_dev(sc->sc_dev, "error doing I2C\n"); 997 return -1; 998 } 999 1000 /* see if we're supposed to do a read */ 1001 if (recv_len > 0) { 1002 sc->sc_iic_done = 0; 1003 command[2] |= 1; 1004 command[3] = 0; 1005 1006 /* 1007 * XXX we need to do something to limit the size of the answer 1008 * - apparently the chip keeps sending until we tell it to stop 1009 */ 1010 sc->sc_i2c_read_len = recv_len; 1011 DPRINTF("rcv_len: %d\n", recv_len); 1012 cuda_send(sc, sc->sc_polling, 3, command); 1013 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 1014 if (sc->sc_polling || cold) { 1015 cuda_poll(sc); 1016 } else 1017 tsleep(&sc->sc_todev, 0, "i2c", 1000); 1018 } 1019 1020 if (sc->sc_error) { 1021 aprint_error_dev(sc->sc_dev, 1022 "error trying to read from I2C\n"); 1023 sc->sc_error = 0; 1024 return -1; 1025 } 1026 } 1027 1028 DPRINTF("received: %d\n", sc->sc_iic_done); 1029 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 1030 int rlen; 1031 1032 /* we got an answer */ 1033 rlen = min(sc->sc_iic_done - 3, recv_len); 1034 memcpy(recv, &sc->sc_in[4], rlen); 1035 #ifdef CUDA_DEBUG 1036 { 1037 int i; 1038 printf("ret:"); 1039 for (i = 0; i < rlen; i++) 1040 printf(" %02x", recv[i]); 1041 printf("\n"); 1042 } 1043 #endif 1044 return rlen; 1045 } 1046 return 0; 1047 } 1048
Indexes created Thu Sep 25 16:09:42 GMT 2025