cuda.c revision 1.24
1 /* $NetBSD: cuda.c,v 1.24 2019/12/22 23:23:30 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.24 2019/12/22 23:23:30 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/mutex.h> 38 39 #include <sys/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 #include <dev/clock_subr.h> 43 #include <dev/i2c/i2cvar.h> 44 45 #include <macppc/dev/viareg.h> 46 #include <macppc/dev/cudavar.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/adb/adbvar.h> 50 #include "opt_cuda.h" 51 52 #ifdef CUDA_DEBUG 53 #define DPRINTF printf 54 #else 55 #define DPRINTF while (0) printf 56 #endif 57 58 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 59 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 60 #define CUDA_OUT 0x3 /* sending out a command */ 61 #define CUDA_IN 0x4 /* receiving data */ 62 #define CUDA_POLLING 0x5 /* polling - II only */ 63 64 static void cuda_attach(device_t, device_t, void *); 65 static int cuda_match(device_t, struct cfdata *, void *); 66 static void cuda_autopoll(void *, int); 67 68 static int cuda_intr(void *); 69 70 typedef struct _cuda_handler { 71 int (*handler)(void *, int, uint8_t *); 72 void *cookie; 73 } CudaHandler; 74 75 struct cuda_softc { 76 device_t sc_dev; 77 void *sc_ih; 78 CudaHandler sc_handlers[16]; 79 struct todr_chip_handle sc_todr; 80 struct adb_bus_accessops sc_adbops; 81 struct i2c_controller sc_i2c; 82 bus_space_tag_t sc_memt; 83 bus_space_handle_t sc_memh; 84 int sc_node; 85 int sc_state; 86 int sc_waiting; 87 int sc_polling; 88 int sc_sent; 89 int sc_out_length; 90 int sc_received; 91 int sc_iic_done; 92 int sc_error; 93 /* time */ 94 uint32_t sc_tod; 95 uint32_t sc_autopoll; 96 uint32_t sc_todev; 97 /* ADB */ 98 void (*sc_adb_handler)(void *, int, uint8_t *); 99 void *sc_adb_cookie; 100 uint32_t sc_i2c_read_len; 101 /* internal buffers */ 102 uint8_t sc_in[256]; 103 uint8_t sc_out[256]; 104 }; 105 106 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc), 107 cuda_match, cuda_attach, NULL, NULL); 108 109 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 110 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 111 static void cuda_idle(struct cuda_softc *); 112 static void cuda_tip(struct cuda_softc *); 113 static void cuda_clear_tip(struct cuda_softc *); 114 static void cuda_in(struct cuda_softc *); 115 static void cuda_out(struct cuda_softc *); 116 static void cuda_toggle_ack(struct cuda_softc *); 117 static void cuda_ack_off(struct cuda_softc *); 118 static int cuda_intr_state(struct cuda_softc *); 119 120 static void cuda_init(struct cuda_softc *); 121 122 /* 123 * send a message to Cuda. 124 */ 125 /* cookie, flags, length, data */ 126 static int cuda_send(void *, int, int, uint8_t *); 127 static void cuda_poll(void *); 128 static void cuda_adb_poll(void *); 129 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 130 131 static int cuda_error_handler(void *, int, uint8_t *); 132 133 static int cuda_todr_handler(void *, int, uint8_t *); 134 static int cuda_todr_set(todr_chip_handle_t, struct timeval *); 135 static int cuda_todr_get(todr_chip_handle_t, struct timeval *); 136 137 static int cuda_adb_handler(void *, int, uint8_t *); 138 static void cuda_final(device_t); 139 140 static struct cuda_attach_args *cuda0 = NULL; 141 142 /* ADB bus attachment stuff */ 143 static int cuda_adb_send(void *, int, int, int, uint8_t *); 144 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 145 146 /* i2c stuff */ 147 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 148 void *, size_t, int); 149 150 static int 151 cuda_match(device_t parent, struct cfdata *cf, void *aux) 152 { 153 struct confargs *ca = aux; 154 155 if (ca->ca_nreg < 8) 156 return 0; 157 158 if (ca->ca_nintr < 4) 159 return 0; 160 161 if (strcmp(ca->ca_name, "via-cuda") == 0) { 162 return 10; /* beat adb* at obio? */ 163 } 164 165 return 0; 166 } 167 168 static void 169 cuda_attach(device_t parent, device_t self, void *aux) 170 { 171 struct confargs *ca = aux; 172 struct cuda_softc *sc = device_private(self); 173 struct i2cbus_attach_args iba; 174 static struct cuda_attach_args caa; 175 prop_dictionary_t dict = device_properties(self); 176 prop_dictionary_t dev; 177 prop_array_t cfg; 178 int irq = ca->ca_intr[0]; 179 int node, i, child; 180 char name[32]; 181 182 sc->sc_dev = self; 183 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1"); 184 if (node) 185 OF_getprop(node, "interrupts", &irq, 4); 186 187 aprint_normal(" irq %d", irq); 188 189 sc->sc_node = ca->ca_node; 190 sc->sc_memt = ca->ca_tag; 191 192 sc->sc_sent = 0; 193 sc->sc_received = 0; 194 sc->sc_waiting = 0; 195 sc->sc_polling = 0; 196 sc->sc_state = CUDA_NOTREADY; 197 sc->sc_error = 0; 198 sc->sc_i2c_read_len = 0; 199 200 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 201 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 202 203 aprint_normal(": unable to map registers\n"); 204 return; 205 } 206 sc->sc_ih = intr_establish(irq, IST_EDGE, IPL_TTY, cuda_intr, sc); 207 printf("\n"); 208 209 for (i = 0; i < 16; i++) { 210 sc->sc_handlers[i].handler = NULL; 211 sc->sc_handlers[i].cookie = NULL; 212 } 213 214 cuda_init(sc); 215 216 /* now attach children */ 217 config_interrupts(self, cuda_final); 218 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 219 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 220 221 child = OF_child(ca->ca_node); 222 while (child != 0) { 223 224 if (OF_getprop(child, "name", name, 32) == 0) 225 continue; 226 if (strncmp(name, "adb", 4) == 0) { 227 228 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 229 sc->sc_adbops.cookie = sc; 230 sc->sc_adbops.send = cuda_adb_send; 231 sc->sc_adbops.poll = cuda_adb_poll; 232 sc->sc_adbops.autopoll = cuda_autopoll; 233 sc->sc_adbops.set_handler = cuda_adb_set_handler; 234 config_found_ia(self, "adb_bus", &sc->sc_adbops, 235 nadb_print); 236 } else if (strncmp(name, "rtc", 4) == 0) { 237 238 sc->sc_todr.todr_gettime = cuda_todr_get; 239 sc->sc_todr.todr_settime = cuda_todr_set; 240 sc->sc_todr.cookie = sc; 241 todr_attach(&sc->sc_todr); 242 } 243 child = OF_peer(child); 244 } 245 246 caa.cookie = sc; 247 caa.set_handler = cuda_set_handler; 248 caa.send = cuda_send; 249 caa.poll = cuda_poll; 250 #if notyet 251 config_found(self, &caa, cuda_print); 252 #endif 253 cfg = prop_array_create(); 254 prop_dictionary_set(dict, "i2c-child-devices", cfg); 255 prop_object_release(cfg); 256 257 /* we don't have OF nodes for i2c devices so we have to make our own */ 258 259 node = OF_finddevice("/valkyrie"); 260 if (node != -1) { 261 dev = prop_dictionary_create(); 262 prop_dictionary_set_cstring(dev, "name", "videopll"); 263 prop_dictionary_set_uint32(dev, "addr", 0x50); 264 prop_array_add(cfg, dev); 265 prop_object_release(dev); 266 } 267 268 node = OF_finddevice("/perch"); 269 if (node != -1) { 270 dev = prop_dictionary_create(); 271 prop_dictionary_set_cstring(dev, "name", "sgsmix"); 272 prop_dictionary_set_uint32(dev, "addr", 0x8a); 273 prop_array_add(cfg, dev); 274 prop_object_release(dev); 275 } 276 277 memset(&iba, 0, sizeof(iba)); 278 iba.iba_tag = &sc->sc_i2c; 279 iic_tag_init(&sc->sc_i2c); 280 sc->sc_i2c.ic_cookie = sc; 281 sc->sc_i2c.ic_exec = cuda_i2c_exec; 282 config_found_ia(self, "i2cbus", &iba, iicbus_print); 283 284 if (cuda0 == NULL) 285 cuda0 = &caa; 286 } 287 288 static void 289 cuda_init(struct cuda_softc *sc) 290 { 291 uint8_t reg; 292 293 reg = cuda_read_reg(sc, vDirB); 294 reg |= 0x30; /* register B bits 4 and 5: outputs */ 295 cuda_write_reg(sc, vDirB, reg); 296 297 reg = cuda_read_reg(sc, vDirB); 298 reg &= 0xf7; /* register B bit 3: input */ 299 cuda_write_reg(sc, vDirB, reg); 300 301 reg = cuda_read_reg(sc, vACR); 302 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 303 cuda_write_reg(sc, vACR, reg); 304 305 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 306 307 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 308 309 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 310 cuda_idle(sc); /* set ADB bus state to idle */ 311 312 /* sort of a device reset */ 313 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 314 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 315 cuda_idle(sc); /* reset state to idle */ 316 delay(150); 317 cuda_tip(sc); /* signal start of frame */ 318 delay(150); 319 cuda_toggle_ack(sc); 320 delay(150); 321 cuda_clear_tip(sc); 322 delay(150); 323 cuda_idle(sc); /* back to idle state */ 324 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 325 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 326 } 327 328 static void 329 cuda_final(device_t dev) 330 { 331 struct cuda_softc *sc = device_private(dev); 332 333 sc->sc_polling = 0; 334 } 335 336 static inline void 337 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 338 { 339 340 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 341 } 342 343 static inline uint8_t 344 cuda_read_reg(struct cuda_softc *sc, int offset) 345 { 346 347 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 348 } 349 350 static int 351 cuda_set_handler(void *cookie, int type, 352 int (*handler)(void *, int, uint8_t *), void *hcookie) 353 { 354 struct cuda_softc *sc = cookie; 355 CudaHandler *me; 356 357 if ((type >= 0) && (type < 16)) { 358 me = &sc->sc_handlers[type]; 359 me->handler = handler; 360 me->cookie = hcookie; 361 return 0; 362 } 363 return -1; 364 } 365 366 static int 367 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 368 { 369 struct cuda_softc *sc = cookie; 370 int s; 371 372 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 373 if (sc->sc_state == CUDA_NOTREADY) 374 return -1; 375 376 s = splhigh(); 377 378 if (sc->sc_state == CUDA_IDLE /*&& 379 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) { 380 /* fine */ 381 DPRINTF("chip is idle\n"); 382 } else { 383 DPRINTF("cuda state is %d\n", sc->sc_state); 384 if (sc->sc_waiting == 0) { 385 sc->sc_waiting = 1; 386 } else { 387 splx(s); 388 return -1; 389 } 390 } 391 392 sc->sc_error = 0; 393 memcpy(sc->sc_out, msg, length); 394 sc->sc_out_length = length; 395 sc->sc_sent = 0; 396 397 if (sc->sc_waiting != 1) { 398 399 delay(150); 400 sc->sc_state = CUDA_OUT; 401 cuda_out(sc); 402 cuda_write_reg(sc, vSR, sc->sc_out[0]); 403 cuda_ack_off(sc); 404 cuda_tip(sc); 405 } 406 sc->sc_waiting = 1; 407 408 if (sc->sc_polling || poll || cold) { 409 cuda_poll(sc); 410 } 411 412 splx(s); 413 414 return 0; 415 } 416 417 static void 418 cuda_poll(void *cookie) 419 { 420 struct cuda_softc *sc = cookie; 421 int s; 422 423 DPRINTF("polling\n"); 424 while ((sc->sc_state != CUDA_IDLE) || 425 (cuda_intr_state(sc)) || 426 (sc->sc_waiting == 1)) { 427 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 428 s = splhigh(); 429 cuda_intr(sc); 430 splx(s); 431 } 432 } 433 } 434 435 static void 436 cuda_adb_poll(void *cookie) 437 { 438 struct cuda_softc *sc = cookie; 439 int s; 440 441 s = splhigh(); 442 cuda_intr(sc); 443 splx(s); 444 } 445 446 static void 447 cuda_idle(struct cuda_softc *sc) 448 { 449 uint8_t reg; 450 451 reg = cuda_read_reg(sc, vBufB); 452 reg |= (vPB4 | vPB5); 453 cuda_write_reg(sc, vBufB, reg); 454 } 455 456 static void 457 cuda_tip(struct cuda_softc *sc) 458 { 459 uint8_t reg; 460 461 reg = cuda_read_reg(sc, vBufB); 462 reg &= ~vPB5; 463 cuda_write_reg(sc, vBufB, reg); 464 } 465 466 static void 467 cuda_clear_tip(struct cuda_softc *sc) 468 { 469 uint8_t reg; 470 471 reg = cuda_read_reg(sc, vBufB); 472 reg |= vPB5; 473 cuda_write_reg(sc, vBufB, reg); 474 } 475 476 static void 477 cuda_in(struct cuda_softc *sc) 478 { 479 uint8_t reg; 480 481 reg = cuda_read_reg(sc, vACR); 482 reg &= ~vSR_OUT; 483 cuda_write_reg(sc, vACR, reg); 484 } 485 486 static void 487 cuda_out(struct cuda_softc *sc) 488 { 489 uint8_t reg; 490 491 reg = cuda_read_reg(sc, vACR); 492 reg |= vSR_OUT; 493 cuda_write_reg(sc, vACR, reg); 494 } 495 496 static void 497 cuda_toggle_ack(struct cuda_softc *sc) 498 { 499 uint8_t reg; 500 501 reg = cuda_read_reg(sc, vBufB); 502 reg ^= vPB4; 503 cuda_write_reg(sc, vBufB, reg); 504 } 505 506 static void 507 cuda_ack_off(struct cuda_softc *sc) 508 { 509 uint8_t reg; 510 511 reg = cuda_read_reg(sc, vBufB); 512 reg |= vPB4; 513 cuda_write_reg(sc, vBufB, reg); 514 } 515 516 static int 517 cuda_intr_state(struct cuda_softc *sc) 518 { 519 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 520 } 521 522 static int 523 cuda_intr(void *arg) 524 { 525 struct cuda_softc *sc = arg; 526 int ending, type; 527 uint8_t reg; 528 529 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 530 DPRINTF("["); 531 if ((reg & 0x80) == 0) { 532 DPRINTF("irq %02x]", reg); 533 return 0; /* No interrupts to process */ 534 } 535 DPRINTF(":"); 536 537 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 538 539 switch_start: 540 switch (sc->sc_state) { 541 case CUDA_IDLE: 542 /* 543 * This is an unexpected packet, so grab the first (dummy) 544 * byte, set up the proper vars, and tell the chip we are 545 * starting to receive the packet by setting the TIP bit. 546 */ 547 sc->sc_in[1] = cuda_read_reg(sc, vSR); 548 DPRINTF("start: %02x", sc->sc_in[1]); 549 if (cuda_intr_state(sc) == 0) { 550 /* must have been a fake start */ 551 DPRINTF(" ... fake start\n"); 552 if (sc->sc_waiting) { 553 /* start over */ 554 delay(150); 555 sc->sc_state = CUDA_OUT; 556 sc->sc_sent = 0; 557 cuda_out(sc); 558 cuda_write_reg(sc, vSR, sc->sc_out[1]); 559 cuda_ack_off(sc); 560 cuda_tip(sc); 561 } 562 break; 563 } 564 565 cuda_in(sc); 566 cuda_tip(sc); 567 568 sc->sc_received = 1; 569 sc->sc_state = CUDA_IN; 570 DPRINTF(" CUDA_IN"); 571 break; 572 573 case CUDA_IN: 574 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 575 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 576 ending = 0; 577 if (sc->sc_received > 255) { 578 /* bitch only once */ 579 if (sc->sc_received == 256) { 580 aprint_error_dev(sc->sc_dev, 581 "input overflow\n"); 582 ending = 1; 583 } 584 } else 585 sc->sc_received++; 586 if (sc->sc_received > 3) { 587 if ((sc->sc_in[3] == CMD_IIC) && 588 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 589 ending = 1; 590 } 591 } 592 593 /* intr off means this is the last byte (end of frame) */ 594 if (cuda_intr_state(sc) == 0) { 595 ending = 1; 596 DPRINTF(".\n"); 597 } else { 598 cuda_toggle_ack(sc); 599 } 600 601 if (ending == 1) { /* end of message? */ 602 603 sc->sc_in[0] = sc->sc_received - 1; 604 605 /* reset vars and signal the end of this frame */ 606 cuda_idle(sc); 607 608 /* check if we have a handler for this message */ 609 type = sc->sc_in[1]; 610 if ((type >= 0) && (type < 16)) { 611 CudaHandler *me = &sc->sc_handlers[type]; 612 613 if (me->handler != NULL) { 614 me->handler(me->cookie, 615 sc->sc_received - 1, &sc->sc_in[1]); 616 } else { 617 aprint_error_dev(sc->sc_dev, 618 "no handler for type %02x\n", type); 619 panic("barf"); 620 } 621 } 622 623 DPRINTF("CUDA_IDLE"); 624 sc->sc_state = CUDA_IDLE; 625 626 sc->sc_received = 0; 627 628 /* 629 * If there is something waiting to be sent out, 630 * set everything up and send the first byte. 631 */ 632 if (sc->sc_waiting == 1) { 633 634 DPRINTF("pending write\n"); 635 delay(1500); /* required */ 636 sc->sc_sent = 0; 637 sc->sc_state = CUDA_OUT; 638 639 /* 640 * If the interrupt is on, we were too slow 641 * and the chip has already started to send 642 * something to us, so back out of the write 643 * and start a read cycle. 644 */ 645 if (cuda_intr_state(sc)) { 646 cuda_in(sc); 647 cuda_idle(sc); 648 sc->sc_sent = 0; 649 sc->sc_state = CUDA_IDLE; 650 sc->sc_received = 0; 651 delay(150); 652 DPRINTF("too slow - incoming message\n"); 653 goto switch_start; 654 } 655 /* 656 * If we got here, it's ok to start sending 657 * so load the first byte and tell the chip 658 * we want to send. 659 */ 660 DPRINTF("sending "); 661 662 cuda_out(sc); 663 cuda_write_reg(sc, vSR, 664 sc->sc_out[sc->sc_sent]); 665 cuda_ack_off(sc); 666 cuda_tip(sc); 667 } 668 } 669 break; 670 671 case CUDA_OUT: 672 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 673 674 sc->sc_sent++; 675 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 676 677 DPRINTF("incoming msg during send\n"); 678 cuda_in(sc); /* make sure SR is set to IN */ 679 cuda_idle(sc); 680 sc->sc_sent = 0; /* must start all over */ 681 sc->sc_state = CUDA_IDLE; /* new state */ 682 sc->sc_received = 0; 683 sc->sc_waiting = 1; /* must retry when done with 684 * read */ 685 delay(150); 686 goto switch_start; /* process next state right 687 * now */ 688 break; 689 } 690 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 691 692 sc->sc_waiting = 0; /* done writing */ 693 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 694 cuda_in(sc); 695 cuda_idle(sc); 696 DPRINTF("done sending\n"); 697 } else { 698 /* send next byte */ 699 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 700 DPRINTF("%02x", sc->sc_out[sc->sc_sent]); 701 cuda_toggle_ack(sc); /* signal byte ready to 702 * shift */ 703 } 704 break; 705 706 case CUDA_NOTREADY: 707 DPRINTF("adb: not yet initialized\n"); 708 break; 709 710 default: 711 DPRINTF("intr: unknown ADB state\n"); 712 break; 713 } 714 715 DPRINTF("]"); 716 return 1; 717 } 718 719 static int 720 cuda_error_handler(void *cookie, int len, uint8_t *data) 721 { 722 struct cuda_softc *sc = cookie; 723 724 /* 725 * something went wrong 726 * byte 3 seems to be the failed command 727 */ 728 sc->sc_error = 1; 729 wakeup(&sc->sc_todev); 730 return 0; 731 } 732 733 734 /* real time clock */ 735 736 static int 737 cuda_todr_handler(void *cookie, int len, uint8_t *data) 738 { 739 struct cuda_softc *sc = cookie; 740 741 #ifdef CUDA_DEBUG 742 int i; 743 printf("msg: %02x", data[0]); 744 for (i = 1; i < len; i++) { 745 printf(" %02x", data[i]); 746 } 747 printf("\n"); 748 #endif 749 750 switch(data[2]) { 751 case CMD_READ_RTC: 752 memcpy(&sc->sc_tod, &data[3], 4); 753 break; 754 case CMD_WRITE_RTC: 755 sc->sc_tod = 0xffffffff; 756 break; 757 case CMD_AUTOPOLL: 758 sc->sc_autopoll = 1; 759 break; 760 case CMD_IIC: 761 sc->sc_iic_done = len; 762 break; 763 } 764 wakeup(&sc->sc_todev); 765 return 0; 766 } 767 768 #define DIFF19041970 2082844800 769 770 static int 771 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp) 772 { 773 struct cuda_softc *sc = tch->cookie; 774 int cnt = 0; 775 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 776 777 sc->sc_tod = 0; 778 while (sc->sc_tod == 0) { 779 cuda_send(sc, 0, 2, cmd); 780 781 while ((sc->sc_tod == 0) && (cnt < 10)) { 782 tsleep(&sc->sc_todev, 0, "todr", 10); 783 cnt++; 784 } 785 786 if (sc->sc_tod == 0) { 787 aprint_error_dev(sc->sc_dev, 788 "unable to read a sane RTC value\n"); 789 return EIO; 790 } 791 if ((sc->sc_tod > 0xf0000000UL) || 792 (sc->sc_tod < DIFF19041970)) { 793 /* huh? try again */ 794 sc->sc_tod = 0; 795 aprint_verbose_dev(sc->sc_dev, 796 "got garbage reading RTC, trying again\n"); 797 } 798 } 799 800 tvp->tv_sec = sc->sc_tod - DIFF19041970; 801 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec); 802 tvp->tv_usec = 0; 803 return 0; 804 } 805 806 static int 807 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp) 808 { 809 struct cuda_softc *sc = tch->cookie; 810 uint32_t sec; 811 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 812 813 sec = tvp->tv_sec + DIFF19041970; 814 memcpy(&cmd[2], &sec, 4); 815 sc->sc_tod = 0; 816 if (cuda_send(sc, 0, 6, cmd) == 0) { 817 while (sc->sc_tod == 0) { 818 tsleep(&sc->sc_todev, 0, "todr", 10); 819 } 820 return 0; 821 } 822 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__); 823 return -1; 824 825 } 826 827 /* poweroff and reboot */ 828 829 void 830 cuda_poweroff(void) 831 { 832 struct cuda_softc *sc; 833 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 834 835 if (cuda0 == NULL) 836 return; 837 sc = cuda0->cookie; 838 sc->sc_polling = 1; 839 cuda0->poll(sc); 840 if (cuda0->send(sc, 1, 2, cmd) == 0) 841 while (1); 842 } 843 844 void 845 cuda_restart(void) 846 { 847 struct cuda_softc *sc; 848 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 849 850 if (cuda0 == NULL) 851 return; 852 sc = cuda0->cookie; 853 sc->sc_polling = 1; 854 cuda0->poll(sc); 855 if (cuda0->send(sc, 1, 2, cmd) == 0) 856 while (1); 857 } 858 859 /* ADB message handling */ 860 861 static void 862 cuda_autopoll(void *cookie, int flag) 863 { 864 struct cuda_softc *sc = cookie; 865 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 866 867 if (cmd[2] == sc->sc_autopoll) 868 return; 869 870 sc->sc_autopoll = -1; 871 cuda_send(sc, 0, 3, cmd); 872 while(sc->sc_autopoll == -1) { 873 if (sc->sc_polling || cold) { 874 cuda_poll(sc); 875 } else 876 tsleep(&sc->sc_todev, 0, "autopoll", 100); 877 } 878 } 879 880 static int 881 cuda_adb_handler(void *cookie, int len, uint8_t *data) 882 { 883 struct cuda_softc *sc = cookie; 884 885 if (sc->sc_adb_handler != NULL) { 886 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 887 &data[1]); 888 return 0; 889 } 890 return -1; 891 } 892 893 static int 894 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 895 { 896 struct cuda_softc *sc = cookie; 897 int i, s = 0; 898 uint8_t packet[16]; 899 900 /* construct an ADB command packet and send it */ 901 packet[0] = CUDA_ADB; 902 packet[1] = command; 903 for (i = 0; i < len; i++) 904 packet[i + 2] = data[i]; 905 if (poll || cold) { 906 s = splhigh(); 907 cuda_poll(sc); 908 } 909 cuda_send(sc, poll, len + 2, packet); 910 if (poll || cold) { 911 cuda_poll(sc); 912 splx(s); 913 } 914 return 0; 915 } 916 917 static int 918 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 919 void *hcookie) 920 { 921 struct cuda_softc *sc = cookie; 922 923 /* register a callback for incoming ADB messages */ 924 sc->sc_adb_handler = handler; 925 sc->sc_adb_cookie = hcookie; 926 return 0; 927 } 928 929 /* i2c message handling */ 930 931 static int 932 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 933 size_t send_len, void *_recv, size_t recv_len, int flags) 934 { 935 struct cuda_softc *sc = cookie; 936 const uint8_t *send = _send; 937 uint8_t *recv = _recv; 938 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 939 940 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 941 command[2] = addr; 942 943 /* Copy command and output data bytes, if any, to buffer */ 944 if (send_len > 0) 945 memcpy(&command[3], send, uimin((int)send_len, 12)); 946 else if (I2C_OP_READ_P(op) && (recv_len == 0)) { 947 /* 948 * If no data bytes in either direction, it's a "quick" 949 * i2c operation. We don't know how to do a quick_read 950 * since that requires us to set the low bit of the 951 * address byte after it has been left-shifted. 952 */ 953 sc->sc_error = 0; 954 return -1; 955 } 956 957 sc->sc_iic_done = 0; 958 cuda_send(sc, sc->sc_polling, send_len + 3, command); 959 960 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 961 if (sc->sc_polling || cold) { 962 cuda_poll(sc); 963 } else 964 tsleep(&sc->sc_todev, 0, "i2c", 1000); 965 } 966 967 if (sc->sc_error) { 968 sc->sc_error = 0; 969 aprint_error_dev(sc->sc_dev, "error doing I2C\n"); 970 return -1; 971 } 972 973 /* see if we're supposed to do a read */ 974 if (recv_len > 0) { 975 sc->sc_iic_done = 0; 976 command[2] |= 1; 977 command[3] = 0; 978 979 /* 980 * XXX we need to do something to limit the size of the answer 981 * - apparently the chip keeps sending until we tell it to stop 982 */ 983 sc->sc_i2c_read_len = recv_len; 984 DPRINTF("rcv_len: %d\n", recv_len); 985 cuda_send(sc, sc->sc_polling, 3, command); 986 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 987 if (sc->sc_polling || cold) { 988 cuda_poll(sc); 989 } else 990 tsleep(&sc->sc_todev, 0, "i2c", 1000); 991 } 992 993 if (sc->sc_error) { 994 aprint_error_dev(sc->sc_dev, 995 "error trying to read from I2C\n"); 996 sc->sc_error = 0; 997 return -1; 998 } 999 } 1000 1001 DPRINTF("received: %d\n", sc->sc_iic_done); 1002 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 1003 int rlen; 1004 1005 /* we got an answer */ 1006 rlen = uimin(sc->sc_iic_done - 3, recv_len); 1007 memcpy(recv, &sc->sc_in[4], rlen); 1008 #ifdef CUDA_DEBUG 1009 { 1010 int i; 1011 printf("ret:"); 1012 for (i = 0; i < rlen; i++) 1013 printf(" %02x", recv[i]); 1014 printf("\n"); 1015 } 1016 #endif 1017 return rlen; 1018 } 1019 return 0; 1020 } 1021
Indexes created Tue Sep 23 23:09:58 GMT 2025