cuda.c revision 1.27
1 /* $NetBSD: cuda.c,v 1.27 2021/03/05 07:15:53 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.27 2021/03/05 07:15:53 rin Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/mutex.h> 38 39 #include <sys/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 #include <dev/clock_subr.h> 43 #include <dev/i2c/i2cvar.h> 44 45 #include <macppc/dev/viareg.h> 46 #include <macppc/dev/cudavar.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/adb/adbvar.h> 50 #include "opt_cuda.h" 51 52 #ifdef CUDA_DEBUG 53 #define DPRINTF printf 54 #else 55 #define DPRINTF while (0) printf 56 #endif 57 58 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 59 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 60 #define CUDA_OUT 0x3 /* sending out a command */ 61 #define CUDA_IN 0x4 /* receiving data */ 62 #define CUDA_POLLING 0x5 /* polling - II only */ 63 64 static void cuda_attach(device_t, device_t, void *); 65 static int cuda_match(device_t, struct cfdata *, void *); 66 static void cuda_autopoll(void *, int); 67 68 static int cuda_intr(void *); 69 70 typedef struct _cuda_handler { 71 int (*handler)(void *, int, uint8_t *); 72 void *cookie; 73 } CudaHandler; 74 75 struct cuda_softc { 76 device_t sc_dev; 77 void *sc_ih; 78 CudaHandler sc_handlers[16]; 79 struct todr_chip_handle sc_todr; 80 struct adb_bus_accessops sc_adbops; 81 struct i2c_controller sc_i2c; 82 bus_space_tag_t sc_memt; 83 bus_space_handle_t sc_memh; 84 int sc_node; 85 int sc_state; 86 int sc_waiting; 87 int sc_polling; 88 int sc_sent; 89 int sc_out_length; 90 int sc_received; 91 int sc_iic_done; 92 int sc_error; 93 /* time */ 94 uint32_t sc_tod; 95 uint32_t sc_autopoll; 96 uint32_t sc_todev; 97 /* ADB */ 98 void (*sc_adb_handler)(void *, int, uint8_t *); 99 void *sc_adb_cookie; 100 uint32_t sc_i2c_read_len; 101 /* internal buffers */ 102 uint8_t sc_in[256]; 103 uint8_t sc_out[256]; 104 }; 105 106 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc), 107 cuda_match, cuda_attach, NULL, NULL); 108 109 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 110 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 111 static void cuda_idle(struct cuda_softc *); 112 static void cuda_tip(struct cuda_softc *); 113 static void cuda_clear_tip(struct cuda_softc *); 114 static void cuda_in(struct cuda_softc *); 115 static void cuda_out(struct cuda_softc *); 116 static void cuda_toggle_ack(struct cuda_softc *); 117 static void cuda_ack_off(struct cuda_softc *); 118 static int cuda_intr_state(struct cuda_softc *); 119 120 static void cuda_init(struct cuda_softc *); 121 122 /* 123 * send a message to Cuda. 124 */ 125 /* cookie, flags, length, data */ 126 static int cuda_send(void *, int, int, uint8_t *); 127 static void cuda_poll(void *); 128 static void cuda_adb_poll(void *); 129 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 130 131 static int cuda_error_handler(void *, int, uint8_t *); 132 133 static int cuda_todr_handler(void *, int, uint8_t *); 134 static int cuda_todr_set(todr_chip_handle_t, struct timeval *); 135 static int cuda_todr_get(todr_chip_handle_t, struct timeval *); 136 137 static int cuda_adb_handler(void *, int, uint8_t *); 138 static void cuda_final(device_t); 139 140 static struct cuda_attach_args *cuda0 = NULL; 141 142 /* ADB bus attachment stuff */ 143 static int cuda_adb_send(void *, int, int, int, uint8_t *); 144 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 145 146 /* i2c stuff */ 147 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 148 void *, size_t, int); 149 150 static int 151 cuda_match(device_t parent, struct cfdata *cf, void *aux) 152 { 153 struct confargs *ca = aux; 154 155 if (ca->ca_nreg < 8) 156 return 0; 157 158 if (ca->ca_nintr < 4) 159 return 0; 160 161 if (strcmp(ca->ca_name, "via-cuda") == 0) { 162 return 10; /* beat adb* at obio? */ 163 } 164 165 return 0; 166 } 167 168 static void 169 cuda_attach(device_t parent, device_t self, void *aux) 170 { 171 struct confargs *ca = aux; 172 struct cuda_softc *sc = device_private(self); 173 struct i2cbus_attach_args iba; 174 static struct cuda_attach_args caa; 175 prop_dictionary_t dict = device_properties(self); 176 prop_dictionary_t dev; 177 prop_array_t cfg; 178 int irq = ca->ca_intr[0]; 179 int node, i, child; 180 char name[32]; 181 182 sc->sc_dev = self; 183 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1"); 184 if (node) 185 OF_getprop(node, "interrupts", &irq, 4); 186 187 aprint_normal(" irq %d", irq); 188 189 sc->sc_node = ca->ca_node; 190 sc->sc_memt = ca->ca_tag; 191 192 sc->sc_sent = 0; 193 sc->sc_received = 0; 194 sc->sc_waiting = 0; 195 sc->sc_polling = 0; 196 sc->sc_state = CUDA_NOTREADY; 197 sc->sc_error = 0; 198 sc->sc_i2c_read_len = 0; 199 200 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 201 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 202 203 aprint_normal(": unable to map registers\n"); 204 return; 205 } 206 sc->sc_ih = intr_establish_xname(irq, IST_EDGE, IPL_TTY, cuda_intr, sc, 207 device_xname(self)); 208 printf("\n"); 209 210 for (i = 0; i < 16; i++) { 211 sc->sc_handlers[i].handler = NULL; 212 sc->sc_handlers[i].cookie = NULL; 213 } 214 215 cuda_init(sc); 216 217 /* now attach children */ 218 config_interrupts(self, cuda_final); 219 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 220 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 221 222 child = OF_child(ca->ca_node); 223 while (child != 0) { 224 225 if (OF_getprop(child, "name", name, 32) == 0) 226 continue; 227 if (strncmp(name, "adb", 4) == 0) { 228 229 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 230 sc->sc_adbops.cookie = sc; 231 sc->sc_adbops.send = cuda_adb_send; 232 sc->sc_adbops.poll = cuda_adb_poll; 233 sc->sc_adbops.autopoll = cuda_autopoll; 234 sc->sc_adbops.set_handler = cuda_adb_set_handler; 235 config_found_ia(self, "adb_bus", &sc->sc_adbops, 236 nadb_print); 237 } else if (strncmp(name, "rtc", 4) == 0) { 238 239 sc->sc_todr.todr_gettime = cuda_todr_get; 240 sc->sc_todr.todr_settime = cuda_todr_set; 241 sc->sc_todr.cookie = sc; 242 todr_attach(&sc->sc_todr); 243 } 244 child = OF_peer(child); 245 } 246 247 caa.cookie = sc; 248 caa.set_handler = cuda_set_handler; 249 caa.send = cuda_send; 250 caa.poll = cuda_poll; 251 #if notyet 252 config_found(self, &caa, cuda_print); 253 #endif 254 cfg = prop_array_create(); 255 prop_dictionary_set(dict, "i2c-child-devices", cfg); 256 prop_object_release(cfg); 257 258 /* we don't have OF nodes for i2c devices so we have to make our own */ 259 260 node = OF_finddevice("/valkyrie"); 261 if (node != -1) { 262 dev = prop_dictionary_create(); 263 prop_dictionary_set_string(dev, "name", "videopll"); 264 prop_dictionary_set_uint32(dev, "addr", 0x50); 265 prop_array_add(cfg, dev); 266 prop_object_release(dev); 267 } 268 269 node = OF_finddevice("/perch"); 270 if (node != -1) { 271 dev = prop_dictionary_create(); 272 prop_dictionary_set_string(dev, "name", "sgsmix"); 273 prop_dictionary_set_uint32(dev, "addr", 0x8a); 274 prop_array_add(cfg, dev); 275 prop_object_release(dev); 276 } 277 278 memset(&iba, 0, sizeof(iba)); 279 iba.iba_tag = &sc->sc_i2c; 280 iic_tag_init(&sc->sc_i2c); 281 sc->sc_i2c.ic_cookie = sc; 282 sc->sc_i2c.ic_exec = cuda_i2c_exec; 283 config_found_ia(self, "i2cbus", &iba, iicbus_print); 284 285 if (cuda0 == NULL) 286 cuda0 = &caa; 287 } 288 289 static void 290 cuda_init(struct cuda_softc *sc) 291 { 292 uint8_t reg; 293 294 reg = cuda_read_reg(sc, vDirB); 295 reg |= 0x30; /* register B bits 4 and 5: outputs */ 296 cuda_write_reg(sc, vDirB, reg); 297 298 reg = cuda_read_reg(sc, vDirB); 299 reg &= 0xf7; /* register B bit 3: input */ 300 cuda_write_reg(sc, vDirB, reg); 301 302 reg = cuda_read_reg(sc, vACR); 303 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 304 cuda_write_reg(sc, vACR, reg); 305 306 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 307 308 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 309 310 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 311 cuda_idle(sc); /* set ADB bus state to idle */ 312 313 /* sort of a device reset */ 314 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 315 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 316 cuda_idle(sc); /* reset state to idle */ 317 delay(150); 318 cuda_tip(sc); /* signal start of frame */ 319 delay(150); 320 cuda_toggle_ack(sc); 321 delay(150); 322 cuda_clear_tip(sc); 323 delay(150); 324 cuda_idle(sc); /* back to idle state */ 325 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 326 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 327 } 328 329 static void 330 cuda_final(device_t dev) 331 { 332 struct cuda_softc *sc = device_private(dev); 333 334 sc->sc_polling = 0; 335 } 336 337 static inline void 338 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 339 { 340 341 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 342 } 343 344 static inline uint8_t 345 cuda_read_reg(struct cuda_softc *sc, int offset) 346 { 347 348 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 349 } 350 351 static int 352 cuda_set_handler(void *cookie, int type, 353 int (*handler)(void *, int, uint8_t *), void *hcookie) 354 { 355 struct cuda_softc *sc = cookie; 356 CudaHandler *me; 357 358 if ((type >= 0) && (type < 16)) { 359 me = &sc->sc_handlers[type]; 360 me->handler = handler; 361 me->cookie = hcookie; 362 return 0; 363 } 364 return -1; 365 } 366 367 static int 368 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 369 { 370 struct cuda_softc *sc = cookie; 371 int s; 372 373 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 374 if (sc->sc_state == CUDA_NOTREADY) 375 return -1; 376 377 s = splhigh(); 378 379 if (sc->sc_state == CUDA_IDLE /*&& 380 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) { 381 /* fine */ 382 DPRINTF("chip is idle\n"); 383 } else { 384 DPRINTF("cuda state is %d\n", sc->sc_state); 385 if (sc->sc_waiting == 0) { 386 sc->sc_waiting = 1; 387 } else { 388 splx(s); 389 return -1; 390 } 391 } 392 393 sc->sc_error = 0; 394 memcpy(sc->sc_out, msg, length); 395 sc->sc_out_length = length; 396 sc->sc_sent = 0; 397 398 if (sc->sc_waiting != 1) { 399 400 delay(150); 401 sc->sc_state = CUDA_OUT; 402 cuda_out(sc); 403 cuda_write_reg(sc, vSR, sc->sc_out[0]); 404 cuda_ack_off(sc); 405 cuda_tip(sc); 406 } 407 sc->sc_waiting = 1; 408 409 if (sc->sc_polling || poll || cold) { 410 cuda_poll(sc); 411 } 412 413 splx(s); 414 415 return 0; 416 } 417 418 static void 419 cuda_poll(void *cookie) 420 { 421 struct cuda_softc *sc = cookie; 422 int s; 423 424 DPRINTF("polling\n"); 425 while ((sc->sc_state != CUDA_IDLE) || 426 (cuda_intr_state(sc)) || 427 (sc->sc_waiting == 1)) { 428 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 429 s = splhigh(); 430 cuda_intr(sc); 431 splx(s); 432 } 433 } 434 } 435 436 static void 437 cuda_adb_poll(void *cookie) 438 { 439 struct cuda_softc *sc = cookie; 440 int s; 441 442 s = splhigh(); 443 cuda_intr(sc); 444 splx(s); 445 } 446 447 static void 448 cuda_idle(struct cuda_softc *sc) 449 { 450 uint8_t reg; 451 452 reg = cuda_read_reg(sc, vBufB); 453 reg |= (vPB4 | vPB5); 454 cuda_write_reg(sc, vBufB, reg); 455 } 456 457 static void 458 cuda_tip(struct cuda_softc *sc) 459 { 460 uint8_t reg; 461 462 reg = cuda_read_reg(sc, vBufB); 463 reg &= ~vPB5; 464 cuda_write_reg(sc, vBufB, reg); 465 } 466 467 static void 468 cuda_clear_tip(struct cuda_softc *sc) 469 { 470 uint8_t reg; 471 472 reg = cuda_read_reg(sc, vBufB); 473 reg |= vPB5; 474 cuda_write_reg(sc, vBufB, reg); 475 } 476 477 static void 478 cuda_in(struct cuda_softc *sc) 479 { 480 uint8_t reg; 481 482 reg = cuda_read_reg(sc, vACR); 483 reg &= ~vSR_OUT; 484 cuda_write_reg(sc, vACR, reg); 485 } 486 487 static void 488 cuda_out(struct cuda_softc *sc) 489 { 490 uint8_t reg; 491 492 reg = cuda_read_reg(sc, vACR); 493 reg |= vSR_OUT; 494 cuda_write_reg(sc, vACR, reg); 495 } 496 497 static void 498 cuda_toggle_ack(struct cuda_softc *sc) 499 { 500 uint8_t reg; 501 502 reg = cuda_read_reg(sc, vBufB); 503 reg ^= vPB4; 504 cuda_write_reg(sc, vBufB, reg); 505 } 506 507 static void 508 cuda_ack_off(struct cuda_softc *sc) 509 { 510 uint8_t reg; 511 512 reg = cuda_read_reg(sc, vBufB); 513 reg |= vPB4; 514 cuda_write_reg(sc, vBufB, reg); 515 } 516 517 static int 518 cuda_intr_state(struct cuda_softc *sc) 519 { 520 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 521 } 522 523 static int 524 cuda_intr(void *arg) 525 { 526 struct cuda_softc *sc = arg; 527 int ending, type; 528 uint8_t reg; 529 530 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 531 DPRINTF("["); 532 if ((reg & 0x80) == 0) { 533 DPRINTF("irq %02x]", reg); 534 return 0; /* No interrupts to process */ 535 } 536 DPRINTF(":"); 537 538 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 539 540 switch_start: 541 switch (sc->sc_state) { 542 case CUDA_IDLE: 543 /* 544 * This is an unexpected packet, so grab the first (dummy) 545 * byte, set up the proper vars, and tell the chip we are 546 * starting to receive the packet by setting the TIP bit. 547 */ 548 sc->sc_in[1] = cuda_read_reg(sc, vSR); 549 DPRINTF("start: %02x", sc->sc_in[1]); 550 if (cuda_intr_state(sc) == 0) { 551 /* must have been a fake start */ 552 DPRINTF(" ... fake start\n"); 553 if (sc->sc_waiting) { 554 /* start over */ 555 delay(150); 556 sc->sc_state = CUDA_OUT; 557 sc->sc_sent = 0; 558 cuda_out(sc); 559 cuda_write_reg(sc, vSR, sc->sc_out[1]); 560 cuda_ack_off(sc); 561 cuda_tip(sc); 562 } 563 break; 564 } 565 566 cuda_in(sc); 567 cuda_tip(sc); 568 569 sc->sc_received = 1; 570 sc->sc_state = CUDA_IN; 571 DPRINTF(" CUDA_IN"); 572 break; 573 574 case CUDA_IN: 575 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 576 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 577 ending = 0; 578 if (sc->sc_received > 255) { 579 /* bitch only once */ 580 if (sc->sc_received == 256) { 581 aprint_error_dev(sc->sc_dev, 582 "input overflow\n"); 583 ending = 1; 584 } 585 } else 586 sc->sc_received++; 587 if (sc->sc_received > 3) { 588 if ((sc->sc_in[3] == CMD_IIC) && 589 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 590 ending = 1; 591 } 592 } 593 594 /* intr off means this is the last byte (end of frame) */ 595 if (cuda_intr_state(sc) == 0) { 596 ending = 1; 597 DPRINTF(".\n"); 598 } else { 599 cuda_toggle_ack(sc); 600 } 601 602 if (ending == 1) { /* end of message? */ 603 604 sc->sc_in[0] = sc->sc_received - 1; 605 606 /* reset vars and signal the end of this frame */ 607 cuda_idle(sc); 608 609 /* check if we have a handler for this message */ 610 type = sc->sc_in[1]; 611 if ((type >= 0) && (type < 16)) { 612 CudaHandler *me = &sc->sc_handlers[type]; 613 614 if (me->handler != NULL) { 615 me->handler(me->cookie, 616 sc->sc_received - 1, &sc->sc_in[1]); 617 } else { 618 aprint_error_dev(sc->sc_dev, 619 "no handler for type %02x\n", type); 620 panic("barf"); 621 } 622 } 623 624 DPRINTF("CUDA_IDLE"); 625 sc->sc_state = CUDA_IDLE; 626 627 sc->sc_received = 0; 628 629 /* 630 * If there is something waiting to be sent out, 631 * set everything up and send the first byte. 632 */ 633 if (sc->sc_waiting == 1) { 634 635 DPRINTF("pending write\n"); 636 delay(1500); /* required */ 637 sc->sc_sent = 0; 638 sc->sc_state = CUDA_OUT; 639 640 /* 641 * If the interrupt is on, we were too slow 642 * and the chip has already started to send 643 * something to us, so back out of the write 644 * and start a read cycle. 645 */ 646 if (cuda_intr_state(sc)) { 647 cuda_in(sc); 648 cuda_idle(sc); 649 sc->sc_sent = 0; 650 sc->sc_state = CUDA_IDLE; 651 sc->sc_received = 0; 652 delay(150); 653 DPRINTF("too slow - incoming message\n"); 654 goto switch_start; 655 } 656 /* 657 * If we got here, it's ok to start sending 658 * so load the first byte and tell the chip 659 * we want to send. 660 */ 661 DPRINTF("sending "); 662 663 cuda_out(sc); 664 cuda_write_reg(sc, vSR, 665 sc->sc_out[sc->sc_sent]); 666 cuda_ack_off(sc); 667 cuda_tip(sc); 668 } 669 } 670 break; 671 672 case CUDA_OUT: 673 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 674 675 sc->sc_sent++; 676 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 677 678 DPRINTF("incoming msg during send\n"); 679 cuda_in(sc); /* make sure SR is set to IN */ 680 cuda_idle(sc); 681 sc->sc_sent = 0; /* must start all over */ 682 sc->sc_state = CUDA_IDLE; /* new state */ 683 sc->sc_received = 0; 684 sc->sc_waiting = 1; /* must retry when done with 685 * read */ 686 delay(150); 687 goto switch_start; /* process next state right 688 * now */ 689 break; 690 } 691 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 692 693 sc->sc_waiting = 0; /* done writing */ 694 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 695 cuda_in(sc); 696 cuda_idle(sc); 697 DPRINTF("done sending\n"); 698 } else { 699 /* send next byte */ 700 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 701 DPRINTF("%02x", sc->sc_out[sc->sc_sent]); 702 cuda_toggle_ack(sc); /* signal byte ready to 703 * shift */ 704 } 705 break; 706 707 case CUDA_NOTREADY: 708 DPRINTF("adb: not yet initialized\n"); 709 break; 710 711 default: 712 DPRINTF("intr: unknown ADB state\n"); 713 break; 714 } 715 716 DPRINTF("]"); 717 return 1; 718 } 719 720 static int 721 cuda_error_handler(void *cookie, int len, uint8_t *data) 722 { 723 struct cuda_softc *sc = cookie; 724 725 /* 726 * something went wrong 727 * byte 3 seems to be the failed command 728 */ 729 sc->sc_error = 1; 730 wakeup(&sc->sc_todev); 731 return 0; 732 } 733 734 735 /* real time clock */ 736 737 static int 738 cuda_todr_handler(void *cookie, int len, uint8_t *data) 739 { 740 struct cuda_softc *sc = cookie; 741 742 #ifdef CUDA_DEBUG 743 int i; 744 printf("msg: %02x", data[0]); 745 for (i = 1; i < len; i++) { 746 printf(" %02x", data[i]); 747 } 748 printf("\n"); 749 #endif 750 751 switch(data[2]) { 752 case CMD_READ_RTC: 753 memcpy(&sc->sc_tod, &data[3], 4); 754 break; 755 case CMD_WRITE_RTC: 756 sc->sc_tod = 0xffffffff; 757 break; 758 case CMD_AUTOPOLL: 759 sc->sc_autopoll = 1; 760 break; 761 case CMD_IIC: 762 sc->sc_iic_done = len; 763 break; 764 } 765 wakeup(&sc->sc_todev); 766 return 0; 767 } 768 769 #define DIFF19041970 2082844800 770 771 static int 772 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp) 773 { 774 struct cuda_softc *sc = tch->cookie; 775 int cnt = 0; 776 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 777 778 sc->sc_tod = 0; 779 while (sc->sc_tod == 0) { 780 cuda_send(sc, 0, 2, cmd); 781 782 while ((sc->sc_tod == 0) && (cnt < 10)) { 783 tsleep(&sc->sc_todev, 0, "todr", 10); 784 cnt++; 785 } 786 787 if (sc->sc_tod == 0) { 788 aprint_error_dev(sc->sc_dev, 789 "unable to read a sane RTC value\n"); 790 return EIO; 791 } 792 if ((sc->sc_tod > 0xf0000000UL) || 793 (sc->sc_tod < DIFF19041970)) { 794 /* huh? try again */ 795 sc->sc_tod = 0; 796 aprint_verbose_dev(sc->sc_dev, 797 "got garbage reading RTC, trying again\n"); 798 } 799 } 800 801 tvp->tv_sec = sc->sc_tod - DIFF19041970; 802 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec); 803 tvp->tv_usec = 0; 804 return 0; 805 } 806 807 static int 808 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp) 809 { 810 struct cuda_softc *sc = tch->cookie; 811 uint32_t sec; 812 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 813 814 sec = tvp->tv_sec + DIFF19041970; 815 memcpy(&cmd[2], &sec, 4); 816 sc->sc_tod = 0; 817 if (cuda_send(sc, 0, 6, cmd) == 0) { 818 while (sc->sc_tod == 0) { 819 tsleep(&sc->sc_todev, 0, "todr", 10); 820 } 821 return 0; 822 } 823 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__); 824 return -1; 825 826 } 827 828 /* poweroff and reboot */ 829 830 void 831 cuda_poweroff(void) 832 { 833 struct cuda_softc *sc; 834 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 835 836 if (cuda0 == NULL) 837 return; 838 sc = cuda0->cookie; 839 sc->sc_polling = 1; 840 cuda0->poll(sc); 841 if (cuda0->send(sc, 1, 2, cmd) == 0) 842 while (1); 843 } 844 845 void 846 cuda_restart(void) 847 { 848 struct cuda_softc *sc; 849 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 850 851 if (cuda0 == NULL) 852 return; 853 sc = cuda0->cookie; 854 sc->sc_polling = 1; 855 cuda0->poll(sc); 856 if (cuda0->send(sc, 1, 2, cmd) == 0) 857 while (1); 858 } 859 860 /* ADB message handling */ 861 862 static void 863 cuda_autopoll(void *cookie, int flag) 864 { 865 struct cuda_softc *sc = cookie; 866 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 867 868 if (cmd[2] == sc->sc_autopoll) 869 return; 870 871 sc->sc_autopoll = -1; 872 cuda_send(sc, 0, 3, cmd); 873 while(sc->sc_autopoll == -1) { 874 if (sc->sc_polling || cold) { 875 cuda_poll(sc); 876 } else 877 tsleep(&sc->sc_todev, 0, "autopoll", 100); 878 } 879 } 880 881 static int 882 cuda_adb_handler(void *cookie, int len, uint8_t *data) 883 { 884 struct cuda_softc *sc = cookie; 885 886 if (sc->sc_adb_handler != NULL) { 887 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 888 &data[1]); 889 return 0; 890 } 891 return -1; 892 } 893 894 static int 895 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 896 { 897 struct cuda_softc *sc = cookie; 898 int i, s = 0; 899 uint8_t packet[16]; 900 901 /* construct an ADB command packet and send it */ 902 packet[0] = CUDA_ADB; 903 packet[1] = command; 904 for (i = 0; i < len; i++) 905 packet[i + 2] = data[i]; 906 if (poll || cold) { 907 s = splhigh(); 908 cuda_poll(sc); 909 } 910 cuda_send(sc, poll, len + 2, packet); 911 if (poll || cold) { 912 cuda_poll(sc); 913 splx(s); 914 } 915 return 0; 916 } 917 918 static int 919 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 920 void *hcookie) 921 { 922 struct cuda_softc *sc = cookie; 923 924 /* register a callback for incoming ADB messages */ 925 sc->sc_adb_handler = handler; 926 sc->sc_adb_cookie = hcookie; 927 return 0; 928 } 929 930 /* i2c message handling */ 931 932 static int 933 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 934 size_t send_len, void *_recv, size_t recv_len, int flags) 935 { 936 struct cuda_softc *sc = cookie; 937 const uint8_t *send = _send; 938 uint8_t *recv = _recv; 939 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 940 941 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 942 command[2] = addr; 943 944 /* Copy command and output data bytes, if any, to buffer */ 945 if (send_len > 0) 946 memcpy(&command[3], send, uimin((int)send_len, 12)); 947 else if (I2C_OP_READ_P(op) && (recv_len == 0)) { 948 /* 949 * If no data bytes in either direction, it's a "quick" 950 * i2c operation. We don't know how to do a quick_read 951 * since that requires us to set the low bit of the 952 * address byte after it has been left-shifted. 953 */ 954 sc->sc_error = 0; 955 return -1; 956 } 957 958 sc->sc_iic_done = 0; 959 cuda_send(sc, sc->sc_polling, send_len + 3, command); 960 961 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 962 if (sc->sc_polling || cold) { 963 cuda_poll(sc); 964 } else 965 tsleep(&sc->sc_todev, 0, "i2c", 1000); 966 } 967 968 if (sc->sc_error) { 969 sc->sc_error = 0; 970 aprint_error_dev(sc->sc_dev, "error doing I2C\n"); 971 return -1; 972 } 973 974 /* see if we're supposed to do a read */ 975 if (recv_len > 0) { 976 sc->sc_iic_done = 0; 977 command[2] |= 1; 978 command[3] = 0; 979 980 /* 981 * XXX we need to do something to limit the size of the answer 982 * - apparently the chip keeps sending until we tell it to stop 983 */ 984 sc->sc_i2c_read_len = recv_len; 985 DPRINTF("rcv_len: %d\n", recv_len); 986 cuda_send(sc, sc->sc_polling, 3, command); 987 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 988 if (sc->sc_polling || cold) { 989 cuda_poll(sc); 990 } else 991 tsleep(&sc->sc_todev, 0, "i2c", 1000); 992 } 993 994 if (sc->sc_error) { 995 aprint_error_dev(sc->sc_dev, 996 "error trying to read from I2C\n"); 997 sc->sc_error = 0; 998 return -1; 999 } 1000 } 1001 1002 DPRINTF("received: %d\n", sc->sc_iic_done); 1003 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 1004 int rlen; 1005 1006 /* we got an answer */ 1007 rlen = uimin(sc->sc_iic_done - 3, recv_len); 1008 memcpy(recv, &sc->sc_in[4], rlen); 1009 #ifdef CUDA_DEBUG 1010 { 1011 int i; 1012 printf("ret:"); 1013 for (i = 0; i < rlen; i++) 1014 printf(" %02x", recv[i]); 1015 printf("\n"); 1016 } 1017 #endif 1018 return rlen; 1019 } 1020 return 0; 1021 } 1022
Indexes created Wed Sep 24 05:09:52 GMT 2025