cuda.c revision 1.28
1 /* $NetBSD: cuda.c,v 1.28 2021/04/24 23:36:41 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.28 2021/04/24 23:36:41 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/mutex.h> 38 39 #include <sys/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 #include <dev/clock_subr.h> 43 #include <dev/i2c/i2cvar.h> 44 45 #include <macppc/dev/viareg.h> 46 #include <macppc/dev/cudavar.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/adb/adbvar.h> 50 #include "opt_cuda.h" 51 52 #ifdef CUDA_DEBUG 53 #define DPRINTF printf 54 #else 55 #define DPRINTF while (0) printf 56 #endif 57 58 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 59 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 60 #define CUDA_OUT 0x3 /* sending out a command */ 61 #define CUDA_IN 0x4 /* receiving data */ 62 #define CUDA_POLLING 0x5 /* polling - II only */ 63 64 static void cuda_attach(device_t, device_t, void *); 65 static int cuda_match(device_t, struct cfdata *, void *); 66 static void cuda_autopoll(void *, int); 67 68 static int cuda_intr(void *); 69 70 typedef struct _cuda_handler { 71 int (*handler)(void *, int, uint8_t *); 72 void *cookie; 73 } CudaHandler; 74 75 struct cuda_softc { 76 device_t sc_dev; 77 void *sc_ih; 78 CudaHandler sc_handlers[16]; 79 struct todr_chip_handle sc_todr; 80 struct adb_bus_accessops sc_adbops; 81 struct i2c_controller sc_i2c; 82 bus_space_tag_t sc_memt; 83 bus_space_handle_t sc_memh; 84 int sc_node; 85 int sc_state; 86 int sc_waiting; 87 int sc_polling; 88 int sc_sent; 89 int sc_out_length; 90 int sc_received; 91 int sc_iic_done; 92 int sc_error; 93 /* time */ 94 uint32_t sc_tod; 95 uint32_t sc_autopoll; 96 uint32_t sc_todev; 97 /* ADB */ 98 void (*sc_adb_handler)(void *, int, uint8_t *); 99 void *sc_adb_cookie; 100 uint32_t sc_i2c_read_len; 101 /* internal buffers */ 102 uint8_t sc_in[256]; 103 uint8_t sc_out[256]; 104 }; 105 106 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc), 107 cuda_match, cuda_attach, NULL, NULL); 108 109 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 110 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 111 static void cuda_idle(struct cuda_softc *); 112 static void cuda_tip(struct cuda_softc *); 113 static void cuda_clear_tip(struct cuda_softc *); 114 static void cuda_in(struct cuda_softc *); 115 static void cuda_out(struct cuda_softc *); 116 static void cuda_toggle_ack(struct cuda_softc *); 117 static void cuda_ack_off(struct cuda_softc *); 118 static int cuda_intr_state(struct cuda_softc *); 119 120 static void cuda_init(struct cuda_softc *); 121 122 /* 123 * send a message to Cuda. 124 */ 125 /* cookie, flags, length, data */ 126 static int cuda_send(void *, int, int, uint8_t *); 127 static void cuda_poll(void *); 128 static void cuda_adb_poll(void *); 129 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 130 131 static int cuda_error_handler(void *, int, uint8_t *); 132 133 static int cuda_todr_handler(void *, int, uint8_t *); 134 static int cuda_todr_set(todr_chip_handle_t, struct timeval *); 135 static int cuda_todr_get(todr_chip_handle_t, struct timeval *); 136 137 static int cuda_adb_handler(void *, int, uint8_t *); 138 static void cuda_final(device_t); 139 140 static struct cuda_attach_args *cuda0 = NULL; 141 142 /* ADB bus attachment stuff */ 143 static int cuda_adb_send(void *, int, int, int, uint8_t *); 144 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 145 146 /* i2c stuff */ 147 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 148 void *, size_t, int); 149 150 static int 151 cuda_match(device_t parent, struct cfdata *cf, void *aux) 152 { 153 struct confargs *ca = aux; 154 155 if (ca->ca_nreg < 8) 156 return 0; 157 158 if (ca->ca_nintr < 4) 159 return 0; 160 161 if (strcmp(ca->ca_name, "via-cuda") == 0) { 162 return 10; /* beat adb* at obio? */ 163 } 164 165 return 0; 166 } 167 168 static void 169 cuda_attach(device_t parent, device_t self, void *aux) 170 { 171 struct confargs *ca = aux; 172 struct cuda_softc *sc = device_private(self); 173 struct i2cbus_attach_args iba; 174 static struct cuda_attach_args caa; 175 prop_dictionary_t dict = device_properties(self); 176 prop_dictionary_t dev; 177 prop_array_t cfg; 178 int irq = ca->ca_intr[0]; 179 int node, i, child; 180 char name[32]; 181 182 sc->sc_dev = self; 183 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1"); 184 if (node) 185 OF_getprop(node, "interrupts", &irq, 4); 186 187 aprint_normal(" irq %d", irq); 188 189 sc->sc_node = ca->ca_node; 190 sc->sc_memt = ca->ca_tag; 191 192 sc->sc_sent = 0; 193 sc->sc_received = 0; 194 sc->sc_waiting = 0; 195 sc->sc_polling = 0; 196 sc->sc_state = CUDA_NOTREADY; 197 sc->sc_error = 0; 198 sc->sc_i2c_read_len = 0; 199 200 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 201 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 202 203 aprint_normal(": unable to map registers\n"); 204 return; 205 } 206 sc->sc_ih = intr_establish_xname(irq, IST_EDGE, IPL_TTY, cuda_intr, sc, 207 device_xname(self)); 208 printf("\n"); 209 210 for (i = 0; i < 16; i++) { 211 sc->sc_handlers[i].handler = NULL; 212 sc->sc_handlers[i].cookie = NULL; 213 } 214 215 cuda_init(sc); 216 217 /* now attach children */ 218 config_interrupts(self, cuda_final); 219 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 220 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 221 222 child = OF_child(ca->ca_node); 223 while (child != 0) { 224 225 if (OF_getprop(child, "name", name, 32) == 0) 226 continue; 227 if (strncmp(name, "adb", 4) == 0) { 228 229 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 230 sc->sc_adbops.cookie = sc; 231 sc->sc_adbops.send = cuda_adb_send; 232 sc->sc_adbops.poll = cuda_adb_poll; 233 sc->sc_adbops.autopoll = cuda_autopoll; 234 sc->sc_adbops.set_handler = cuda_adb_set_handler; 235 config_found(self, &sc->sc_adbops, nadb_print, 236 CFARG_IATTR, "adb_bus", 237 CFARG_EOL); 238 } else if (strncmp(name, "rtc", 4) == 0) { 239 240 sc->sc_todr.todr_gettime = cuda_todr_get; 241 sc->sc_todr.todr_settime = cuda_todr_set; 242 sc->sc_todr.cookie = sc; 243 todr_attach(&sc->sc_todr); 244 } 245 child = OF_peer(child); 246 } 247 248 caa.cookie = sc; 249 caa.set_handler = cuda_set_handler; 250 caa.send = cuda_send; 251 caa.poll = cuda_poll; 252 #if notyet 253 config_found(self, &caa, cuda_print, CFARG_EOL); 254 #endif 255 cfg = prop_array_create(); 256 prop_dictionary_set(dict, "i2c-child-devices", cfg); 257 prop_object_release(cfg); 258 259 /* we don't have OF nodes for i2c devices so we have to make our own */ 260 261 node = OF_finddevice("/valkyrie"); 262 if (node != -1) { 263 dev = prop_dictionary_create(); 264 prop_dictionary_set_string(dev, "name", "videopll"); 265 prop_dictionary_set_uint32(dev, "addr", 0x50); 266 prop_array_add(cfg, dev); 267 prop_object_release(dev); 268 } 269 270 node = OF_finddevice("/perch"); 271 if (node != -1) { 272 dev = prop_dictionary_create(); 273 prop_dictionary_set_string(dev, "name", "sgsmix"); 274 prop_dictionary_set_uint32(dev, "addr", 0x8a); 275 prop_array_add(cfg, dev); 276 prop_object_release(dev); 277 } 278 279 memset(&iba, 0, sizeof(iba)); 280 iba.iba_tag = &sc->sc_i2c; 281 iic_tag_init(&sc->sc_i2c); 282 sc->sc_i2c.ic_cookie = sc; 283 sc->sc_i2c.ic_exec = cuda_i2c_exec; 284 config_found(self, &iba, iicbus_print, 285 CFARG_IATTR, "i2cbus", 286 CFARG_EOL); 287 288 if (cuda0 == NULL) 289 cuda0 = &caa; 290 } 291 292 static void 293 cuda_init(struct cuda_softc *sc) 294 { 295 uint8_t reg; 296 297 reg = cuda_read_reg(sc, vDirB); 298 reg |= 0x30; /* register B bits 4 and 5: outputs */ 299 cuda_write_reg(sc, vDirB, reg); 300 301 reg = cuda_read_reg(sc, vDirB); 302 reg &= 0xf7; /* register B bit 3: input */ 303 cuda_write_reg(sc, vDirB, reg); 304 305 reg = cuda_read_reg(sc, vACR); 306 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 307 cuda_write_reg(sc, vACR, reg); 308 309 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 310 311 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 312 313 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 314 cuda_idle(sc); /* set ADB bus state to idle */ 315 316 /* sort of a device reset */ 317 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 318 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 319 cuda_idle(sc); /* reset state to idle */ 320 delay(150); 321 cuda_tip(sc); /* signal start of frame */ 322 delay(150); 323 cuda_toggle_ack(sc); 324 delay(150); 325 cuda_clear_tip(sc); 326 delay(150); 327 cuda_idle(sc); /* back to idle state */ 328 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 329 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 330 } 331 332 static void 333 cuda_final(device_t dev) 334 { 335 struct cuda_softc *sc = device_private(dev); 336 337 sc->sc_polling = 0; 338 } 339 340 static inline void 341 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 342 { 343 344 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 345 } 346 347 static inline uint8_t 348 cuda_read_reg(struct cuda_softc *sc, int offset) 349 { 350 351 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 352 } 353 354 static int 355 cuda_set_handler(void *cookie, int type, 356 int (*handler)(void *, int, uint8_t *), void *hcookie) 357 { 358 struct cuda_softc *sc = cookie; 359 CudaHandler *me; 360 361 if ((type >= 0) && (type < 16)) { 362 me = &sc->sc_handlers[type]; 363 me->handler = handler; 364 me->cookie = hcookie; 365 return 0; 366 } 367 return -1; 368 } 369 370 static int 371 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 372 { 373 struct cuda_softc *sc = cookie; 374 int s; 375 376 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 377 if (sc->sc_state == CUDA_NOTREADY) 378 return -1; 379 380 s = splhigh(); 381 382 if (sc->sc_state == CUDA_IDLE /*&& 383 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) { 384 /* fine */ 385 DPRINTF("chip is idle\n"); 386 } else { 387 DPRINTF("cuda state is %d\n", sc->sc_state); 388 if (sc->sc_waiting == 0) { 389 sc->sc_waiting = 1; 390 } else { 391 splx(s); 392 return -1; 393 } 394 } 395 396 sc->sc_error = 0; 397 memcpy(sc->sc_out, msg, length); 398 sc->sc_out_length = length; 399 sc->sc_sent = 0; 400 401 if (sc->sc_waiting != 1) { 402 403 delay(150); 404 sc->sc_state = CUDA_OUT; 405 cuda_out(sc); 406 cuda_write_reg(sc, vSR, sc->sc_out[0]); 407 cuda_ack_off(sc); 408 cuda_tip(sc); 409 } 410 sc->sc_waiting = 1; 411 412 if (sc->sc_polling || poll || cold) { 413 cuda_poll(sc); 414 } 415 416 splx(s); 417 418 return 0; 419 } 420 421 static void 422 cuda_poll(void *cookie) 423 { 424 struct cuda_softc *sc = cookie; 425 int s; 426 427 DPRINTF("polling\n"); 428 while ((sc->sc_state != CUDA_IDLE) || 429 (cuda_intr_state(sc)) || 430 (sc->sc_waiting == 1)) { 431 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 432 s = splhigh(); 433 cuda_intr(sc); 434 splx(s); 435 } 436 } 437 } 438 439 static void 440 cuda_adb_poll(void *cookie) 441 { 442 struct cuda_softc *sc = cookie; 443 int s; 444 445 s = splhigh(); 446 cuda_intr(sc); 447 splx(s); 448 } 449 450 static void 451 cuda_idle(struct cuda_softc *sc) 452 { 453 uint8_t reg; 454 455 reg = cuda_read_reg(sc, vBufB); 456 reg |= (vPB4 | vPB5); 457 cuda_write_reg(sc, vBufB, reg); 458 } 459 460 static void 461 cuda_tip(struct cuda_softc *sc) 462 { 463 uint8_t reg; 464 465 reg = cuda_read_reg(sc, vBufB); 466 reg &= ~vPB5; 467 cuda_write_reg(sc, vBufB, reg); 468 } 469 470 static void 471 cuda_clear_tip(struct cuda_softc *sc) 472 { 473 uint8_t reg; 474 475 reg = cuda_read_reg(sc, vBufB); 476 reg |= vPB5; 477 cuda_write_reg(sc, vBufB, reg); 478 } 479 480 static void 481 cuda_in(struct cuda_softc *sc) 482 { 483 uint8_t reg; 484 485 reg = cuda_read_reg(sc, vACR); 486 reg &= ~vSR_OUT; 487 cuda_write_reg(sc, vACR, reg); 488 } 489 490 static void 491 cuda_out(struct cuda_softc *sc) 492 { 493 uint8_t reg; 494 495 reg = cuda_read_reg(sc, vACR); 496 reg |= vSR_OUT; 497 cuda_write_reg(sc, vACR, reg); 498 } 499 500 static void 501 cuda_toggle_ack(struct cuda_softc *sc) 502 { 503 uint8_t reg; 504 505 reg = cuda_read_reg(sc, vBufB); 506 reg ^= vPB4; 507 cuda_write_reg(sc, vBufB, reg); 508 } 509 510 static void 511 cuda_ack_off(struct cuda_softc *sc) 512 { 513 uint8_t reg; 514 515 reg = cuda_read_reg(sc, vBufB); 516 reg |= vPB4; 517 cuda_write_reg(sc, vBufB, reg); 518 } 519 520 static int 521 cuda_intr_state(struct cuda_softc *sc) 522 { 523 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 524 } 525 526 static int 527 cuda_intr(void *arg) 528 { 529 struct cuda_softc *sc = arg; 530 int ending, type; 531 uint8_t reg; 532 533 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 534 DPRINTF("["); 535 if ((reg & 0x80) == 0) { 536 DPRINTF("irq %02x]", reg); 537 return 0; /* No interrupts to process */ 538 } 539 DPRINTF(":"); 540 541 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 542 543 switch_start: 544 switch (sc->sc_state) { 545 case CUDA_IDLE: 546 /* 547 * This is an unexpected packet, so grab the first (dummy) 548 * byte, set up the proper vars, and tell the chip we are 549 * starting to receive the packet by setting the TIP bit. 550 */ 551 sc->sc_in[1] = cuda_read_reg(sc, vSR); 552 DPRINTF("start: %02x", sc->sc_in[1]); 553 if (cuda_intr_state(sc) == 0) { 554 /* must have been a fake start */ 555 DPRINTF(" ... fake start\n"); 556 if (sc->sc_waiting) { 557 /* start over */ 558 delay(150); 559 sc->sc_state = CUDA_OUT; 560 sc->sc_sent = 0; 561 cuda_out(sc); 562 cuda_write_reg(sc, vSR, sc->sc_out[1]); 563 cuda_ack_off(sc); 564 cuda_tip(sc); 565 } 566 break; 567 } 568 569 cuda_in(sc); 570 cuda_tip(sc); 571 572 sc->sc_received = 1; 573 sc->sc_state = CUDA_IN; 574 DPRINTF(" CUDA_IN"); 575 break; 576 577 case CUDA_IN: 578 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 579 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 580 ending = 0; 581 if (sc->sc_received > 255) { 582 /* bitch only once */ 583 if (sc->sc_received == 256) { 584 aprint_error_dev(sc->sc_dev, 585 "input overflow\n"); 586 ending = 1; 587 } 588 } else 589 sc->sc_received++; 590 if (sc->sc_received > 3) { 591 if ((sc->sc_in[3] == CMD_IIC) && 592 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 593 ending = 1; 594 } 595 } 596 597 /* intr off means this is the last byte (end of frame) */ 598 if (cuda_intr_state(sc) == 0) { 599 ending = 1; 600 DPRINTF(".\n"); 601 } else { 602 cuda_toggle_ack(sc); 603 } 604 605 if (ending == 1) { /* end of message? */ 606 607 sc->sc_in[0] = sc->sc_received - 1; 608 609 /* reset vars and signal the end of this frame */ 610 cuda_idle(sc); 611 612 /* check if we have a handler for this message */ 613 type = sc->sc_in[1]; 614 if ((type >= 0) && (type < 16)) { 615 CudaHandler *me = &sc->sc_handlers[type]; 616 617 if (me->handler != NULL) { 618 me->handler(me->cookie, 619 sc->sc_received - 1, &sc->sc_in[1]); 620 } else { 621 aprint_error_dev(sc->sc_dev, 622 "no handler for type %02x\n", type); 623 panic("barf"); 624 } 625 } 626 627 DPRINTF("CUDA_IDLE"); 628 sc->sc_state = CUDA_IDLE; 629 630 sc->sc_received = 0; 631 632 /* 633 * If there is something waiting to be sent out, 634 * set everything up and send the first byte. 635 */ 636 if (sc->sc_waiting == 1) { 637 638 DPRINTF("pending write\n"); 639 delay(1500); /* required */ 640 sc->sc_sent = 0; 641 sc->sc_state = CUDA_OUT; 642 643 /* 644 * If the interrupt is on, we were too slow 645 * and the chip has already started to send 646 * something to us, so back out of the write 647 * and start a read cycle. 648 */ 649 if (cuda_intr_state(sc)) { 650 cuda_in(sc); 651 cuda_idle(sc); 652 sc->sc_sent = 0; 653 sc->sc_state = CUDA_IDLE; 654 sc->sc_received = 0; 655 delay(150); 656 DPRINTF("too slow - incoming message\n"); 657 goto switch_start; 658 } 659 /* 660 * If we got here, it's ok to start sending 661 * so load the first byte and tell the chip 662 * we want to send. 663 */ 664 DPRINTF("sending "); 665 666 cuda_out(sc); 667 cuda_write_reg(sc, vSR, 668 sc->sc_out[sc->sc_sent]); 669 cuda_ack_off(sc); 670 cuda_tip(sc); 671 } 672 } 673 break; 674 675 case CUDA_OUT: 676 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 677 678 sc->sc_sent++; 679 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 680 681 DPRINTF("incoming msg during send\n"); 682 cuda_in(sc); /* make sure SR is set to IN */ 683 cuda_idle(sc); 684 sc->sc_sent = 0; /* must start all over */ 685 sc->sc_state = CUDA_IDLE; /* new state */ 686 sc->sc_received = 0; 687 sc->sc_waiting = 1; /* must retry when done with 688 * read */ 689 delay(150); 690 goto switch_start; /* process next state right 691 * now */ 692 break; 693 } 694 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 695 696 sc->sc_waiting = 0; /* done writing */ 697 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 698 cuda_in(sc); 699 cuda_idle(sc); 700 DPRINTF("done sending\n"); 701 } else { 702 /* send next byte */ 703 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 704 DPRINTF("%02x", sc->sc_out[sc->sc_sent]); 705 cuda_toggle_ack(sc); /* signal byte ready to 706 * shift */ 707 } 708 break; 709 710 case CUDA_NOTREADY: 711 DPRINTF("adb: not yet initialized\n"); 712 break; 713 714 default: 715 DPRINTF("intr: unknown ADB state\n"); 716 break; 717 } 718 719 DPRINTF("]"); 720 return 1; 721 } 722 723 static int 724 cuda_error_handler(void *cookie, int len, uint8_t *data) 725 { 726 struct cuda_softc *sc = cookie; 727 728 /* 729 * something went wrong 730 * byte 3 seems to be the failed command 731 */ 732 sc->sc_error = 1; 733 wakeup(&sc->sc_todev); 734 return 0; 735 } 736 737 738 /* real time clock */ 739 740 static int 741 cuda_todr_handler(void *cookie, int len, uint8_t *data) 742 { 743 struct cuda_softc *sc = cookie; 744 745 #ifdef CUDA_DEBUG 746 int i; 747 printf("msg: %02x", data[0]); 748 for (i = 1; i < len; i++) { 749 printf(" %02x", data[i]); 750 } 751 printf("\n"); 752 #endif 753 754 switch(data[2]) { 755 case CMD_READ_RTC: 756 memcpy(&sc->sc_tod, &data[3], 4); 757 break; 758 case CMD_WRITE_RTC: 759 sc->sc_tod = 0xffffffff; 760 break; 761 case CMD_AUTOPOLL: 762 sc->sc_autopoll = 1; 763 break; 764 case CMD_IIC: 765 sc->sc_iic_done = len; 766 break; 767 } 768 wakeup(&sc->sc_todev); 769 return 0; 770 } 771 772 #define DIFF19041970 2082844800 773 774 static int 775 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp) 776 { 777 struct cuda_softc *sc = tch->cookie; 778 int cnt = 0; 779 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 780 781 sc->sc_tod = 0; 782 while (sc->sc_tod == 0) { 783 cuda_send(sc, 0, 2, cmd); 784 785 while ((sc->sc_tod == 0) && (cnt < 10)) { 786 tsleep(&sc->sc_todev, 0, "todr", 10); 787 cnt++; 788 } 789 790 if (sc->sc_tod == 0) { 791 aprint_error_dev(sc->sc_dev, 792 "unable to read a sane RTC value\n"); 793 return EIO; 794 } 795 if ((sc->sc_tod > 0xf0000000UL) || 796 (sc->sc_tod < DIFF19041970)) { 797 /* huh? try again */ 798 sc->sc_tod = 0; 799 aprint_verbose_dev(sc->sc_dev, 800 "got garbage reading RTC, trying again\n"); 801 } 802 } 803 804 tvp->tv_sec = sc->sc_tod - DIFF19041970; 805 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec); 806 tvp->tv_usec = 0; 807 return 0; 808 } 809 810 static int 811 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp) 812 { 813 struct cuda_softc *sc = tch->cookie; 814 uint32_t sec; 815 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 816 817 sec = tvp->tv_sec + DIFF19041970; 818 memcpy(&cmd[2], &sec, 4); 819 sc->sc_tod = 0; 820 if (cuda_send(sc, 0, 6, cmd) == 0) { 821 while (sc->sc_tod == 0) { 822 tsleep(&sc->sc_todev, 0, "todr", 10); 823 } 824 return 0; 825 } 826 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__); 827 return -1; 828 829 } 830 831 /* poweroff and reboot */ 832 833 void 834 cuda_poweroff(void) 835 { 836 struct cuda_softc *sc; 837 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 838 839 if (cuda0 == NULL) 840 return; 841 sc = cuda0->cookie; 842 sc->sc_polling = 1; 843 cuda0->poll(sc); 844 if (cuda0->send(sc, 1, 2, cmd) == 0) 845 while (1); 846 } 847 848 void 849 cuda_restart(void) 850 { 851 struct cuda_softc *sc; 852 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 853 854 if (cuda0 == NULL) 855 return; 856 sc = cuda0->cookie; 857 sc->sc_polling = 1; 858 cuda0->poll(sc); 859 if (cuda0->send(sc, 1, 2, cmd) == 0) 860 while (1); 861 } 862 863 /* ADB message handling */ 864 865 static void 866 cuda_autopoll(void *cookie, int flag) 867 { 868 struct cuda_softc *sc = cookie; 869 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 870 871 if (cmd[2] == sc->sc_autopoll) 872 return; 873 874 sc->sc_autopoll = -1; 875 cuda_send(sc, 0, 3, cmd); 876 while(sc->sc_autopoll == -1) { 877 if (sc->sc_polling || cold) { 878 cuda_poll(sc); 879 } else 880 tsleep(&sc->sc_todev, 0, "autopoll", 100); 881 } 882 } 883 884 static int 885 cuda_adb_handler(void *cookie, int len, uint8_t *data) 886 { 887 struct cuda_softc *sc = cookie; 888 889 if (sc->sc_adb_handler != NULL) { 890 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 891 &data[1]); 892 return 0; 893 } 894 return -1; 895 } 896 897 static int 898 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 899 { 900 struct cuda_softc *sc = cookie; 901 int i, s = 0; 902 uint8_t packet[16]; 903 904 /* construct an ADB command packet and send it */ 905 packet[0] = CUDA_ADB; 906 packet[1] = command; 907 for (i = 0; i < len; i++) 908 packet[i + 2] = data[i]; 909 if (poll || cold) { 910 s = splhigh(); 911 cuda_poll(sc); 912 } 913 cuda_send(sc, poll, len + 2, packet); 914 if (poll || cold) { 915 cuda_poll(sc); 916 splx(s); 917 } 918 return 0; 919 } 920 921 static int 922 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 923 void *hcookie) 924 { 925 struct cuda_softc *sc = cookie; 926 927 /* register a callback for incoming ADB messages */ 928 sc->sc_adb_handler = handler; 929 sc->sc_adb_cookie = hcookie; 930 return 0; 931 } 932 933 /* i2c message handling */ 934 935 static int 936 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 937 size_t send_len, void *_recv, size_t recv_len, int flags) 938 { 939 struct cuda_softc *sc = cookie; 940 const uint8_t *send = _send; 941 uint8_t *recv = _recv; 942 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 943 944 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 945 command[2] = addr; 946 947 /* Copy command and output data bytes, if any, to buffer */ 948 if (send_len > 0) 949 memcpy(&command[3], send, uimin((int)send_len, 12)); 950 else if (I2C_OP_READ_P(op) && (recv_len == 0)) { 951 /* 952 * If no data bytes in either direction, it's a "quick" 953 * i2c operation. We don't know how to do a quick_read 954 * since that requires us to set the low bit of the 955 * address byte after it has been left-shifted. 956 */ 957 sc->sc_error = 0; 958 return -1; 959 } 960 961 sc->sc_iic_done = 0; 962 cuda_send(sc, sc->sc_polling, send_len + 3, command); 963 964 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 965 if (sc->sc_polling || cold) { 966 cuda_poll(sc); 967 } else 968 tsleep(&sc->sc_todev, 0, "i2c", 1000); 969 } 970 971 if (sc->sc_error) { 972 sc->sc_error = 0; 973 aprint_error_dev(sc->sc_dev, "error doing I2C\n"); 974 return -1; 975 } 976 977 /* see if we're supposed to do a read */ 978 if (recv_len > 0) { 979 sc->sc_iic_done = 0; 980 command[2] |= 1; 981 command[3] = 0; 982 983 /* 984 * XXX we need to do something to limit the size of the answer 985 * - apparently the chip keeps sending until we tell it to stop 986 */ 987 sc->sc_i2c_read_len = recv_len; 988 DPRINTF("rcv_len: %d\n", recv_len); 989 cuda_send(sc, sc->sc_polling, 3, command); 990 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 991 if (sc->sc_polling || cold) { 992 cuda_poll(sc); 993 } else 994 tsleep(&sc->sc_todev, 0, "i2c", 1000); 995 } 996 997 if (sc->sc_error) { 998 aprint_error_dev(sc->sc_dev, 999 "error trying to read from I2C\n"); 1000 sc->sc_error = 0; 1001 return -1; 1002 } 1003 } 1004 1005 DPRINTF("received: %d\n", sc->sc_iic_done); 1006 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 1007 int rlen; 1008 1009 /* we got an answer */ 1010 rlen = uimin(sc->sc_iic_done - 3, recv_len); 1011 memcpy(recv, &sc->sc_in[4], rlen); 1012 #ifdef CUDA_DEBUG 1013 { 1014 int i; 1015 printf("ret:"); 1016 for (i = 0; i < rlen; i++) 1017 printf(" %02x", recv[i]); 1018 printf("\n"); 1019 } 1020 #endif 1021 return rlen; 1022 } 1023 return 0; 1024 } 1025
Indexes created Tue Sep 23 23:09:58 GMT 2025