cuda.c revision 1.29
1 /* $NetBSD: cuda.c,v 1.29 2021/08/07 16:18:57 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.29 2021/08/07 16:18:57 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/mutex.h> 38 39 #include <sys/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 #include <dev/clock_subr.h> 43 #include <dev/i2c/i2cvar.h> 44 45 #include <macppc/dev/viareg.h> 46 #include <macppc/dev/cudavar.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/adb/adbvar.h> 50 #include "opt_cuda.h" 51 52 #ifdef CUDA_DEBUG 53 #define DPRINTF printf 54 #else 55 #define DPRINTF while (0) printf 56 #endif 57 58 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 59 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 60 #define CUDA_OUT 0x3 /* sending out a command */ 61 #define CUDA_IN 0x4 /* receiving data */ 62 #define CUDA_POLLING 0x5 /* polling - II only */ 63 64 static void cuda_attach(device_t, device_t, void *); 65 static int cuda_match(device_t, struct cfdata *, void *); 66 static void cuda_autopoll(void *, int); 67 68 static int cuda_intr(void *); 69 70 typedef struct _cuda_handler { 71 int (*handler)(void *, int, uint8_t *); 72 void *cookie; 73 } CudaHandler; 74 75 struct cuda_softc { 76 device_t sc_dev; 77 void *sc_ih; 78 CudaHandler sc_handlers[16]; 79 struct todr_chip_handle sc_todr; 80 struct adb_bus_accessops sc_adbops; 81 struct i2c_controller sc_i2c; 82 bus_space_tag_t sc_memt; 83 bus_space_handle_t sc_memh; 84 int sc_node; 85 int sc_state; 86 int sc_waiting; 87 int sc_polling; 88 int sc_sent; 89 int sc_out_length; 90 int sc_received; 91 int sc_iic_done; 92 int sc_error; 93 /* time */ 94 uint32_t sc_tod; 95 uint32_t sc_autopoll; 96 uint32_t sc_todev; 97 /* ADB */ 98 void (*sc_adb_handler)(void *, int, uint8_t *); 99 void *sc_adb_cookie; 100 uint32_t sc_i2c_read_len; 101 /* internal buffers */ 102 uint8_t sc_in[256]; 103 uint8_t sc_out[256]; 104 }; 105 106 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc), 107 cuda_match, cuda_attach, NULL, NULL); 108 109 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 110 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 111 static void cuda_idle(struct cuda_softc *); 112 static void cuda_tip(struct cuda_softc *); 113 static void cuda_clear_tip(struct cuda_softc *); 114 static void cuda_in(struct cuda_softc *); 115 static void cuda_out(struct cuda_softc *); 116 static void cuda_toggle_ack(struct cuda_softc *); 117 static void cuda_ack_off(struct cuda_softc *); 118 static int cuda_intr_state(struct cuda_softc *); 119 120 static void cuda_init(struct cuda_softc *); 121 122 /* 123 * send a message to Cuda. 124 */ 125 /* cookie, flags, length, data */ 126 static int cuda_send(void *, int, int, uint8_t *); 127 static void cuda_poll(void *); 128 static void cuda_adb_poll(void *); 129 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 130 131 static int cuda_error_handler(void *, int, uint8_t *); 132 133 static int cuda_todr_handler(void *, int, uint8_t *); 134 static int cuda_todr_set(todr_chip_handle_t, struct timeval *); 135 static int cuda_todr_get(todr_chip_handle_t, struct timeval *); 136 137 static int cuda_adb_handler(void *, int, uint8_t *); 138 static void cuda_final(device_t); 139 140 static struct cuda_attach_args *cuda0 = NULL; 141 142 /* ADB bus attachment stuff */ 143 static int cuda_adb_send(void *, int, int, int, uint8_t *); 144 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 145 146 /* i2c stuff */ 147 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 148 void *, size_t, int); 149 150 static int 151 cuda_match(device_t parent, struct cfdata *cf, void *aux) 152 { 153 struct confargs *ca = aux; 154 155 if (ca->ca_nreg < 8) 156 return 0; 157 158 if (ca->ca_nintr < 4) 159 return 0; 160 161 if (strcmp(ca->ca_name, "via-cuda") == 0) { 162 return 10; /* beat adb* at obio? */ 163 } 164 165 return 0; 166 } 167 168 static void 169 cuda_attach(device_t parent, device_t self, void *aux) 170 { 171 struct confargs *ca = aux; 172 struct cuda_softc *sc = device_private(self); 173 struct i2cbus_attach_args iba; 174 static struct cuda_attach_args caa; 175 prop_dictionary_t dict = device_properties(self); 176 prop_dictionary_t dev; 177 prop_array_t cfg; 178 int irq = ca->ca_intr[0]; 179 int node, i, child; 180 char name[32]; 181 182 sc->sc_dev = self; 183 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1"); 184 if (node) 185 OF_getprop(node, "interrupts", &irq, 4); 186 187 aprint_normal(" irq %d", irq); 188 189 sc->sc_node = ca->ca_node; 190 sc->sc_memt = ca->ca_tag; 191 192 sc->sc_sent = 0; 193 sc->sc_received = 0; 194 sc->sc_waiting = 0; 195 sc->sc_polling = 0; 196 sc->sc_state = CUDA_NOTREADY; 197 sc->sc_error = 0; 198 sc->sc_i2c_read_len = 0; 199 200 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 201 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 202 203 aprint_normal(": unable to map registers\n"); 204 return; 205 } 206 sc->sc_ih = intr_establish_xname(irq, IST_EDGE, IPL_TTY, cuda_intr, sc, 207 device_xname(self)); 208 printf("\n"); 209 210 for (i = 0; i < 16; i++) { 211 sc->sc_handlers[i].handler = NULL; 212 sc->sc_handlers[i].cookie = NULL; 213 } 214 215 cuda_init(sc); 216 217 /* now attach children */ 218 config_interrupts(self, cuda_final); 219 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 220 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 221 222 child = OF_child(ca->ca_node); 223 while (child != 0) { 224 225 if (OF_getprop(child, "name", name, 32) == 0) 226 continue; 227 if (strncmp(name, "adb", 4) == 0) { 228 229 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 230 sc->sc_adbops.cookie = sc; 231 sc->sc_adbops.send = cuda_adb_send; 232 sc->sc_adbops.poll = cuda_adb_poll; 233 sc->sc_adbops.autopoll = cuda_autopoll; 234 sc->sc_adbops.set_handler = cuda_adb_set_handler; 235 config_found(self, &sc->sc_adbops, nadb_print, 236 CFARGS(.iattr = "adb_bus")); 237 } else if (strncmp(name, "rtc", 4) == 0) { 238 239 sc->sc_todr.todr_gettime = cuda_todr_get; 240 sc->sc_todr.todr_settime = cuda_todr_set; 241 sc->sc_todr.cookie = sc; 242 todr_attach(&sc->sc_todr); 243 } 244 child = OF_peer(child); 245 } 246 247 caa.cookie = sc; 248 caa.set_handler = cuda_set_handler; 249 caa.send = cuda_send; 250 caa.poll = cuda_poll; 251 #if notyet 252 config_found(self, &caa, cuda_print, CFARGS_NONE); 253 #endif 254 cfg = prop_array_create(); 255 prop_dictionary_set(dict, "i2c-child-devices", cfg); 256 prop_object_release(cfg); 257 258 /* we don't have OF nodes for i2c devices so we have to make our own */ 259 260 node = OF_finddevice("/valkyrie"); 261 if (node != -1) { 262 dev = prop_dictionary_create(); 263 prop_dictionary_set_string(dev, "name", "videopll"); 264 prop_dictionary_set_uint32(dev, "addr", 0x50); 265 prop_array_add(cfg, dev); 266 prop_object_release(dev); 267 } 268 269 node = OF_finddevice("/perch"); 270 if (node != -1) { 271 dev = prop_dictionary_create(); 272 prop_dictionary_set_string(dev, "name", "sgsmix"); 273 prop_dictionary_set_uint32(dev, "addr", 0x8a); 274 prop_array_add(cfg, dev); 275 prop_object_release(dev); 276 } 277 278 memset(&iba, 0, sizeof(iba)); 279 iba.iba_tag = &sc->sc_i2c; 280 iic_tag_init(&sc->sc_i2c); 281 sc->sc_i2c.ic_cookie = sc; 282 sc->sc_i2c.ic_exec = cuda_i2c_exec; 283 config_found(self, &iba, iicbus_print, 284 CFARGS(.iattr = "i2cbus")); 285 286 if (cuda0 == NULL) 287 cuda0 = &caa; 288 } 289 290 static void 291 cuda_init(struct cuda_softc *sc) 292 { 293 uint8_t reg; 294 295 reg = cuda_read_reg(sc, vDirB); 296 reg |= 0x30; /* register B bits 4 and 5: outputs */ 297 cuda_write_reg(sc, vDirB, reg); 298 299 reg = cuda_read_reg(sc, vDirB); 300 reg &= 0xf7; /* register B bit 3: input */ 301 cuda_write_reg(sc, vDirB, reg); 302 303 reg = cuda_read_reg(sc, vACR); 304 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 305 cuda_write_reg(sc, vACR, reg); 306 307 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 308 309 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 310 311 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 312 cuda_idle(sc); /* set ADB bus state to idle */ 313 314 /* sort of a device reset */ 315 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 316 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 317 cuda_idle(sc); /* reset state to idle */ 318 delay(150); 319 cuda_tip(sc); /* signal start of frame */ 320 delay(150); 321 cuda_toggle_ack(sc); 322 delay(150); 323 cuda_clear_tip(sc); 324 delay(150); 325 cuda_idle(sc); /* back to idle state */ 326 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 327 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 328 } 329 330 static void 331 cuda_final(device_t dev) 332 { 333 struct cuda_softc *sc = device_private(dev); 334 335 sc->sc_polling = 0; 336 } 337 338 static inline void 339 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 340 { 341 342 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 343 } 344 345 static inline uint8_t 346 cuda_read_reg(struct cuda_softc *sc, int offset) 347 { 348 349 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 350 } 351 352 static int 353 cuda_set_handler(void *cookie, int type, 354 int (*handler)(void *, int, uint8_t *), void *hcookie) 355 { 356 struct cuda_softc *sc = cookie; 357 CudaHandler *me; 358 359 if ((type >= 0) && (type < 16)) { 360 me = &sc->sc_handlers[type]; 361 me->handler = handler; 362 me->cookie = hcookie; 363 return 0; 364 } 365 return -1; 366 } 367 368 static int 369 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 370 { 371 struct cuda_softc *sc = cookie; 372 int s; 373 374 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 375 if (sc->sc_state == CUDA_NOTREADY) 376 return -1; 377 378 s = splhigh(); 379 380 if (sc->sc_state == CUDA_IDLE /*&& 381 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) { 382 /* fine */ 383 DPRINTF("chip is idle\n"); 384 } else { 385 DPRINTF("cuda state is %d\n", sc->sc_state); 386 if (sc->sc_waiting == 0) { 387 sc->sc_waiting = 1; 388 } else { 389 splx(s); 390 return -1; 391 } 392 } 393 394 sc->sc_error = 0; 395 memcpy(sc->sc_out, msg, length); 396 sc->sc_out_length = length; 397 sc->sc_sent = 0; 398 399 if (sc->sc_waiting != 1) { 400 401 delay(150); 402 sc->sc_state = CUDA_OUT; 403 cuda_out(sc); 404 cuda_write_reg(sc, vSR, sc->sc_out[0]); 405 cuda_ack_off(sc); 406 cuda_tip(sc); 407 } 408 sc->sc_waiting = 1; 409 410 if (sc->sc_polling || poll || cold) { 411 cuda_poll(sc); 412 } 413 414 splx(s); 415 416 return 0; 417 } 418 419 static void 420 cuda_poll(void *cookie) 421 { 422 struct cuda_softc *sc = cookie; 423 int s; 424 425 DPRINTF("polling\n"); 426 while ((sc->sc_state != CUDA_IDLE) || 427 (cuda_intr_state(sc)) || 428 (sc->sc_waiting == 1)) { 429 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 430 s = splhigh(); 431 cuda_intr(sc); 432 splx(s); 433 } 434 } 435 } 436 437 static void 438 cuda_adb_poll(void *cookie) 439 { 440 struct cuda_softc *sc = cookie; 441 int s; 442 443 s = splhigh(); 444 cuda_intr(sc); 445 splx(s); 446 } 447 448 static void 449 cuda_idle(struct cuda_softc *sc) 450 { 451 uint8_t reg; 452 453 reg = cuda_read_reg(sc, vBufB); 454 reg |= (vPB4 | vPB5); 455 cuda_write_reg(sc, vBufB, reg); 456 } 457 458 static void 459 cuda_tip(struct cuda_softc *sc) 460 { 461 uint8_t reg; 462 463 reg = cuda_read_reg(sc, vBufB); 464 reg &= ~vPB5; 465 cuda_write_reg(sc, vBufB, reg); 466 } 467 468 static void 469 cuda_clear_tip(struct cuda_softc *sc) 470 { 471 uint8_t reg; 472 473 reg = cuda_read_reg(sc, vBufB); 474 reg |= vPB5; 475 cuda_write_reg(sc, vBufB, reg); 476 } 477 478 static void 479 cuda_in(struct cuda_softc *sc) 480 { 481 uint8_t reg; 482 483 reg = cuda_read_reg(sc, vACR); 484 reg &= ~vSR_OUT; 485 cuda_write_reg(sc, vACR, reg); 486 } 487 488 static void 489 cuda_out(struct cuda_softc *sc) 490 { 491 uint8_t reg; 492 493 reg = cuda_read_reg(sc, vACR); 494 reg |= vSR_OUT; 495 cuda_write_reg(sc, vACR, reg); 496 } 497 498 static void 499 cuda_toggle_ack(struct cuda_softc *sc) 500 { 501 uint8_t reg; 502 503 reg = cuda_read_reg(sc, vBufB); 504 reg ^= vPB4; 505 cuda_write_reg(sc, vBufB, reg); 506 } 507 508 static void 509 cuda_ack_off(struct cuda_softc *sc) 510 { 511 uint8_t reg; 512 513 reg = cuda_read_reg(sc, vBufB); 514 reg |= vPB4; 515 cuda_write_reg(sc, vBufB, reg); 516 } 517 518 static int 519 cuda_intr_state(struct cuda_softc *sc) 520 { 521 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 522 } 523 524 static int 525 cuda_intr(void *arg) 526 { 527 struct cuda_softc *sc = arg; 528 int ending, type; 529 uint8_t reg; 530 531 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 532 DPRINTF("["); 533 if ((reg & 0x80) == 0) { 534 DPRINTF("irq %02x]", reg); 535 return 0; /* No interrupts to process */ 536 } 537 DPRINTF(":"); 538 539 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 540 541 switch_start: 542 switch (sc->sc_state) { 543 case CUDA_IDLE: 544 /* 545 * This is an unexpected packet, so grab the first (dummy) 546 * byte, set up the proper vars, and tell the chip we are 547 * starting to receive the packet by setting the TIP bit. 548 */ 549 sc->sc_in[1] = cuda_read_reg(sc, vSR); 550 DPRINTF("start: %02x", sc->sc_in[1]); 551 if (cuda_intr_state(sc) == 0) { 552 /* must have been a fake start */ 553 DPRINTF(" ... fake start\n"); 554 if (sc->sc_waiting) { 555 /* start over */ 556 delay(150); 557 sc->sc_state = CUDA_OUT; 558 sc->sc_sent = 0; 559 cuda_out(sc); 560 cuda_write_reg(sc, vSR, sc->sc_out[1]); 561 cuda_ack_off(sc); 562 cuda_tip(sc); 563 } 564 break; 565 } 566 567 cuda_in(sc); 568 cuda_tip(sc); 569 570 sc->sc_received = 1; 571 sc->sc_state = CUDA_IN; 572 DPRINTF(" CUDA_IN"); 573 break; 574 575 case CUDA_IN: 576 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 577 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 578 ending = 0; 579 if (sc->sc_received > 255) { 580 /* bitch only once */ 581 if (sc->sc_received == 256) { 582 aprint_error_dev(sc->sc_dev, 583 "input overflow\n"); 584 ending = 1; 585 } 586 } else 587 sc->sc_received++; 588 if (sc->sc_received > 3) { 589 if ((sc->sc_in[3] == CMD_IIC) && 590 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 591 ending = 1; 592 } 593 } 594 595 /* intr off means this is the last byte (end of frame) */ 596 if (cuda_intr_state(sc) == 0) { 597 ending = 1; 598 DPRINTF(".\n"); 599 } else { 600 cuda_toggle_ack(sc); 601 } 602 603 if (ending == 1) { /* end of message? */ 604 605 sc->sc_in[0] = sc->sc_received - 1; 606 607 /* reset vars and signal the end of this frame */ 608 cuda_idle(sc); 609 610 /* check if we have a handler for this message */ 611 type = sc->sc_in[1]; 612 if ((type >= 0) && (type < 16)) { 613 CudaHandler *me = &sc->sc_handlers[type]; 614 615 if (me->handler != NULL) { 616 me->handler(me->cookie, 617 sc->sc_received - 1, &sc->sc_in[1]); 618 } else { 619 aprint_error_dev(sc->sc_dev, 620 "no handler for type %02x\n", type); 621 panic("barf"); 622 } 623 } 624 625 DPRINTF("CUDA_IDLE"); 626 sc->sc_state = CUDA_IDLE; 627 628 sc->sc_received = 0; 629 630 /* 631 * If there is something waiting to be sent out, 632 * set everything up and send the first byte. 633 */ 634 if (sc->sc_waiting == 1) { 635 636 DPRINTF("pending write\n"); 637 delay(1500); /* required */ 638 sc->sc_sent = 0; 639 sc->sc_state = CUDA_OUT; 640 641 /* 642 * If the interrupt is on, we were too slow 643 * and the chip has already started to send 644 * something to us, so back out of the write 645 * and start a read cycle. 646 */ 647 if (cuda_intr_state(sc)) { 648 cuda_in(sc); 649 cuda_idle(sc); 650 sc->sc_sent = 0; 651 sc->sc_state = CUDA_IDLE; 652 sc->sc_received = 0; 653 delay(150); 654 DPRINTF("too slow - incoming message\n"); 655 goto switch_start; 656 } 657 /* 658 * If we got here, it's ok to start sending 659 * so load the first byte and tell the chip 660 * we want to send. 661 */ 662 DPRINTF("sending "); 663 664 cuda_out(sc); 665 cuda_write_reg(sc, vSR, 666 sc->sc_out[sc->sc_sent]); 667 cuda_ack_off(sc); 668 cuda_tip(sc); 669 } 670 } 671 break; 672 673 case CUDA_OUT: 674 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 675 676 sc->sc_sent++; 677 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 678 679 DPRINTF("incoming msg during send\n"); 680 cuda_in(sc); /* make sure SR is set to IN */ 681 cuda_idle(sc); 682 sc->sc_sent = 0; /* must start all over */ 683 sc->sc_state = CUDA_IDLE; /* new state */ 684 sc->sc_received = 0; 685 sc->sc_waiting = 1; /* must retry when done with 686 * read */ 687 delay(150); 688 goto switch_start; /* process next state right 689 * now */ 690 break; 691 } 692 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 693 694 sc->sc_waiting = 0; /* done writing */ 695 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 696 cuda_in(sc); 697 cuda_idle(sc); 698 DPRINTF("done sending\n"); 699 } else { 700 /* send next byte */ 701 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 702 DPRINTF("%02x", sc->sc_out[sc->sc_sent]); 703 cuda_toggle_ack(sc); /* signal byte ready to 704 * shift */ 705 } 706 break; 707 708 case CUDA_NOTREADY: 709 DPRINTF("adb: not yet initialized\n"); 710 break; 711 712 default: 713 DPRINTF("intr: unknown ADB state\n"); 714 break; 715 } 716 717 DPRINTF("]"); 718 return 1; 719 } 720 721 static int 722 cuda_error_handler(void *cookie, int len, uint8_t *data) 723 { 724 struct cuda_softc *sc = cookie; 725 726 /* 727 * something went wrong 728 * byte 3 seems to be the failed command 729 */ 730 sc->sc_error = 1; 731 wakeup(&sc->sc_todev); 732 return 0; 733 } 734 735 736 /* real time clock */ 737 738 static int 739 cuda_todr_handler(void *cookie, int len, uint8_t *data) 740 { 741 struct cuda_softc *sc = cookie; 742 743 #ifdef CUDA_DEBUG 744 int i; 745 printf("msg: %02x", data[0]); 746 for (i = 1; i < len; i++) { 747 printf(" %02x", data[i]); 748 } 749 printf("\n"); 750 #endif 751 752 switch(data[2]) { 753 case CMD_READ_RTC: 754 memcpy(&sc->sc_tod, &data[3], 4); 755 break; 756 case CMD_WRITE_RTC: 757 sc->sc_tod = 0xffffffff; 758 break; 759 case CMD_AUTOPOLL: 760 sc->sc_autopoll = 1; 761 break; 762 case CMD_IIC: 763 sc->sc_iic_done = len; 764 break; 765 } 766 wakeup(&sc->sc_todev); 767 return 0; 768 } 769 770 #define DIFF19041970 2082844800 771 772 static int 773 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp) 774 { 775 struct cuda_softc *sc = tch->cookie; 776 int cnt = 0; 777 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 778 779 sc->sc_tod = 0; 780 while (sc->sc_tod == 0) { 781 cuda_send(sc, 0, 2, cmd); 782 783 while ((sc->sc_tod == 0) && (cnt < 10)) { 784 tsleep(&sc->sc_todev, 0, "todr", 10); 785 cnt++; 786 } 787 788 if (sc->sc_tod == 0) { 789 aprint_error_dev(sc->sc_dev, 790 "unable to read a sane RTC value\n"); 791 return EIO; 792 } 793 if ((sc->sc_tod > 0xf0000000UL) || 794 (sc->sc_tod < DIFF19041970)) { 795 /* huh? try again */ 796 sc->sc_tod = 0; 797 aprint_verbose_dev(sc->sc_dev, 798 "got garbage reading RTC, trying again\n"); 799 } 800 } 801 802 tvp->tv_sec = sc->sc_tod - DIFF19041970; 803 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec); 804 tvp->tv_usec = 0; 805 return 0; 806 } 807 808 static int 809 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp) 810 { 811 struct cuda_softc *sc = tch->cookie; 812 uint32_t sec; 813 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 814 815 sec = tvp->tv_sec + DIFF19041970; 816 memcpy(&cmd[2], &sec, 4); 817 sc->sc_tod = 0; 818 if (cuda_send(sc, 0, 6, cmd) == 0) { 819 while (sc->sc_tod == 0) { 820 tsleep(&sc->sc_todev, 0, "todr", 10); 821 } 822 return 0; 823 } 824 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__); 825 return -1; 826 827 } 828 829 /* poweroff and reboot */ 830 831 void 832 cuda_poweroff(void) 833 { 834 struct cuda_softc *sc; 835 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 836 837 if (cuda0 == NULL) 838 return; 839 sc = cuda0->cookie; 840 sc->sc_polling = 1; 841 cuda0->poll(sc); 842 if (cuda0->send(sc, 1, 2, cmd) == 0) 843 while (1); 844 } 845 846 void 847 cuda_restart(void) 848 { 849 struct cuda_softc *sc; 850 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 851 852 if (cuda0 == NULL) 853 return; 854 sc = cuda0->cookie; 855 sc->sc_polling = 1; 856 cuda0->poll(sc); 857 if (cuda0->send(sc, 1, 2, cmd) == 0) 858 while (1); 859 } 860 861 /* ADB message handling */ 862 863 static void 864 cuda_autopoll(void *cookie, int flag) 865 { 866 struct cuda_softc *sc = cookie; 867 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 868 869 if (cmd[2] == sc->sc_autopoll) 870 return; 871 872 sc->sc_autopoll = -1; 873 cuda_send(sc, 0, 3, cmd); 874 while(sc->sc_autopoll == -1) { 875 if (sc->sc_polling || cold) { 876 cuda_poll(sc); 877 } else 878 tsleep(&sc->sc_todev, 0, "autopoll", 100); 879 } 880 } 881 882 static int 883 cuda_adb_handler(void *cookie, int len, uint8_t *data) 884 { 885 struct cuda_softc *sc = cookie; 886 887 if (sc->sc_adb_handler != NULL) { 888 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 889 &data[1]); 890 return 0; 891 } 892 return -1; 893 } 894 895 static int 896 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 897 { 898 struct cuda_softc *sc = cookie; 899 int i, s = 0; 900 uint8_t packet[16]; 901 902 /* construct an ADB command packet and send it */ 903 packet[0] = CUDA_ADB; 904 packet[1] = command; 905 for (i = 0; i < len; i++) 906 packet[i + 2] = data[i]; 907 if (poll || cold) { 908 s = splhigh(); 909 cuda_poll(sc); 910 } 911 cuda_send(sc, poll, len + 2, packet); 912 if (poll || cold) { 913 cuda_poll(sc); 914 splx(s); 915 } 916 return 0; 917 } 918 919 static int 920 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 921 void *hcookie) 922 { 923 struct cuda_softc *sc = cookie; 924 925 /* register a callback for incoming ADB messages */ 926 sc->sc_adb_handler = handler; 927 sc->sc_adb_cookie = hcookie; 928 return 0; 929 } 930 931 /* i2c message handling */ 932 933 static int 934 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 935 size_t send_len, void *_recv, size_t recv_len, int flags) 936 { 937 struct cuda_softc *sc = cookie; 938 const uint8_t *send = _send; 939 uint8_t *recv = _recv; 940 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 941 942 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 943 command[2] = addr; 944 945 /* Copy command and output data bytes, if any, to buffer */ 946 if (send_len > 0) 947 memcpy(&command[3], send, uimin((int)send_len, 12)); 948 else if (I2C_OP_READ_P(op) && (recv_len == 0)) { 949 /* 950 * If no data bytes in either direction, it's a "quick" 951 * i2c operation. We don't know how to do a quick_read 952 * since that requires us to set the low bit of the 953 * address byte after it has been left-shifted. 954 */ 955 sc->sc_error = 0; 956 return -1; 957 } 958 959 sc->sc_iic_done = 0; 960 cuda_send(sc, sc->sc_polling, send_len + 3, command); 961 962 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 963 if (sc->sc_polling || cold) { 964 cuda_poll(sc); 965 } else 966 tsleep(&sc->sc_todev, 0, "i2c", 1000); 967 } 968 969 if (sc->sc_error) { 970 sc->sc_error = 0; 971 aprint_error_dev(sc->sc_dev, "error doing I2C\n"); 972 return -1; 973 } 974 975 /* see if we're supposed to do a read */ 976 if (recv_len > 0) { 977 sc->sc_iic_done = 0; 978 command[2] |= 1; 979 command[3] = 0; 980 981 /* 982 * XXX we need to do something to limit the size of the answer 983 * - apparently the chip keeps sending until we tell it to stop 984 */ 985 sc->sc_i2c_read_len = recv_len; 986 DPRINTF("rcv_len: %d\n", recv_len); 987 cuda_send(sc, sc->sc_polling, 3, command); 988 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 989 if (sc->sc_polling || cold) { 990 cuda_poll(sc); 991 } else 992 tsleep(&sc->sc_todev, 0, "i2c", 1000); 993 } 994 995 if (sc->sc_error) { 996 aprint_error_dev(sc->sc_dev, 997 "error trying to read from I2C\n"); 998 sc->sc_error = 0; 999 return -1; 1000 } 1001 } 1002 1003 DPRINTF("received: %d\n", sc->sc_iic_done); 1004 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 1005 int rlen; 1006 1007 /* we got an answer */ 1008 rlen = uimin(sc->sc_iic_done - 3, recv_len); 1009 memcpy(recv, &sc->sc_in[4], rlen); 1010 #ifdef CUDA_DEBUG 1011 { 1012 int i; 1013 printf("ret:"); 1014 for (i = 0; i < rlen; i++) 1015 printf(" %02x", recv[i]); 1016 printf("\n"); 1017 } 1018 #endif 1019 return rlen; 1020 } 1021 return 0; 1022 } 1023
Indexes created Thu Sep 25 16:09:42 GMT 2025