cuda.c revision 1.3.12.1
1 /* $NetBSD: cuda.c,v 1.3.12.1 2007/12/09 16:03:55 reinoud Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of The NetBSD Foundation nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.3.12.1 2007/12/09 16:03:55 reinoud Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <dev/clock_subr.h> 44 #include <dev/i2c/i2cvar.h> 45 46 #include <macppc/dev/viareg.h> 47 #include <macppc/dev/cudavar.h> 48 49 #include <dev/ofw/openfirm.h> 50 #include <dev/adb/adbvar.h> 51 #include "opt_cuda.h" 52 53 #ifdef CUDA_DEBUG 54 #define DPRINTF printf 55 #else 56 #define DPRINTF while (0) printf 57 #endif 58 59 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 60 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 61 #define CUDA_OUT 0x3 /* sending out a command */ 62 #define CUDA_IN 0x4 /* receiving data */ 63 #define CUDA_POLLING 0x5 /* polling - II only */ 64 65 static void cuda_attach(struct device *, struct device *, void *); 66 static int cuda_match(struct device *, struct cfdata *, void *); 67 static void cuda_autopoll(void *, int); 68 69 static int cuda_intr(void *); 70 71 typedef struct _cuda_handler { 72 int (*handler)(void *, int, uint8_t *); 73 void *cookie; 74 } CudaHandler; 75 76 struct cuda_softc { 77 struct device sc_dev; 78 void *sc_ih; 79 CudaHandler sc_handlers[16]; 80 struct todr_chip_handle sc_todr; 81 struct adb_bus_accessops sc_adbops; 82 struct i2c_controller sc_i2c; 83 bus_space_tag_t sc_memt; 84 bus_space_handle_t sc_memh; 85 int sc_node; 86 int sc_state; 87 int sc_waiting; 88 int sc_polling; 89 int sc_sent; 90 int sc_out_length; 91 int sc_received; 92 int sc_iic_done; 93 int sc_error; 94 /* time */ 95 uint32_t sc_tod; 96 uint32_t sc_autopoll; 97 uint32_t sc_todev; 98 /* ADB */ 99 void (*sc_adb_handler)(void *, int, uint8_t *); 100 void *sc_adb_cookie; 101 uint32_t sc_i2c_read_len; 102 /* internal buffers */ 103 uint8_t sc_in[256]; 104 uint8_t sc_out[256]; 105 }; 106 107 CFATTACH_DECL(cuda, sizeof(struct cuda_softc), 108 cuda_match, cuda_attach, NULL, NULL); 109 110 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 111 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 112 static void cuda_idle(struct cuda_softc *); 113 static void cuda_tip(struct cuda_softc *); 114 static void cuda_clear_tip(struct cuda_softc *); 115 static void cuda_in(struct cuda_softc *); 116 static void cuda_out(struct cuda_softc *); 117 static void cuda_toggle_ack(struct cuda_softc *); 118 static void cuda_ack_off(struct cuda_softc *); 119 static int cuda_intr_state(struct cuda_softc *); 120 121 static void cuda_init(struct cuda_softc *); 122 123 /* 124 * send a message to Cuda. 125 */ 126 /* cookie, flags, length, data */ 127 static int cuda_send(void *, int, int, uint8_t *); 128 static void cuda_poll(void *); 129 static void cuda_adb_poll(void *); 130 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 131 132 static int cuda_error_handler(void *, int, uint8_t *); 133 134 static int cuda_todr_handler(void *, int, uint8_t *); 135 static int cuda_todr_set(todr_chip_handle_t, volatile struct timeval *); 136 static int cuda_todr_get(todr_chip_handle_t, volatile struct timeval *); 137 138 static int cuda_adb_handler(void *, int, uint8_t *); 139 static void cuda_final(struct device *); 140 141 static struct cuda_attach_args *cuda0 = NULL; 142 143 /* ADB bus attachment stuff */ 144 static int cuda_adb_send(void *, int, int, int, uint8_t *); 145 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 146 147 /* i2c stuff */ 148 static int cuda_i2c_acquire_bus(void *, int); 149 static void cuda_i2c_release_bus(void *, int); 150 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 151 void *, size_t, int); 152 153 static int 154 cuda_match(struct device *parent, struct cfdata *cf, void *aux) 155 { 156 struct confargs *ca = aux; 157 158 if (ca->ca_nreg < 8) 159 return 0; 160 161 if (ca->ca_nintr < 4) 162 return 0; 163 164 if (strcmp(ca->ca_name, "via-cuda") == 0) { 165 return 10; /* beat adb* at obio? */ 166 } 167 168 return 0; 169 } 170 171 static void 172 cuda_attach(struct device *parent, struct device *dev, void *aux) 173 { 174 struct confargs *ca = aux; 175 struct cuda_softc *sc = (struct cuda_softc *)dev; 176 struct i2cbus_attach_args iba; 177 static struct cuda_attach_args caa; 178 int irq = ca->ca_intr[0]; 179 int node, i, child; 180 char name[32]; 181 182 node = getnodebyname(OF_parent(ca->ca_node), "extint-gpio1"); 183 if (node) 184 OF_getprop(node, "interrupts", &irq, 4); 185 186 printf(" irq %d: ", irq); 187 188 sc->sc_node = ca->ca_node; 189 sc->sc_memt = ca->ca_tag; 190 191 sc->sc_sent = 0; 192 sc->sc_received = 0; 193 sc->sc_waiting = 0; 194 sc->sc_polling = 0; 195 sc->sc_state = CUDA_NOTREADY; 196 sc->sc_error = 0; 197 sc->sc_i2c_read_len = 0; 198 199 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 200 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 201 202 printf("%s: unable to map registers\n", dev->dv_xname); 203 return; 204 } 205 sc->sc_ih = intr_establish(irq, IST_LEVEL, IPL_TTY, cuda_intr, sc); 206 printf("\n"); 207 208 for (i = 0; i < 16; i++) { 209 sc->sc_handlers[i].handler = NULL; 210 sc->sc_handlers[i].cookie = NULL; 211 } 212 213 cuda_init(sc); 214 215 /* now attach children */ 216 config_interrupts(dev, cuda_final); 217 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 218 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 219 220 child = OF_child(ca->ca_node); 221 while (child != 0) { 222 223 if (OF_getprop(child, "name", name, 32) == 0) 224 continue; 225 if (strncmp(name, "adb", 4) == 0) { 226 227 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 228 sc->sc_adbops.cookie = sc; 229 sc->sc_adbops.send = cuda_adb_send; 230 sc->sc_adbops.poll = cuda_adb_poll; 231 sc->sc_adbops.autopoll = cuda_autopoll; 232 sc->sc_adbops.set_handler = cuda_adb_set_handler; 233 config_found_ia(dev, "adb_bus", &sc->sc_adbops, 234 nadb_print); 235 } else if (strncmp(name, "rtc", 4) == 0) { 236 237 sc->sc_todr.todr_gettime = cuda_todr_get; 238 sc->sc_todr.todr_settime = cuda_todr_set; 239 sc->sc_todr.cookie = sc; 240 todr_attach(&sc->sc_todr); 241 } 242 child = OF_peer(child); 243 } 244 245 caa.cookie = sc; 246 caa.set_handler = cuda_set_handler; 247 caa.send = cuda_send; 248 caa.poll = cuda_poll; 249 #if notyet 250 config_found(dev, &caa, cuda_print); 251 #endif 252 253 iba.iba_tag = &sc->sc_i2c; 254 sc->sc_i2c.ic_cookie = sc; 255 sc->sc_i2c.ic_acquire_bus = cuda_i2c_acquire_bus; 256 sc->sc_i2c.ic_release_bus = cuda_i2c_release_bus; 257 sc->sc_i2c.ic_send_start = NULL; 258 sc->sc_i2c.ic_send_stop = NULL; 259 sc->sc_i2c.ic_initiate_xfer = NULL; 260 sc->sc_i2c.ic_read_byte = NULL; 261 sc->sc_i2c.ic_write_byte = NULL; 262 sc->sc_i2c.ic_exec = cuda_i2c_exec; 263 config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 264 265 if (cuda0 == NULL) 266 cuda0 = &caa; 267 } 268 269 static void 270 cuda_init(struct cuda_softc *sc) 271 { 272 volatile int i; 273 uint8_t reg; 274 275 reg = cuda_read_reg(sc, vDirB); 276 reg |= 0x30; /* register B bits 4 and 5: outputs */ 277 cuda_write_reg(sc, vDirB, reg); 278 279 reg = cuda_read_reg(sc, vDirB); 280 reg &= 0xf7; /* register B bit 3: input */ 281 cuda_write_reg(sc, vDirB, reg); 282 283 reg = cuda_read_reg(sc, vACR); 284 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 285 cuda_write_reg(sc, vACR, reg); 286 287 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 288 289 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 290 291 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 292 cuda_idle(sc); /* set ADB bus state to idle */ 293 294 /* sort of a device reset */ 295 i = cuda_read_reg(sc, vSR); /* clear interrupt */ 296 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 297 cuda_idle(sc); /* reset state to idle */ 298 delay(150); 299 cuda_tip(sc); /* signal start of frame */ 300 delay(150); 301 cuda_toggle_ack(sc); 302 delay(150); 303 cuda_clear_tip(sc); 304 delay(150); 305 cuda_idle(sc); /* back to idle state */ 306 i = cuda_read_reg(sc, vSR); /* clear interrupt */ 307 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 308 } 309 310 static void 311 cuda_final(struct device *dev) 312 { 313 struct cuda_softc *sc = (struct cuda_softc *)dev; 314 315 sc->sc_polling = 0; 316 #if 0 317 { 318 int err; 319 uint8_t buffer[2], buf2[2]; 320 321 /* trying to read */ 322 printf("reading\n"); 323 buffer[0] = 0; 324 buffer[1] = 1; 325 buf2[0] = 0; 326 err = cuda_i2c_exec(sc, I2C_OP_WRITE, 0x8a, buffer, 2, buf2, 0, 0); 327 buf2[0] = 0; 328 err = cuda_i2c_exec(sc, I2C_OP_WRITE | I2C_OP_READ, 0x8a, buffer, 1, buf2, 2, 0); 329 printf("buf2: %02x\n", buf2[0]); 330 } 331 #endif 332 } 333 334 static inline void 335 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 336 { 337 338 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 339 } 340 341 static inline uint8_t 342 cuda_read_reg(struct cuda_softc *sc, int offset) 343 { 344 345 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 346 } 347 348 static int 349 cuda_set_handler(void *cookie, int type, 350 int (*handler)(void *, int, uint8_t *), void *hcookie) 351 { 352 struct cuda_softc *sc = cookie; 353 CudaHandler *me; 354 355 if ((type >= 0) && (type < 16)) { 356 me = &sc->sc_handlers[type]; 357 me->handler = handler; 358 me->cookie = hcookie; 359 return 0; 360 } 361 return -1; 362 } 363 364 static int 365 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 366 { 367 struct cuda_softc *sc = cookie; 368 int s; 369 370 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 371 if (sc->sc_state == CUDA_NOTREADY) 372 return -1; 373 374 s = splhigh(); 375 376 if ((sc->sc_state == CUDA_IDLE) /*&& 377 ((cuda_read_reg(sc, vBufB) & vPB3) == vPB3)*/) { 378 /* fine */ 379 DPRINTF("chip is idle\n"); 380 } else { 381 DPRINTF("cuda state is %d\n", sc->sc_state); 382 if (sc->sc_waiting == 0) { 383 sc->sc_waiting = 1; 384 } else { 385 splx(s); 386 return -1; 387 } 388 } 389 390 sc->sc_error = 0; 391 memcpy(sc->sc_out, msg, length); 392 sc->sc_out_length = length; 393 sc->sc_sent = 0; 394 395 if (sc->sc_waiting != 1) { 396 397 delay(150); 398 sc->sc_state = CUDA_OUT; 399 cuda_out(sc); 400 cuda_write_reg(sc, vSR, sc->sc_out[0]); 401 cuda_ack_off(sc); 402 cuda_tip(sc); 403 } 404 sc->sc_waiting = 1; 405 406 if (sc->sc_polling || poll || cold) { 407 cuda_poll(sc); 408 } 409 410 splx(s); 411 412 return 0; 413 } 414 415 static void 416 cuda_poll(void *cookie) 417 { 418 struct cuda_softc *sc = cookie; 419 int s; 420 421 DPRINTF("polling\n"); 422 while ((sc->sc_state != CUDA_IDLE) || 423 (cuda_intr_state(sc)) || 424 (sc->sc_waiting == 1)) { 425 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 426 s = splhigh(); 427 cuda_intr(sc); 428 splx(s); 429 } 430 } 431 } 432 433 static void 434 cuda_adb_poll(void *cookie) 435 { 436 struct cuda_softc *sc = cookie; 437 int s; 438 439 s = splhigh(); 440 cuda_intr(sc); 441 splx(s); 442 } 443 444 static void 445 cuda_idle(struct cuda_softc *sc) 446 { 447 uint8_t reg; 448 449 reg = cuda_read_reg(sc, vBufB); 450 reg |= (vPB4 | vPB5); 451 cuda_write_reg(sc, vBufB, reg); 452 } 453 454 static void 455 cuda_tip(struct cuda_softc *sc) 456 { 457 uint8_t reg; 458 459 reg = cuda_read_reg(sc, vBufB); 460 reg &= ~vPB5; 461 cuda_write_reg(sc, vBufB, reg); 462 } 463 464 static void 465 cuda_clear_tip(struct cuda_softc *sc) 466 { 467 uint8_t reg; 468 469 reg = cuda_read_reg(sc, vBufB); 470 reg |= vPB5; 471 cuda_write_reg(sc, vBufB, reg); 472 } 473 474 static void 475 cuda_in(struct cuda_softc *sc) 476 { 477 uint8_t reg; 478 479 reg = cuda_read_reg(sc, vACR); 480 reg &= ~vSR_OUT; 481 cuda_write_reg(sc, vACR, reg); 482 } 483 484 static void 485 cuda_out(struct cuda_softc *sc) 486 { 487 uint8_t reg; 488 489 reg = cuda_read_reg(sc, vACR); 490 reg |= vSR_OUT; 491 cuda_write_reg(sc, vACR, reg); 492 } 493 494 static void 495 cuda_toggle_ack(struct cuda_softc *sc) 496 { 497 uint8_t reg; 498 499 reg = cuda_read_reg(sc, vBufB); 500 reg ^= vPB4; 501 cuda_write_reg(sc, vBufB, reg); 502 } 503 504 static void 505 cuda_ack_off(struct cuda_softc *sc) 506 { 507 uint8_t reg; 508 509 reg = cuda_read_reg(sc, vBufB); 510 reg |= vPB4; 511 cuda_write_reg(sc, vBufB, reg); 512 } 513 514 static int 515 cuda_intr_state(struct cuda_softc *sc) 516 { 517 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 518 } 519 520 static int 521 cuda_intr(void *arg) 522 { 523 struct cuda_softc *sc = arg; 524 int i, ending, type; 525 uint8_t reg; 526 527 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 528 DPRINTF("["); 529 if ((reg & 0x80) == 0) { 530 DPRINTF("irq %02x]", reg); 531 return 0; /* No interrupts to process */ 532 } 533 DPRINTF(":"); 534 535 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 536 537 switch_start: 538 switch (sc->sc_state) { 539 case CUDA_IDLE: 540 /* 541 * This is an unexpected packet, so grab the first (dummy) 542 * byte, set up the proper vars, and tell the chip we are 543 * starting to receive the packet by setting the TIP bit. 544 */ 545 sc->sc_in[1] = cuda_read_reg(sc, vSR); 546 DPRINTF("start: %02x", sc->sc_in[1]); 547 if (cuda_intr_state(sc) == 0) { 548 /* must have been a fake start */ 549 DPRINTF(" ... fake start\n"); 550 if (sc->sc_waiting) { 551 /* start over */ 552 delay(150); 553 sc->sc_state = CUDA_OUT; 554 sc->sc_sent = 0; 555 cuda_out(sc); 556 cuda_write_reg(sc, vSR, sc->sc_out[1]); 557 cuda_ack_off(sc); 558 cuda_tip(sc); 559 } 560 break; 561 } 562 563 cuda_in(sc); 564 cuda_tip(sc); 565 566 sc->sc_received = 1; 567 sc->sc_state = CUDA_IN; 568 DPRINTF(" CUDA_IN"); 569 break; 570 571 case CUDA_IN: 572 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 573 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 574 ending = 0; 575 if (sc->sc_received > 255) { 576 /* bitch only once */ 577 if (sc->sc_received == 256) { 578 printf("%s: input overflow\n", 579 sc->sc_dev.dv_xname); 580 ending = 1; 581 } 582 } else 583 sc->sc_received++; 584 if (sc->sc_received > 3) { 585 if ((sc->sc_in[3] == CMD_IIC) && 586 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 587 ending = 1; 588 } 589 } 590 591 /* intr off means this is the last byte (end of frame) */ 592 if (cuda_intr_state(sc) == 0) { 593 ending = 1; 594 DPRINTF(".\n"); 595 } else { 596 cuda_toggle_ack(sc); 597 } 598 599 if (ending == 1) { /* end of message? */ 600 601 sc->sc_in[0] = sc->sc_received - 1; 602 603 /* reset vars and signal the end of this frame */ 604 cuda_idle(sc); 605 606 /* check if we have a handler for this message */ 607 type = sc->sc_in[1]; 608 if ((type >= 0) && (type < 16)) { 609 CudaHandler *me = &sc->sc_handlers[type]; 610 611 if (me->handler != NULL) { 612 me->handler(me->cookie, 613 sc->sc_received - 1, &sc->sc_in[1]); 614 } else { 615 printf("no handler for type %02x\n", type); 616 panic("barf"); 617 } 618 } 619 620 DPRINTF("CUDA_IDLE"); 621 sc->sc_state = CUDA_IDLE; 622 623 sc->sc_received = 0; 624 625 /* 626 * If there is something waiting to be sent out, 627 * set everything up and send the first byte. 628 */ 629 if (sc->sc_waiting == 1) { 630 631 DPRINTF("pending write\n"); 632 delay(1500); /* required */ 633 sc->sc_sent = 0; 634 sc->sc_state = CUDA_OUT; 635 636 /* 637 * If the interrupt is on, we were too slow 638 * and the chip has already started to send 639 * something to us, so back out of the write 640 * and start a read cycle. 641 */ 642 if (cuda_intr_state(sc)) { 643 cuda_in(sc); 644 cuda_idle(sc); 645 sc->sc_sent = 0; 646 sc->sc_state = CUDA_IDLE; 647 sc->sc_received = 0; 648 delay(150); 649 DPRINTF("too slow - incoming message\n"); 650 goto switch_start; 651 } 652 /* 653 * If we got here, it's ok to start sending 654 * so load the first byte and tell the chip 655 * we want to send. 656 */ 657 DPRINTF("sending "); 658 659 cuda_out(sc); 660 cuda_write_reg(sc, vSR, 661 sc->sc_out[sc->sc_sent]); 662 cuda_ack_off(sc); 663 cuda_tip(sc); 664 } 665 } 666 break; 667 668 case CUDA_OUT: 669 i = cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 670 671 sc->sc_sent++; 672 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 673 674 DPRINTF("incoming msg during send\n"); 675 cuda_in(sc); /* make sure SR is set to IN */ 676 cuda_idle(sc); 677 sc->sc_sent = 0; /* must start all over */ 678 sc->sc_state = CUDA_IDLE; /* new state */ 679 sc->sc_received = 0; 680 sc->sc_waiting = 1; /* must retry when done with 681 * read */ 682 delay(150); 683 goto switch_start; /* process next state right 684 * now */ 685 break; 686 } 687 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 688 689 sc->sc_waiting = 0; /* done writing */ 690 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 691 cuda_in(sc); 692 cuda_idle(sc); 693 DPRINTF("done sending\n"); 694 } else { 695 /* send next byte */ 696 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 697 cuda_toggle_ack(sc); /* signal byte ready to 698 * shift */ 699 } 700 break; 701 702 case CUDA_NOTREADY: 703 DPRINTF("adb: not yet initialized\n"); 704 break; 705 706 default: 707 DPRINTF("intr: unknown ADB state\n"); 708 break; 709 } 710 711 DPRINTF("]"); 712 return 1; 713 } 714 715 static int 716 cuda_error_handler(void *cookie, int len, uint8_t *data) 717 { 718 struct cuda_softc *sc = cookie; 719 720 /* 721 * something went wrong 722 * byte 3 seems to be the failed command 723 */ 724 sc->sc_error = 1; 725 wakeup(&sc->sc_todev); 726 return 0; 727 } 728 729 730 /* real time clock */ 731 732 static int 733 cuda_todr_handler(void *cookie, int len, uint8_t *data) 734 { 735 struct cuda_softc *sc = cookie; 736 737 #ifdef CUDA_DEBUG 738 int i; 739 printf("msg: %02x", data[0]); 740 for (i = 1; i < len; i++) { 741 printf(" %02x", data[i]); 742 } 743 printf("\n"); 744 #endif 745 746 switch(data[2]) { 747 case CMD_READ_RTC: 748 memcpy(&sc->sc_tod, &data[3], 4); 749 break; 750 case CMD_WRITE_RTC: 751 sc->sc_tod = 0xffffffff; 752 break; 753 case CMD_AUTOPOLL: 754 sc->sc_autopoll = 1; 755 break; 756 case CMD_IIC: 757 sc->sc_iic_done = len; 758 break; 759 } 760 wakeup(&sc->sc_todev); 761 return 0; 762 } 763 764 #define DIFF19041970 2082844800 765 766 static int 767 cuda_todr_get(todr_chip_handle_t tch, volatile struct timeval *tvp) 768 { 769 struct cuda_softc *sc = tch->cookie; 770 int cnt = 0; 771 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 772 773 sc->sc_tod = 0; 774 cuda_send(sc, 0, 2, cmd); 775 776 while ((sc->sc_tod == 0) && (cnt < 10)) { 777 tsleep(&sc->sc_todev, 0, "todr", 10); 778 cnt++; 779 } 780 781 if (sc->sc_tod == 0) 782 return EIO; 783 784 tvp->tv_sec = sc->sc_tod - DIFF19041970; 785 DPRINTF("tod: %ld\n", tvp->tv_sec); 786 tvp->tv_usec = 0; 787 return 0; 788 } 789 790 static int 791 cuda_todr_set(todr_chip_handle_t tch, volatile struct timeval *tvp) 792 { 793 struct cuda_softc *sc = tch->cookie; 794 uint32_t sec; 795 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 796 797 sec = tvp->tv_sec + DIFF19041970; 798 memcpy(&cmd[2], &sec, 4); 799 sc->sc_tod = 0; 800 if (cuda_send(sc, 0, 6, cmd) == 0) { 801 while (sc->sc_tod == 0) { 802 tsleep(&sc->sc_todev, 0, "todr", 10); 803 } 804 return 0; 805 } 806 return -1; 807 808 } 809 810 /* poweroff and reboot */ 811 812 void 813 cuda_poweroff() 814 { 815 struct cuda_softc *sc; 816 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 817 818 if (cuda0 == NULL) 819 return; 820 sc = cuda0->cookie; 821 sc->sc_polling = 1; 822 cuda0->poll(sc); 823 if (cuda0->send(sc, 1, 2, cmd) == 0) 824 while (1); 825 } 826 827 void 828 cuda_restart() 829 { 830 struct cuda_softc *sc; 831 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 832 833 if (cuda0 == NULL) 834 return; 835 sc = cuda0->cookie; 836 sc->sc_polling = 1; 837 cuda0->poll(sc); 838 if (cuda0->send(sc, 1, 2, cmd) == 0) 839 while (1); 840 } 841 842 /* ADB message handling */ 843 844 static void 845 cuda_autopoll(void *cookie, int flag) 846 { 847 struct cuda_softc *sc = cookie; 848 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 849 850 if (cmd[2] == sc->sc_autopoll) 851 return; 852 853 sc->sc_autopoll = -1; 854 cuda_send(sc, 0, 3, cmd); 855 while(sc->sc_autopoll == -1) { 856 if (sc->sc_polling || cold) { 857 cuda_poll(sc); 858 } else 859 tsleep(&sc->sc_todev, 0, "autopoll", 100); 860 } 861 } 862 863 static int 864 cuda_adb_handler(void *cookie, int len, uint8_t *data) 865 { 866 struct cuda_softc *sc = cookie; 867 868 if (sc->sc_adb_handler != NULL) { 869 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 870 &data[1]); 871 return 0; 872 } 873 return -1; 874 } 875 876 static int 877 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 878 { 879 struct cuda_softc *sc = cookie; 880 int i, s = 0; 881 uint8_t packet[16]; 882 883 /* construct an ADB command packet and send it */ 884 packet[0] = CUDA_ADB; 885 packet[1] = command; 886 for (i = 0; i < len; i++) 887 packet[i + 2] = data[i]; 888 if (poll || cold) { 889 s = splhigh(); 890 cuda_poll(sc); 891 } 892 cuda_send(sc, poll, len + 2, packet); 893 if (poll || cold) { 894 cuda_poll(sc); 895 splx(s); 896 } 897 return 0; 898 } 899 900 static int 901 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 902 void *hcookie) 903 { 904 struct cuda_softc *sc = cookie; 905 906 /* register a callback for incoming ADB messages */ 907 sc->sc_adb_handler = handler; 908 sc->sc_adb_cookie = hcookie; 909 return 0; 910 } 911 912 /* i2c message handling */ 913 914 static int 915 cuda_i2c_acquire_bus(void *cookie, int flags) 916 { 917 /* nothing yet */ 918 return 0; 919 } 920 921 static void 922 cuda_i2c_release_bus(void *cookie, int flags) 923 { 924 /* nothing here either */ 925 } 926 927 static int 928 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 929 size_t send_len, void *_recv, size_t recv_len, int flags) 930 { 931 struct cuda_softc *sc = cookie; 932 const uint8_t *send = _send; 933 uint8_t *recv = _recv; 934 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 935 936 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 937 command[2] = addr; 938 939 memcpy(&command[3], send, min((int)send_len, 12)); 940 941 sc->sc_iic_done = 0; 942 cuda_send(sc, sc->sc_polling, send_len + 3, command); 943 944 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 945 if (sc->sc_polling || cold) { 946 cuda_poll(sc); 947 } else 948 tsleep(&sc->sc_todev, 0, "i2c", 1000); 949 } 950 951 if (sc->sc_error) { 952 sc->sc_error = 0; 953 return -1; 954 } 955 956 /* see if we're supposed to do a read */ 957 if (recv_len > 0) { 958 sc->sc_iic_done = 0; 959 command[2] |= 1; 960 command[3] = 0; 961 962 /* 963 * XXX we need to do something to limit the size of the answer 964 * - apparently the chip keeps sending until we tell it to stop 965 */ 966 sc->sc_i2c_read_len = recv_len; 967 DPRINTF("rcv_len: %d\n", recv_len); 968 cuda_send(sc, sc->sc_polling, 3, command); 969 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 970 if (sc->sc_polling || cold) { 971 cuda_poll(sc); 972 } else 973 tsleep(&sc->sc_todev, 0, "i2c", 1000); 974 } 975 976 if (sc->sc_error) { 977 printf("error trying to read\n"); 978 sc->sc_error = 0; 979 return -1; 980 } 981 } 982 983 DPRINTF("received: %d\n", sc->sc_iic_done); 984 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 985 int rlen; 986 987 /* we got an answer */ 988 rlen = min(sc->sc_iic_done - 3, recv_len); 989 memcpy(recv, &sc->sc_in[4], rlen); 990 #ifdef CUDA_DEBUG 991 { 992 int i; 993 printf("ret:"); 994 for (i = 0; i < rlen; i++) 995 printf(" %02x", recv[i]); 996 printf("\n"); 997 } 998 #endif 999 return rlen; 1000 } 1001 return 0; 1002 } 1003
Indexes created Tue Sep 30 11:09:46 GMT 2025