cuda.c revision 1.4
1 /* $NetBSD: cuda.c,v 1.4 2007/10/17 19:55:18 garbled Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of The NetBSD Foundation nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.4 2007/10/17 19:55:18 garbled Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/pio.h> 44 #include <dev/clock_subr.h> 45 #include <dev/i2c/i2cvar.h> 46 47 #include <macppc/dev/viareg.h> 48 #include <macppc/dev/cudavar.h> 49 50 #include <dev/ofw/openfirm.h> 51 #include <dev/adb/adbvar.h> 52 #include "opt_cuda.h" 53 54 #ifdef CUDA_DEBUG 55 #define DPRINTF printf 56 #else 57 #define DPRINTF while (0) printf 58 #endif 59 60 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 61 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 62 #define CUDA_OUT 0x3 /* sending out a command */ 63 #define CUDA_IN 0x4 /* receiving data */ 64 #define CUDA_POLLING 0x5 /* polling - II only */ 65 66 static void cuda_attach(struct device *, struct device *, void *); 67 static int cuda_match(struct device *, struct cfdata *, void *); 68 static void cuda_autopoll(void *, int); 69 70 static int cuda_intr(void *); 71 72 typedef struct _cuda_handler { 73 int (*handler)(void *, int, uint8_t *); 74 void *cookie; 75 } CudaHandler; 76 77 struct cuda_softc { 78 struct device sc_dev; 79 void *sc_ih; 80 CudaHandler sc_handlers[16]; 81 struct todr_chip_handle sc_todr; 82 struct adb_bus_accessops sc_adbops; 83 struct i2c_controller sc_i2c; 84 struct lock sc_buslock; 85 bus_space_tag_t sc_memt; 86 bus_space_handle_t sc_memh; 87 int sc_node; 88 int sc_state; 89 int sc_waiting; 90 int sc_polling; 91 int sc_sent; 92 int sc_out_length; 93 int sc_received; 94 int sc_iic_done; 95 int sc_error; 96 /* time */ 97 uint32_t sc_tod; 98 uint32_t sc_autopoll; 99 uint32_t sc_todev; 100 /* ADB */ 101 void (*sc_adb_handler)(void *, int, uint8_t *); 102 void *sc_adb_cookie; 103 uint32_t sc_i2c_read_len; 104 /* internal buffers */ 105 uint8_t sc_in[256]; 106 uint8_t sc_out[256]; 107 }; 108 109 CFATTACH_DECL(cuda, sizeof(struct cuda_softc), 110 cuda_match, cuda_attach, NULL, NULL); 111 112 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 113 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 114 static void cuda_idle(struct cuda_softc *); 115 static void cuda_tip(struct cuda_softc *); 116 static void cuda_clear_tip(struct cuda_softc *); 117 static void cuda_in(struct cuda_softc *); 118 static void cuda_out(struct cuda_softc *); 119 static void cuda_toggle_ack(struct cuda_softc *); 120 static void cuda_ack_off(struct cuda_softc *); 121 static int cuda_intr_state(struct cuda_softc *); 122 123 static void cuda_init(struct cuda_softc *); 124 125 /* 126 * send a message to Cuda. 127 */ 128 /* cookie, flags, length, data */ 129 static int cuda_send(void *, int, int, uint8_t *); 130 static void cuda_poll(void *); 131 static void cuda_adb_poll(void *); 132 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 133 134 static int cuda_error_handler(void *, int, uint8_t *); 135 136 static int cuda_todr_handler(void *, int, uint8_t *); 137 static int cuda_todr_set(todr_chip_handle_t, volatile struct timeval *); 138 static int cuda_todr_get(todr_chip_handle_t, volatile struct timeval *); 139 140 static int cuda_adb_handler(void *, int, uint8_t *); 141 static void cuda_final(struct device *); 142 143 static struct cuda_attach_args *cuda0 = NULL; 144 145 /* ADB bus attachment stuff */ 146 static int cuda_adb_send(void *, int, int, int, uint8_t *); 147 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 148 149 /* i2c stuff */ 150 static int cuda_i2c_acquire_bus(void *, int); 151 static void cuda_i2c_release_bus(void *, int); 152 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 153 void *, size_t, int); 154 155 static int 156 cuda_match(struct device *parent, struct cfdata *cf, void *aux) 157 { 158 struct confargs *ca = aux; 159 160 if (ca->ca_nreg < 8) 161 return 0; 162 163 if (ca->ca_nintr < 4) 164 return 0; 165 166 if (strcmp(ca->ca_name, "via-cuda") == 0) { 167 return 10; /* beat adb* at obio? */ 168 } 169 170 return 0; 171 } 172 173 static void 174 cuda_attach(struct device *parent, struct device *dev, void *aux) 175 { 176 struct confargs *ca = aux; 177 struct cuda_softc *sc = (struct cuda_softc *)dev; 178 struct i2cbus_attach_args iba; 179 static struct cuda_attach_args caa; 180 int irq = ca->ca_intr[0]; 181 int node, i, child; 182 char name[32]; 183 184 node = getnodebyname(OF_parent(ca->ca_node), "extint-gpio1"); 185 if (node) 186 OF_getprop(node, "interrupts", &irq, 4); 187 188 printf(" irq %d: ", irq); 189 190 sc->sc_node = ca->ca_node; 191 sc->sc_memt = ca->ca_tag; 192 193 sc->sc_sent = 0; 194 sc->sc_received = 0; 195 sc->sc_waiting = 0; 196 sc->sc_polling = 0; 197 sc->sc_state = CUDA_NOTREADY; 198 sc->sc_error = 0; 199 sc->sc_i2c_read_len = 0; 200 201 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 202 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 203 204 printf("%s: unable to map registers\n", dev->dv_xname); 205 return; 206 } 207 sc->sc_ih = intr_establish(irq, IST_EDGE, IPL_TTY, cuda_intr, sc); 208 printf("\n"); 209 210 for (i = 0; i < 16; i++) { 211 sc->sc_handlers[i].handler = NULL; 212 sc->sc_handlers[i].cookie = NULL; 213 } 214 215 cuda_init(sc); 216 217 /* now attach children */ 218 config_interrupts(dev, cuda_final); 219 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 220 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 221 222 child = OF_child(ca->ca_node); 223 while (child != 0) { 224 225 if (OF_getprop(child, "name", name, 32) == 0) 226 continue; 227 if (strncmp(name, "adb", 4) == 0) { 228 229 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 230 sc->sc_adbops.cookie = sc; 231 sc->sc_adbops.send = cuda_adb_send; 232 sc->sc_adbops.poll = cuda_adb_poll; 233 sc->sc_adbops.autopoll = cuda_autopoll; 234 sc->sc_adbops.set_handler = cuda_adb_set_handler; 235 config_found_ia(dev, "adb_bus", &sc->sc_adbops, 236 nadb_print); 237 } else if (strncmp(name, "rtc", 4) == 0) { 238 239 sc->sc_todr.todr_gettime = cuda_todr_get; 240 sc->sc_todr.todr_settime = cuda_todr_set; 241 sc->sc_todr.cookie = sc; 242 todr_attach(&sc->sc_todr); 243 } 244 child = OF_peer(child); 245 } 246 247 caa.cookie = sc; 248 caa.set_handler = cuda_set_handler; 249 caa.send = cuda_send; 250 caa.poll = cuda_poll; 251 #if notyet 252 config_found(dev, &caa, cuda_print); 253 #endif 254 255 iba.iba_tag = &sc->sc_i2c; 256 sc->sc_i2c.ic_cookie = sc; 257 sc->sc_i2c.ic_acquire_bus = cuda_i2c_acquire_bus; 258 sc->sc_i2c.ic_release_bus = cuda_i2c_release_bus; 259 sc->sc_i2c.ic_send_start = NULL; 260 sc->sc_i2c.ic_send_stop = NULL; 261 sc->sc_i2c.ic_initiate_xfer = NULL; 262 sc->sc_i2c.ic_read_byte = NULL; 263 sc->sc_i2c.ic_write_byte = NULL; 264 sc->sc_i2c.ic_exec = cuda_i2c_exec; 265 config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 266 267 if (cuda0 == NULL) 268 cuda0 = &caa; 269 } 270 271 static void 272 cuda_init(struct cuda_softc *sc) 273 { 274 volatile int i; 275 uint8_t reg; 276 277 reg = cuda_read_reg(sc, vDirB); 278 reg |= 0x30; /* register B bits 4 and 5: outputs */ 279 cuda_write_reg(sc, vDirB, reg); 280 281 reg = cuda_read_reg(sc, vDirB); 282 reg &= 0xf7; /* register B bit 3: input */ 283 cuda_write_reg(sc, vDirB, reg); 284 285 reg = cuda_read_reg(sc, vACR); 286 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 287 cuda_write_reg(sc, vACR, reg); 288 289 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 290 291 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 292 293 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 294 cuda_idle(sc); /* set ADB bus state to idle */ 295 296 /* sort of a device reset */ 297 i = cuda_read_reg(sc, vSR); /* clear interrupt */ 298 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 299 cuda_idle(sc); /* reset state to idle */ 300 delay(150); 301 cuda_tip(sc); /* signal start of frame */ 302 delay(150); 303 cuda_toggle_ack(sc); 304 delay(150); 305 cuda_clear_tip(sc); 306 delay(150); 307 cuda_idle(sc); /* back to idle state */ 308 i = cuda_read_reg(sc, vSR); /* clear interrupt */ 309 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 310 } 311 312 static void 313 cuda_final(struct device *dev) 314 { 315 struct cuda_softc *sc = (struct cuda_softc *)dev; 316 317 sc->sc_polling = 0; 318 #if 0 319 { 320 int err; 321 uint8_t buffer[2], buf2[2]; 322 323 /* trying to read */ 324 printf("reading\n"); 325 buffer[0] = 0; 326 buffer[1] = 1; 327 buf2[0] = 0; 328 err = cuda_i2c_exec(sc, I2C_OP_WRITE, 0x8a, buffer, 2, buf2, 0, 0); 329 buf2[0] = 0; 330 err = cuda_i2c_exec(sc, I2C_OP_WRITE | I2C_OP_READ, 0x8a, buffer, 1, buf2, 2, 0); 331 printf("buf2: %02x\n", buf2[0]); 332 } 333 #endif 334 } 335 336 static inline void 337 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 338 { 339 340 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 341 } 342 343 static inline uint8_t 344 cuda_read_reg(struct cuda_softc *sc, int offset) 345 { 346 347 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 348 } 349 350 static int 351 cuda_set_handler(void *cookie, int type, 352 int (*handler)(void *, int, uint8_t *), void *hcookie) 353 { 354 struct cuda_softc *sc = cookie; 355 CudaHandler *me; 356 357 if ((type >= 0) && (type < 16)) { 358 me = &sc->sc_handlers[type]; 359 me->handler = handler; 360 me->cookie = hcookie; 361 return 0; 362 } 363 return -1; 364 } 365 366 static int 367 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 368 { 369 struct cuda_softc *sc = cookie; 370 int s; 371 372 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 373 if (sc->sc_state == CUDA_NOTREADY) 374 return -1; 375 376 s = splhigh(); 377 378 if ((sc->sc_state == CUDA_IDLE) /*&& 379 ((cuda_read_reg(sc, vBufB) & vPB3) == vPB3)*/) { 380 /* fine */ 381 DPRINTF("chip is idle\n"); 382 } else { 383 DPRINTF("cuda state is %d\n", sc->sc_state); 384 if (sc->sc_waiting == 0) { 385 sc->sc_waiting = 1; 386 } else { 387 splx(s); 388 return -1; 389 } 390 } 391 392 sc->sc_error = 0; 393 memcpy(sc->sc_out, msg, length); 394 sc->sc_out_length = length; 395 sc->sc_sent = 0; 396 397 if (sc->sc_waiting != 1) { 398 399 delay(150); 400 sc->sc_state = CUDA_OUT; 401 cuda_out(sc); 402 cuda_write_reg(sc, vSR, sc->sc_out[0]); 403 cuda_ack_off(sc); 404 cuda_tip(sc); 405 } 406 sc->sc_waiting = 1; 407 408 if (sc->sc_polling || poll || cold) { 409 cuda_poll(sc); 410 } 411 412 splx(s); 413 414 return 0; 415 } 416 417 static void 418 cuda_poll(void *cookie) 419 { 420 struct cuda_softc *sc = cookie; 421 int s; 422 423 DPRINTF("polling\n"); 424 while ((sc->sc_state != CUDA_IDLE) || 425 (cuda_intr_state(sc)) || 426 (sc->sc_waiting == 1)) { 427 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 428 s = splhigh(); 429 cuda_intr(sc); 430 splx(s); 431 } 432 } 433 } 434 435 static void 436 cuda_adb_poll(void *cookie) 437 { 438 struct cuda_softc *sc = cookie; 439 int s; 440 441 s = splhigh(); 442 cuda_intr(sc); 443 splx(s); 444 } 445 446 static void 447 cuda_idle(struct cuda_softc *sc) 448 { 449 uint8_t reg; 450 451 reg = cuda_read_reg(sc, vBufB); 452 reg |= (vPB4 | vPB5); 453 cuda_write_reg(sc, vBufB, reg); 454 } 455 456 static void 457 cuda_tip(struct cuda_softc *sc) 458 { 459 uint8_t reg; 460 461 reg = cuda_read_reg(sc, vBufB); 462 reg &= ~vPB5; 463 cuda_write_reg(sc, vBufB, reg); 464 } 465 466 static void 467 cuda_clear_tip(struct cuda_softc *sc) 468 { 469 uint8_t reg; 470 471 reg = cuda_read_reg(sc, vBufB); 472 reg |= vPB5; 473 cuda_write_reg(sc, vBufB, reg); 474 } 475 476 static void 477 cuda_in(struct cuda_softc *sc) 478 { 479 uint8_t reg; 480 481 reg = cuda_read_reg(sc, vACR); 482 reg &= ~vSR_OUT; 483 cuda_write_reg(sc, vACR, reg); 484 } 485 486 static void 487 cuda_out(struct cuda_softc *sc) 488 { 489 uint8_t reg; 490 491 reg = cuda_read_reg(sc, vACR); 492 reg |= vSR_OUT; 493 cuda_write_reg(sc, vACR, reg); 494 } 495 496 static void 497 cuda_toggle_ack(struct cuda_softc *sc) 498 { 499 uint8_t reg; 500 501 reg = cuda_read_reg(sc, vBufB); 502 reg ^= vPB4; 503 cuda_write_reg(sc, vBufB, reg); 504 } 505 506 static void 507 cuda_ack_off(struct cuda_softc *sc) 508 { 509 uint8_t reg; 510 511 reg = cuda_read_reg(sc, vBufB); 512 reg |= vPB4; 513 cuda_write_reg(sc, vBufB, reg); 514 } 515 516 static int 517 cuda_intr_state(struct cuda_softc *sc) 518 { 519 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 520 } 521 522 static int 523 cuda_intr(void *arg) 524 { 525 struct cuda_softc *sc = arg; 526 int i, ending, type; 527 uint8_t reg; 528 529 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 530 DPRINTF("["); 531 if ((reg & 0x80) == 0) { 532 DPRINTF("irq %02x]", reg); 533 return 0; /* No interrupts to process */ 534 } 535 DPRINTF(":"); 536 537 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 538 539 switch_start: 540 switch (sc->sc_state) { 541 case CUDA_IDLE: 542 /* 543 * This is an unexpected packet, so grab the first (dummy) 544 * byte, set up the proper vars, and tell the chip we are 545 * starting to receive the packet by setting the TIP bit. 546 */ 547 sc->sc_in[1] = cuda_read_reg(sc, vSR); 548 DPRINTF("start: %02x", sc->sc_in[1]); 549 if (cuda_intr_state(sc) == 0) { 550 /* must have been a fake start */ 551 DPRINTF(" ... fake start\n"); 552 if (sc->sc_waiting) { 553 /* start over */ 554 delay(150); 555 sc->sc_state = CUDA_OUT; 556 sc->sc_sent = 0; 557 cuda_out(sc); 558 cuda_write_reg(sc, vSR, sc->sc_out[1]); 559 cuda_ack_off(sc); 560 cuda_tip(sc); 561 } 562 break; 563 } 564 565 cuda_in(sc); 566 cuda_tip(sc); 567 568 sc->sc_received = 1; 569 sc->sc_state = CUDA_IN; 570 DPRINTF(" CUDA_IN"); 571 break; 572 573 case CUDA_IN: 574 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 575 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 576 ending = 0; 577 if (sc->sc_received > 255) { 578 /* bitch only once */ 579 if (sc->sc_received == 256) { 580 printf("%s: input overflow\n", 581 sc->sc_dev.dv_xname); 582 ending = 1; 583 } 584 } else 585 sc->sc_received++; 586 if (sc->sc_received > 3) { 587 if ((sc->sc_in[3] == CMD_IIC) && 588 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 589 ending = 1; 590 } 591 } 592 593 /* intr off means this is the last byte (end of frame) */ 594 if (cuda_intr_state(sc) == 0) { 595 ending = 1; 596 DPRINTF(".\n"); 597 } else { 598 cuda_toggle_ack(sc); 599 } 600 601 if (ending == 1) { /* end of message? */ 602 603 sc->sc_in[0] = sc->sc_received - 1; 604 605 /* reset vars and signal the end of this frame */ 606 cuda_idle(sc); 607 608 /* check if we have a handler for this message */ 609 type = sc->sc_in[1]; 610 if ((type >= 0) && (type < 16)) { 611 CudaHandler *me = &sc->sc_handlers[type]; 612 613 if (me->handler != NULL) { 614 me->handler(me->cookie, 615 sc->sc_received - 1, &sc->sc_in[1]); 616 } else { 617 printf("no handler for type %02x\n", type); 618 panic("barf"); 619 } 620 } 621 622 DPRINTF("CUDA_IDLE"); 623 sc->sc_state = CUDA_IDLE; 624 625 sc->sc_received = 0; 626 627 /* 628 * If there is something waiting to be sent out, 629 * set everything up and send the first byte. 630 */ 631 if (sc->sc_waiting == 1) { 632 633 DPRINTF("pending write\n"); 634 delay(1500); /* required */ 635 sc->sc_sent = 0; 636 sc->sc_state = CUDA_OUT; 637 638 /* 639 * If the interrupt is on, we were too slow 640 * and the chip has already started to send 641 * something to us, so back out of the write 642 * and start a read cycle. 643 */ 644 if (cuda_intr_state(sc)) { 645 cuda_in(sc); 646 cuda_idle(sc); 647 sc->sc_sent = 0; 648 sc->sc_state = CUDA_IDLE; 649 sc->sc_received = 0; 650 delay(150); 651 DPRINTF("too slow - incoming message\n"); 652 goto switch_start; 653 } 654 /* 655 * If we got here, it's ok to start sending 656 * so load the first byte and tell the chip 657 * we want to send. 658 */ 659 DPRINTF("sending "); 660 661 cuda_out(sc); 662 cuda_write_reg(sc, vSR, 663 sc->sc_out[sc->sc_sent]); 664 cuda_ack_off(sc); 665 cuda_tip(sc); 666 } 667 } 668 break; 669 670 case CUDA_OUT: 671 i = cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 672 673 sc->sc_sent++; 674 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 675 676 DPRINTF("incoming msg during send\n"); 677 cuda_in(sc); /* make sure SR is set to IN */ 678 cuda_idle(sc); 679 sc->sc_sent = 0; /* must start all over */ 680 sc->sc_state = CUDA_IDLE; /* new state */ 681 sc->sc_received = 0; 682 sc->sc_waiting = 1; /* must retry when done with 683 * read */ 684 delay(150); 685 goto switch_start; /* process next state right 686 * now */ 687 break; 688 } 689 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 690 691 sc->sc_waiting = 0; /* done writing */ 692 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 693 cuda_in(sc); 694 cuda_idle(sc); 695 DPRINTF("done sending\n"); 696 } else { 697 /* send next byte */ 698 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 699 cuda_toggle_ack(sc); /* signal byte ready to 700 * shift */ 701 } 702 break; 703 704 case CUDA_NOTREADY: 705 DPRINTF("adb: not yet initialized\n"); 706 break; 707 708 default: 709 DPRINTF("intr: unknown ADB state\n"); 710 break; 711 } 712 713 DPRINTF("]"); 714 return 1; 715 } 716 717 static int 718 cuda_error_handler(void *cookie, int len, uint8_t *data) 719 { 720 struct cuda_softc *sc = cookie; 721 722 /* 723 * something went wrong 724 * byte 3 seems to be the failed command 725 */ 726 sc->sc_error = 1; 727 wakeup(&sc->sc_todev); 728 return 0; 729 } 730 731 732 /* real time clock */ 733 734 static int 735 cuda_todr_handler(void *cookie, int len, uint8_t *data) 736 { 737 struct cuda_softc *sc = cookie; 738 739 #ifdef CUDA_DEBUG 740 int i; 741 printf("msg: %02x", data[0]); 742 for (i = 1; i < len; i++) { 743 printf(" %02x", data[i]); 744 } 745 printf("\n"); 746 #endif 747 748 switch(data[2]) { 749 case CMD_READ_RTC: 750 memcpy(&sc->sc_tod, &data[3], 4); 751 break; 752 case CMD_WRITE_RTC: 753 sc->sc_tod = 0xffffffff; 754 break; 755 case CMD_AUTOPOLL: 756 sc->sc_autopoll = 1; 757 break; 758 case CMD_IIC: 759 sc->sc_iic_done = len; 760 break; 761 } 762 wakeup(&sc->sc_todev); 763 return 0; 764 } 765 766 #define DIFF19041970 2082844800 767 768 static int 769 cuda_todr_get(todr_chip_handle_t tch, volatile struct timeval *tvp) 770 { 771 struct cuda_softc *sc = tch->cookie; 772 int cnt = 0; 773 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 774 775 sc->sc_tod = 0; 776 cuda_send(sc, 0, 2, cmd); 777 778 while ((sc->sc_tod == 0) && (cnt < 10)) { 779 tsleep(&sc->sc_todev, 0, "todr", 10); 780 cnt++; 781 } 782 783 if (sc->sc_tod == 0) 784 return EIO; 785 786 tvp->tv_sec = sc->sc_tod - DIFF19041970; 787 DPRINTF("tod: %ld\n", tvp->tv_sec); 788 tvp->tv_usec = 0; 789 return 0; 790 } 791 792 static int 793 cuda_todr_set(todr_chip_handle_t tch, volatile struct timeval *tvp) 794 { 795 struct cuda_softc *sc = tch->cookie; 796 uint32_t sec; 797 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 798 799 sec = tvp->tv_sec + DIFF19041970; 800 memcpy(&cmd[2], &sec, 4); 801 sc->sc_tod = 0; 802 if (cuda_send(sc, 0, 6, cmd) == 0) { 803 while (sc->sc_tod == 0) { 804 tsleep(&sc->sc_todev, 0, "todr", 10); 805 } 806 return 0; 807 } 808 return -1; 809 810 } 811 812 /* poweroff and reboot */ 813 814 void 815 cuda_poweroff() 816 { 817 struct cuda_softc *sc; 818 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 819 820 if (cuda0 == NULL) 821 return; 822 sc = cuda0->cookie; 823 sc->sc_polling = 1; 824 cuda0->poll(sc); 825 if (cuda0->send(sc, 1, 2, cmd) == 0) 826 while (1); 827 } 828 829 void 830 cuda_restart() 831 { 832 struct cuda_softc *sc; 833 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 834 835 if (cuda0 == NULL) 836 return; 837 sc = cuda0->cookie; 838 sc->sc_polling = 1; 839 cuda0->poll(sc); 840 if (cuda0->send(sc, 1, 2, cmd) == 0) 841 while (1); 842 } 843 844 /* ADB message handling */ 845 846 static void 847 cuda_autopoll(void *cookie, int flag) 848 { 849 struct cuda_softc *sc = cookie; 850 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 851 852 if (cmd[2] == sc->sc_autopoll) 853 return; 854 855 sc->sc_autopoll = -1; 856 cuda_send(sc, 0, 3, cmd); 857 while(sc->sc_autopoll == -1) { 858 if (sc->sc_polling || cold) { 859 cuda_poll(sc); 860 } else 861 tsleep(&sc->sc_todev, 0, "autopoll", 100); 862 } 863 } 864 865 static int 866 cuda_adb_handler(void *cookie, int len, uint8_t *data) 867 { 868 struct cuda_softc *sc = cookie; 869 870 if (sc->sc_adb_handler != NULL) { 871 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 872 &data[1]); 873 return 0; 874 } 875 return -1; 876 } 877 878 static int 879 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 880 { 881 struct cuda_softc *sc = cookie; 882 int i, s = 0; 883 uint8_t packet[16]; 884 885 /* construct an ADB command packet and send it */ 886 packet[0] = CUDA_ADB; 887 packet[1] = command; 888 for (i = 0; i < len; i++) 889 packet[i + 2] = data[i]; 890 if (poll || cold) { 891 s = splhigh(); 892 cuda_poll(sc); 893 } 894 cuda_send(sc, poll, len + 2, packet); 895 if (poll || cold) { 896 cuda_poll(sc); 897 splx(s); 898 } 899 return 0; 900 } 901 902 static int 903 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 904 void *hcookie) 905 { 906 struct cuda_softc *sc = cookie; 907 908 /* register a callback for incoming ADB messages */ 909 sc->sc_adb_handler = handler; 910 sc->sc_adb_cookie = hcookie; 911 return 0; 912 } 913 914 /* i2c message handling */ 915 916 static int 917 cuda_i2c_acquire_bus(void *cookie, int flags) 918 { 919 /* nothing yet */ 920 return 0; 921 } 922 923 static void 924 cuda_i2c_release_bus(void *cookie, int flags) 925 { 926 /* nothing here either */ 927 } 928 929 static int 930 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 931 size_t send_len, void *_recv, size_t recv_len, int flags) 932 { 933 struct cuda_softc *sc = cookie; 934 const uint8_t *send = _send; 935 uint8_t *recv = _recv; 936 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 937 938 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 939 command[2] = addr; 940 941 memcpy(&command[3], send, min((int)send_len, 12)); 942 943 sc->sc_iic_done = 0; 944 cuda_send(sc, sc->sc_polling, send_len + 3, command); 945 946 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 947 if (sc->sc_polling || cold) { 948 cuda_poll(sc); 949 } else 950 tsleep(&sc->sc_todev, 0, "i2c", 1000); 951 } 952 953 if (sc->sc_error) { 954 sc->sc_error = 0; 955 return -1; 956 } 957 958 /* see if we're supposed to do a read */ 959 if (recv_len > 0) { 960 sc->sc_iic_done = 0; 961 command[2] |= 1; 962 command[3] = 0; 963 964 /* 965 * XXX we need to do something to limit the size of the answer 966 * - apparently the chip keeps sending until we tell it to stop 967 */ 968 sc->sc_i2c_read_len = recv_len; 969 DPRINTF("rcv_len: %d\n", recv_len); 970 cuda_send(sc, sc->sc_polling, 3, command); 971 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 972 if (sc->sc_polling || cold) { 973 cuda_poll(sc); 974 } else 975 tsleep(&sc->sc_todev, 0, "i2c", 1000); 976 } 977 978 if (sc->sc_error) { 979 printf("error trying to read\n"); 980 sc->sc_error = 0; 981 return -1; 982 } 983 } 984 985 DPRINTF("received: %d\n", sc->sc_iic_done); 986 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 987 int rlen; 988 989 /* we got an answer */ 990 rlen = min(sc->sc_iic_done - 3, recv_len); 991 memcpy(recv, &sc->sc_in[4], rlen); 992 #ifdef CUDA_DEBUG 993 { 994 int i; 995 printf("ret:"); 996 for (i = 0; i < rlen; i++) 997 printf(" %02x", recv[i]); 998 printf("\n"); 999 } 1000 #endif 1001 return rlen; 1002 } 1003 return 0; 1004 } 1005
Indexes created Tue Sep 23 20:09:58 GMT 2025