esp.c revision 1.22
1 /* $NetBSD: esp.c,v 1.22 2007/03/05 10:50:24 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.22 2007/03/05 10:50:24 tsutsui Exp $"); 81 82 #include <sys/types.h> 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/kernel.h> 86 #include <sys/errno.h> 87 #include <sys/ioctl.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 #include <sys/queue.h> 93 #include <sys/malloc.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #include <dev/scsipi/scsi_all.h> 98 #include <dev/scsipi/scsipi_all.h> 99 #include <dev/scsipi/scsiconf.h> 100 #include <dev/scsipi/scsi_message.h> 101 102 #include <dev/ofw/openfirm.h> 103 104 #include <machine/cpu.h> 105 #include <machine/autoconf.h> 106 #include <machine/pio.h> 107 108 #include <dev/ic/ncr53c9xreg.h> 109 #include <dev/ic/ncr53c9xvar.h> 110 111 #include <macppc/dev/dbdma.h> 112 #include <macppc/dev/espvar.h> 113 114 void espattach __P((struct device *, struct device *, void *)); 115 int espmatch __P((struct device *, struct cfdata *, void *)); 116 117 /* Linkup to the rest of the kernel */ 118 CFATTACH_DECL(esp, sizeof(struct esp_softc), 119 espmatch, espattach, NULL, NULL); 120 121 /* 122 * Functions and the switch for the MI code. 123 */ 124 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 125 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 126 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 127 void esp_dma_reset __P((struct ncr53c9x_softc *)); 128 int esp_dma_intr __P((struct ncr53c9x_softc *)); 129 int esp_dma_setup __P((struct ncr53c9x_softc *, void **, 130 size_t *, int, size_t *)); 131 void esp_dma_go __P((struct ncr53c9x_softc *)); 132 void esp_dma_stop __P((struct ncr53c9x_softc *)); 133 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 134 135 struct ncr53c9x_glue esp_glue = { 136 esp_read_reg, 137 esp_write_reg, 138 esp_dma_isintr, 139 esp_dma_reset, 140 esp_dma_intr, 141 esp_dma_setup, 142 esp_dma_go, 143 esp_dma_stop, 144 esp_dma_isactive, 145 NULL, /* gl_clear_latched_intr */ 146 }; 147 148 static int espdmaintr __P((struct esp_softc *)); 149 static void esp_shutdownhook __P((void *)); 150 151 int 152 espmatch(parent, cf, aux) 153 struct device *parent; 154 struct cfdata *cf; 155 void *aux; 156 { 157 struct confargs *ca = aux; 158 159 if (strcmp(ca->ca_name, "53c94") != 0) 160 return 0; 161 162 if (ca->ca_nreg != 16) 163 return 0; 164 if (ca->ca_nintr != 8) 165 return 0; 166 167 return 1; 168 } 169 170 /* 171 * Attach this instance, and then all the sub-devices 172 */ 173 void 174 espattach(parent, self, aux) 175 struct device *parent, *self; 176 void *aux; 177 { 178 register struct confargs *ca = aux; 179 struct esp_softc *esc = (void *)self; 180 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 181 u_int *reg; 182 int sz; 183 184 /* 185 * Set up glue for MI code early; we use some of it here. 186 */ 187 sc->sc_glue = &esp_glue; 188 189 esc->sc_node = ca->ca_node; 190 esc->sc_pri = ca->ca_intr[0]; 191 printf(" irq %d", esc->sc_pri); 192 193 /* 194 * Map my registers in. 195 */ 196 reg = ca->ca_reg; 197 esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1]); 198 esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3]); 199 200 /* Allocate 16-byte aligned DMA command space */ 201 esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 202 203 /* Other settings */ 204 sc->sc_id = 7; 205 sz = OF_getprop(ca->ca_node, "clock-frequency", 206 &sc->sc_freq, sizeof(int)); 207 if (sz != sizeof(int)) 208 sc->sc_freq = 25000000; 209 210 /* gimme MHz */ 211 sc->sc_freq /= 1000000; 212 213 /* esc->sc_dma->sc_esp = esc;*/ 214 215 /* 216 * XXX More of this should be in ncr53c9x_attach(), but 217 * XXX should we really poke around the chip that much in 218 * XXX the MI code? Think about this more... 219 */ 220 221 /* 222 * Set up static configuration info. 223 */ 224 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 225 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 226 sc->sc_cfg3 = NCRCFG3_CDB; 227 sc->sc_rev = NCR_VARIANT_NCR53C94; 228 229 /* 230 * XXX minsync and maxxfer _should_ be set up in MI code, 231 * XXX but it appears to have some dependency on what sort 232 * XXX of DMA we're hooked up to, etc. 233 */ 234 235 /* 236 * This is the value used to start sync negotiations 237 * Note that the NCR register "SYNCTP" is programmed 238 * in "clocks per byte", and has a minimum value of 4. 239 * The SCSI period used in negotiation is one-fourth 240 * of the time (in nanoseconds) needed to transfer one byte. 241 * Since the chip's clock is given in MHz, we have the following 242 * formula: 4 * period = (1000 / freq) * 4 243 */ 244 sc->sc_minsync = 1000 / sc->sc_freq; 245 246 sc->sc_maxxfer = 64 * 1024; 247 248 /* and the interuppts */ 249 intr_establish(esc->sc_pri, IST_LEVEL, IPL_BIO, ncr53c9x_intr, sc); 250 251 /* Reset SCSI bus when halt. */ 252 shutdownhook_establish(esp_shutdownhook, sc); 253 254 /* Do the common parts of attachment. */ 255 sc->sc_adapter.adapt_minphys = minphys; 256 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 257 ncr53c9x_attach(sc); 258 259 /* Turn on target selection using the `DMA' method */ 260 sc->sc_features |= NCR_F_DMASELECT; 261 } 262 263 /* 264 * Glue functions. 265 */ 266 267 u_char 268 esp_read_reg(sc, reg) 269 struct ncr53c9x_softc *sc; 270 int reg; 271 { 272 struct esp_softc *esc = (struct esp_softc *)sc; 273 274 return in8(&esc->sc_reg[reg * 16]); 275 /*return (esc->sc_reg[reg * 16]);*/ 276 } 277 278 void 279 esp_write_reg(sc, reg, val) 280 struct ncr53c9x_softc *sc; 281 int reg; 282 u_char val; 283 { 284 struct esp_softc *esc = (struct esp_softc *)sc; 285 u_char v = val; 286 287 out8(&esc->sc_reg[reg * 16], v); 288 /*esc->sc_reg[reg * 16] = v;*/ 289 } 290 291 int 292 esp_dma_isintr(sc) 293 struct ncr53c9x_softc *sc; 294 { 295 return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 296 } 297 298 void 299 esp_dma_reset(sc) 300 struct ncr53c9x_softc *sc; 301 { 302 struct esp_softc *esc = (struct esp_softc *)sc; 303 304 dbdma_stop(esc->sc_dmareg); 305 esc->sc_dmaactive = 0; 306 } 307 308 int 309 esp_dma_intr(sc) 310 struct ncr53c9x_softc *sc; 311 { 312 struct esp_softc *esc = (struct esp_softc *)sc; 313 314 return (espdmaintr(esc)); 315 } 316 317 int 318 esp_dma_setup(sc, addr, len, datain, dmasize) 319 struct ncr53c9x_softc *sc; 320 void **addr; 321 size_t *len; 322 int datain; 323 size_t *dmasize; 324 { 325 struct esp_softc *esc = (struct esp_softc *)sc; 326 dbdma_command_t *cmdp; 327 u_int cmd; 328 u_int va; 329 int count, offset; 330 331 cmdp = esc->sc_dmacmd; 332 cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 333 334 count = *dmasize; 335 336 if (count / PAGE_SIZE > 32) 337 panic("esp: transfer size >= 128k"); 338 339 esc->sc_dmaaddr = addr; 340 esc->sc_dmalen = len; 341 esc->sc_dmasize = count; 342 343 va = (u_int)*esc->sc_dmaaddr; 344 offset = va & PGOFSET; 345 346 /* if va is not page-aligned, setup the first page */ 347 if (offset != 0) { 348 int rest = PAGE_SIZE - offset; /* the rest of the page */ 349 350 if (count > rest) { /* if continues to next page */ 351 DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((void *)va), 352 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 353 DBDMA_BRANCH_NEVER); 354 count -= rest; 355 va += rest; 356 cmdp++; 357 } 358 } 359 360 /* now va is page-aligned */ 361 while (count > PAGE_SIZE) { 362 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, kvtop((void *)va), 363 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 364 count -= PAGE_SIZE; 365 va += PAGE_SIZE; 366 cmdp++; 367 } 368 369 /* the last page (count <= PAGE_SIZE here) */ 370 cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 371 DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((void *)va), 372 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 373 cmdp++; 374 375 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 376 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 377 378 esc->sc_dma_direction = datain ? D_WRITE : 0; 379 380 return 0; 381 } 382 383 void 384 esp_dma_go(sc) 385 struct ncr53c9x_softc *sc; 386 { 387 struct esp_softc *esc = (struct esp_softc *)sc; 388 389 dbdma_start(esc->sc_dmareg, esc->sc_dmacmd); 390 esc->sc_dmaactive = 1; 391 } 392 393 void 394 esp_dma_stop(sc) 395 struct ncr53c9x_softc *sc; 396 { 397 struct esp_softc *esc = (struct esp_softc *)sc; 398 399 dbdma_stop(esc->sc_dmareg); 400 esc->sc_dmaactive = 0; 401 } 402 403 int 404 esp_dma_isactive(sc) 405 struct ncr53c9x_softc *sc; 406 { 407 struct esp_softc *esc = (struct esp_softc *)sc; 408 409 return (esc->sc_dmaactive); 410 } 411 412 413 /* 414 * Pseudo (chained) interrupt from the esp driver to kick the 415 * current running DMA transfer. I am replying on espintr() to 416 * pickup and clean errors for now 417 * 418 * return 1 if it was a DMA continue. 419 */ 420 int 421 espdmaintr(sc) 422 struct esp_softc *sc; 423 { 424 struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc; 425 int trans, resid; 426 u_long csr = sc->sc_dma_direction; 427 428 #if 0 429 if (csr & D_ERR_PEND) { 430 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 431 DMACSR(sc) |= D_INVALIDATE; 432 printf("%s: error: csr=%s\n", nsc->sc_dev.dv_xname, 433 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 434 return -1; 435 } 436 #endif 437 438 /* This is an "assertion" :) */ 439 if (sc->sc_dmaactive == 0) 440 panic("dmaintr: DMA wasn't active"); 441 442 /* dbdma_flush(sc->sc_dmareg); */ 443 444 /* DMA has stopped */ 445 dbdma_stop(sc->sc_dmareg); 446 sc->sc_dmaactive = 0; 447 448 if (sc->sc_dmasize == 0) { 449 /* A "Transfer Pad" operation completed */ 450 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 451 NCR_READ_REG(nsc, NCR_TCL) | 452 (NCR_READ_REG(nsc, NCR_TCM) << 8), 453 NCR_READ_REG(nsc, NCR_TCL), 454 NCR_READ_REG(nsc, NCR_TCM))); 455 return 0; 456 } 457 458 resid = 0; 459 /* 460 * If a transfer onto the SCSI bus gets interrupted by the device 461 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 462 * as residual since the ESP counter registers get decremented as 463 * bytes are clocked into the FIFO. 464 */ 465 if (!(csr & D_WRITE) && 466 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 467 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 468 } 469 470 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 471 /* 472 * `Terminal count' is off, so read the residue 473 * out of the ESP counter registers. 474 */ 475 resid += (NCR_READ_REG(nsc, NCR_TCL) | 476 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 477 ((nsc->sc_cfg2 & NCRCFG2_FE) 478 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 479 : 0)); 480 481 if (resid == 0 && sc->sc_dmasize == 65536 && 482 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 483 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 484 resid = 65536; 485 } 486 487 trans = sc->sc_dmasize - resid; 488 if (trans < 0) { /* transferred < 0 ? */ 489 #if 0 490 /* 491 * This situation can happen in perfectly normal operation 492 * if the ESP is reselected while using DMA to select 493 * another target. As such, don't print the warning. 494 */ 495 printf("%s: xfer (%d) > req (%d)\n", 496 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 497 #endif 498 trans = sc->sc_dmasize; 499 } 500 501 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 502 NCR_READ_REG(nsc, NCR_TCL), 503 NCR_READ_REG(nsc, NCR_TCM), 504 (nsc->sc_cfg2 & NCRCFG2_FE) 505 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 506 trans, resid)); 507 508 #if 0 509 if (csr & D_WRITE) 510 flushcache(*sc->sc_dmaaddr, trans); 511 #endif 512 513 *sc->sc_dmalen -= trans; 514 *sc->sc_dmaaddr = (char *)*sc->sc_dmaaddr + trans; 515 516 #if 0 /* this is not normal operation just yet */ 517 if (*sc->sc_dmalen == 0 || 518 nsc->sc_phase != nsc->sc_prevphase) 519 return 0; 520 521 /* and again */ 522 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 523 return 1; 524 #endif 525 return 0; 526 } 527 528 void 529 esp_shutdownhook(arg) 530 void *arg; 531 { 532 struct ncr53c9x_softc *sc = arg; 533 534 NCRCMD(sc, NCRCMD_RSTSCSI); 535 } 536
Indexes created Thu Oct 02 14:10:14 GMT 2025