esp.c revision 1.33
1 /* $NetBSD: esp.c,v 1.33 2021/03/05 07:15:53 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1994 Peter Galbavy 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.33 2021/03/05 07:15:53 rin Exp $"); 74 75 #include <sys/types.h> 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/errno.h> 80 #include <sys/ioctl.h> 81 #include <sys/device.h> 82 #include <sys/buf.h> 83 #include <sys/proc.h> 84 #include <sys/queue.h> 85 #include <sys/malloc.h> 86 87 #include <dev/scsipi/scsi_all.h> 88 #include <dev/scsipi/scsipi_all.h> 89 #include <dev/scsipi/scsiconf.h> 90 #include <dev/scsipi/scsi_message.h> 91 92 #include <dev/ofw/openfirm.h> 93 94 #include <machine/cpu.h> 95 #include <machine/autoconf.h> 96 #include <machine/pio.h> 97 98 #include <dev/ic/ncr53c9xreg.h> 99 #include <dev/ic/ncr53c9xvar.h> 100 101 #include <macppc/dev/dbdma.h> 102 #include <macppc/dev/espvar.h> 103 104 int espmatch(device_t, cfdata_t, void *); 105 void espattach(device_t, device_t, void *); 106 107 /* Linkup to the rest of the kernel */ 108 CFATTACH_DECL_NEW(esp, sizeof(struct esp_softc), 109 espmatch, espattach, NULL, NULL); 110 111 /* 112 * Functions and the switch for the MI code. 113 */ 114 static uint8_t esp_read_reg(struct ncr53c9x_softc *, int); 115 static void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t); 116 static int esp_dma_isintr(struct ncr53c9x_softc *); 117 static void esp_dma_reset(struct ncr53c9x_softc *); 118 static int esp_dma_intr(struct ncr53c9x_softc *); 119 static int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, 120 size_t *, int, size_t *); 121 static void esp_dma_go(struct ncr53c9x_softc *); 122 static void esp_dma_stop(struct ncr53c9x_softc *); 123 static int esp_dma_isactive(struct ncr53c9x_softc *); 124 125 static struct ncr53c9x_glue esp_glue = { 126 esp_read_reg, 127 esp_write_reg, 128 esp_dma_isintr, 129 esp_dma_reset, 130 esp_dma_intr, 131 esp_dma_setup, 132 esp_dma_go, 133 esp_dma_stop, 134 esp_dma_isactive, 135 NULL, /* gl_clear_latched_intr */ 136 }; 137 138 static int espdmaintr(struct esp_softc *); 139 static bool esp_shutdown(device_t, int); 140 141 int 142 espmatch(device_t parent, cfdata_t cf, void *aux) 143 { 144 struct confargs *ca = aux; 145 146 if (strcmp(ca->ca_name, "53c94") != 0) 147 return 0; 148 149 if (ca->ca_nreg != 16) 150 return 0; 151 if (ca->ca_nintr != 8) 152 return 0; 153 154 return 1; 155 } 156 157 /* 158 * Attach this instance, and then all the sub-devices 159 */ 160 void 161 espattach(device_t parent, device_t self, void *aux) 162 { 163 struct esp_softc *esc = device_private(self); 164 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 165 struct confargs *ca = aux; 166 u_int *reg; 167 int sz; 168 169 /* 170 * Set up glue for MI code early; we use some of it here. 171 */ 172 sc->sc_dev = self; 173 sc->sc_glue = &esp_glue; 174 175 esc->sc_node = ca->ca_node; 176 esc->sc_pri = ca->ca_intr[0]; 177 aprint_normal(" irq %d", esc->sc_pri); 178 179 /* 180 * Map my registers in. 181 */ 182 reg = ca->ca_reg; 183 esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1], false); 184 esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3], false); 185 186 /* Allocate 16-byte aligned DMA command space */ 187 esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20, NULL); 188 189 /* Other settings */ 190 sc->sc_id = 7; 191 sz = OF_getprop(ca->ca_node, "clock-frequency", 192 &sc->sc_freq, sizeof(int)); 193 if (sz != sizeof(int)) 194 sc->sc_freq = 25000000; 195 196 /* gimme MHz */ 197 sc->sc_freq /= 1000000; 198 199 /* esc->sc_dma->sc_esp = esc;*/ 200 201 /* 202 * XXX More of this should be in ncr53c9x_attach(), but 203 * XXX should we really poke around the chip that much in 204 * XXX the MI code? Think about this more... 205 */ 206 207 /* 208 * Set up static configuration info. 209 */ 210 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 211 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 212 sc->sc_cfg3 = NCRCFG3_CDB; 213 sc->sc_rev = NCR_VARIANT_NCR53C94; 214 215 /* 216 * XXX minsync and maxxfer _should_ be set up in MI code, 217 * XXX but it appears to have some dependency on what sort 218 * XXX of DMA we're hooked up to, etc. 219 */ 220 221 /* 222 * This is the value used to start sync negotiations 223 * Note that the NCR register "SYNCTP" is programmed 224 * in "clocks per byte", and has a minimum value of 4. 225 * The SCSI period used in negotiation is one-fourth 226 * of the time (in nanoseconds) needed to transfer one byte. 227 * Since the chip's clock is given in MHz, we have the following 228 * formula: 4 * period = (1000 / freq) * 4 229 */ 230 sc->sc_minsync = 1000 / sc->sc_freq; 231 232 sc->sc_maxxfer = 64 * 1024; 233 234 /* and the interuppts */ 235 intr_establish_xname(esc->sc_pri, IST_EDGE, IPL_BIO, ncr53c9x_intr, sc, 236 device_xname(self)); 237 238 /* Do the common parts of attachment. */ 239 sc->sc_adapter.adapt_minphys = minphys; 240 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 241 ncr53c9x_attach(sc); 242 243 /* Turn on target selection using the `DMA' method */ 244 sc->sc_features |= NCR_F_DMASELECT; 245 246 /* Reset SCSI bus when halt. */ 247 if (!pmf_device_register1(self, NULL, NULL, esp_shutdown)) 248 aprint_error_dev(self, "couldn't establish power handler\n"); 249 } 250 251 /* 252 * Glue functions. 253 */ 254 255 uint8_t 256 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 257 { 258 struct esp_softc *esc = (struct esp_softc *)sc; 259 260 return in8(&esc->sc_reg[reg * 16]); 261 /*return (esc->sc_reg[reg * 16]);*/ 262 } 263 264 void 265 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 266 { 267 struct esp_softc *esc = (struct esp_softc *)sc; 268 uint8_t v = val; 269 270 out8(&esc->sc_reg[reg * 16], v); 271 /*esc->sc_reg[reg * 16] = v;*/ 272 } 273 274 int 275 esp_dma_isintr(struct ncr53c9x_softc *sc) 276 { 277 278 return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 279 } 280 281 void 282 esp_dma_reset(struct ncr53c9x_softc *sc) 283 { 284 struct esp_softc *esc = (struct esp_softc *)sc; 285 286 dbdma_stop(esc->sc_dmareg); 287 esc->sc_dmaactive = 0; 288 } 289 290 int 291 esp_dma_intr(struct ncr53c9x_softc *sc) 292 { 293 struct esp_softc *esc = (struct esp_softc *)sc; 294 295 return espdmaintr(esc); 296 } 297 298 int 299 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 300 int datain, size_t *dmasize) 301 { 302 struct esp_softc *esc = (struct esp_softc *)sc; 303 dbdma_command_t *cmdp; 304 u_int cmd; 305 u_int va; 306 int count, offset; 307 308 cmdp = esc->sc_dmacmd; 309 cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 310 311 count = *dmasize; 312 313 if (count / PAGE_SIZE > 32) 314 panic("%s: transfer size >= 128k", device_xname(sc->sc_dev)); 315 316 esc->sc_dmaaddr = addr; 317 esc->sc_dmalen = len; 318 esc->sc_dmasize = count; 319 320 va = (u_int)*esc->sc_dmaaddr; 321 offset = va & PGOFSET; 322 323 /* if va is not page-aligned, setup the first page */ 324 if (offset != 0) { 325 int rest = PAGE_SIZE - offset; /* the rest of the page */ 326 327 if (count > rest) { /* if continues to next page */ 328 DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((void *)va), 329 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 330 DBDMA_BRANCH_NEVER); 331 count -= rest; 332 va += rest; 333 cmdp++; 334 } 335 } 336 337 /* now va is page-aligned */ 338 while (count > PAGE_SIZE) { 339 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, kvtop((void *)va), 340 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 341 count -= PAGE_SIZE; 342 va += PAGE_SIZE; 343 cmdp++; 344 } 345 346 /* the last page (count <= PAGE_SIZE here) */ 347 cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 348 DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((void *)va), 349 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 350 cmdp++; 351 352 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 353 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 354 355 esc->sc_dma_direction = datain ? D_WRITE : 0; 356 357 return 0; 358 } 359 360 void 361 esp_dma_go(struct ncr53c9x_softc *sc) 362 { 363 struct esp_softc *esc = (struct esp_softc *)sc; 364 365 dbdma_start(esc->sc_dmareg, esc->sc_dmacmd); 366 esc->sc_dmaactive = 1; 367 } 368 369 void 370 esp_dma_stop(struct ncr53c9x_softc *sc) 371 { 372 struct esp_softc *esc = (struct esp_softc *)sc; 373 374 dbdma_stop(esc->sc_dmareg); 375 esc->sc_dmaactive = 0; 376 } 377 378 int 379 esp_dma_isactive(struct ncr53c9x_softc *sc) 380 { 381 struct esp_softc *esc = (struct esp_softc *)sc; 382 383 return esc->sc_dmaactive; 384 } 385 386 387 /* 388 * Pseudo (chained) interrupt from the esp driver to kick the 389 * current running DMA transfer. I am replying on espintr() to 390 * pickup and clean errors for now 391 * 392 * return 1 if it was a DMA continue. 393 */ 394 int 395 espdmaintr(struct esp_softc *sc) 396 { 397 struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc; 398 int trans, resid; 399 u_long csr = sc->sc_dma_direction; 400 401 #if 0 402 if (csr & D_ERR_PEND) { 403 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 404 DMACSR(sc) |= D_INVALIDATE; 405 snprintb(bits, sizeof(bits), DMACSRBITS, csr); 406 printf("%s: error: csr=%s\n", device_xname(nsc->sc_dev), bits); 407 return -1; 408 } 409 #endif 410 411 /* This is an "assertion" :) */ 412 if (sc->sc_dmaactive == 0) 413 panic("%s: DMA wasn't active", __func__); 414 415 /* dbdma_flush(sc->sc_dmareg); */ 416 417 /* DMA has stopped */ 418 dbdma_stop(sc->sc_dmareg); 419 sc->sc_dmaactive = 0; 420 421 if (sc->sc_dmasize == 0) { 422 /* A "Transfer Pad" operation completed */ 423 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 424 NCR_READ_REG(nsc, NCR_TCL) | 425 (NCR_READ_REG(nsc, NCR_TCM) << 8), 426 NCR_READ_REG(nsc, NCR_TCL), 427 NCR_READ_REG(nsc, NCR_TCM))); 428 return 0; 429 } 430 431 resid = 0; 432 /* 433 * If a transfer onto the SCSI bus gets interrupted by the device 434 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 435 * as residual since the ESP counter registers get decremented as 436 * bytes are clocked into the FIFO. 437 */ 438 if (!(csr & D_WRITE) && 439 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 440 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 441 } 442 443 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 444 /* 445 * `Terminal count' is off, so read the residue 446 * out of the ESP counter registers. 447 */ 448 resid += (NCR_READ_REG(nsc, NCR_TCL) | 449 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 450 ((nsc->sc_cfg2 & NCRCFG2_FE) 451 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 452 : 0)); 453 454 if (resid == 0 && sc->sc_dmasize == 65536 && 455 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 456 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 457 resid = 65536; 458 } 459 460 trans = sc->sc_dmasize - resid; 461 if (trans < 0) { /* transferred < 0 ? */ 462 #if 0 463 /* 464 * This situation can happen in perfectly normal operation 465 * if the ESP is reselected while using DMA to select 466 * another target. As such, don't print the warning. 467 */ 468 printf("%s: xfer (%d) > req (%d)\n", 469 device_xname(nsc->sc_dev), trans, sc->sc_dmasize); 470 #endif 471 trans = sc->sc_dmasize; 472 } 473 474 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 475 NCR_READ_REG(nsc, NCR_TCL), 476 NCR_READ_REG(nsc, NCR_TCM), 477 (nsc->sc_cfg2 & NCRCFG2_FE) 478 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 479 trans, resid)); 480 481 #if 0 482 if (csr & D_WRITE) 483 flushcache(*sc->sc_dmaaddr, trans); 484 #endif 485 486 *sc->sc_dmalen -= trans; 487 *sc->sc_dmaaddr += trans; 488 489 #if 0 /* this is not normal operation just yet */ 490 if (*sc->sc_dmalen == 0 || 491 nsc->sc_phase != nsc->sc_prevphase) 492 return 0; 493 494 /* and again */ 495 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 496 return 1; 497 #endif 498 return 0; 499 } 500 501 bool 502 esp_shutdown(device_t self, int howto) 503 { 504 struct esp_softc *esc; 505 struct ncr53c9x_softc *sc; 506 507 esc = device_private(self); 508 sc = &esc->sc_ncr53c9x; 509 NCRCMD(sc, NCRCMD_RSTSCSI); 510 511 return true; 512 } 513
Indexes created Thu Oct 02 01:09:59 GMT 2025