esp.c revision 1.4
1 /* $NetBSD: esp.c,v 1.4 1998/06/19 14:11:32 tsubai Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Charles M. Hannum. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * Copyright (c) 1994 Peter Galbavy 71 * Copyright (c) 1995 Paul Kranenburg 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 3. All advertising materials mentioning features or use of this software 83 * must display the following acknowledgement: 84 * This product includes software developed by Peter Galbavy 85 * 4. The name of the author may not be used to endorse or promote products 86 * derived from this software without specific prior written permission. 87 * 88 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 89 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 90 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 91 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 92 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 93 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 95 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 96 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 97 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98 * POSSIBILITY OF SUCH DAMAGE. 99 */ 100 101 /* 102 * Based on aic6360 by Jarle Greipsland 103 * 104 * Acknowledgements: Many of the algorithms used in this driver are 105 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 106 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 107 */ 108 109 #include <sys/types.h> 110 #include <sys/param.h> 111 #include <sys/systm.h> 112 #include <sys/kernel.h> 113 #include <sys/errno.h> 114 #include <sys/ioctl.h> 115 #include <sys/device.h> 116 #include <sys/buf.h> 117 #include <sys/proc.h> 118 #include <sys/user.h> 119 #include <sys/queue.h> 120 #include <sys/malloc.h> 121 122 #include <vm/vm_param.h> /* for trunc_page */ 123 124 #include <dev/scsipi/scsi_all.h> 125 #include <dev/scsipi/scsipi_all.h> 126 #include <dev/scsipi/scsiconf.h> 127 #include <dev/scsipi/scsi_message.h> 128 129 #include <dev/ofw/openfirm.h> 130 131 #include <machine/cpu.h> 132 #include <machine/autoconf.h> 133 #include <machine/pio.h> 134 135 #include <dev/ic/ncr53c9xreg.h> 136 #include <dev/ic/ncr53c9xvar.h> 137 138 #include <macppc/dev/dbdma.h> 139 #include <macppc/dev/espvar.h> 140 141 void espattach __P((struct device *, struct device *, void *)); 142 int espmatch __P((struct device *, struct cfdata *, void *)); 143 144 /* Linkup to the rest of the kernel */ 145 struct cfattach esp_ca = { 146 sizeof(struct esp_softc), espmatch, espattach 147 }; 148 149 struct scsipi_adapter esp_switch = { 150 ncr53c9x_scsi_cmd, 151 minphys, /* no max at this level; handled by DMA code */ 152 NULL, 153 NULL, 154 }; 155 156 struct scsipi_device esp_dev = { 157 NULL, /* Use default error handler */ 158 NULL, /* have a queue, served by this */ 159 NULL, /* have no async handler */ 160 NULL, /* Use default 'done' routine */ 161 }; 162 163 /* 164 * Functions and the switch for the MI code. 165 */ 166 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 167 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 168 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 169 void esp_dma_reset __P((struct ncr53c9x_softc *)); 170 int esp_dma_intr __P((struct ncr53c9x_softc *)); 171 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 172 size_t *, int, size_t *)); 173 void esp_dma_go __P((struct ncr53c9x_softc *)); 174 void esp_dma_stop __P((struct ncr53c9x_softc *)); 175 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 176 177 struct ncr53c9x_glue esp_glue = { 178 esp_read_reg, 179 esp_write_reg, 180 esp_dma_isintr, 181 esp_dma_reset, 182 esp_dma_intr, 183 esp_dma_setup, 184 esp_dma_go, 185 esp_dma_stop, 186 esp_dma_isactive, 187 NULL, /* gl_clear_latched_intr */ 188 }; 189 190 static int espdmaintr __P((struct esp_softc *)); 191 static void esp_shutdownhook __P((void *)); 192 193 int 194 espmatch(parent, cf, aux) 195 struct device *parent; 196 struct cfdata *cf; 197 void *aux; 198 { 199 struct confargs *ca = aux; 200 201 if (strcmp(ca->ca_name, "53c94") != 0) 202 return 0; 203 204 if (ca->ca_nreg != 16) 205 return 0; 206 if (ca->ca_nintr != 8) 207 return 0; 208 209 return 1; 210 } 211 212 /* 213 * Attach this instance, and then all the sub-devices 214 */ 215 void 216 espattach(parent, self, aux) 217 struct device *parent, *self; 218 void *aux; 219 { 220 register struct confargs *ca = aux; 221 struct esp_softc *esc = (void *)self; 222 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 223 u_int *reg; 224 int sz; 225 226 /* 227 * Set up glue for MI code early; we use some of it here. 228 */ 229 sc->sc_glue = &esp_glue; 230 231 esc->sc_node = ca->ca_node; 232 esc->sc_pri = ca->ca_intr[0]; 233 printf(" irq %d", esc->sc_pri); 234 235 /* 236 * Map my registers in. 237 */ 238 reg = ca->ca_reg; 239 esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1]); 240 esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3]); 241 242 /* Allocate 16-byte aligned dma command space */ 243 esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 244 245 /* Other settings */ 246 sc->sc_id = 7; 247 sz = OF_getprop(ca->ca_node, "clock-frequency", 248 &sc->sc_freq, sizeof(int)); 249 if (sz != sizeof(int)) 250 sc->sc_freq = 25000000; 251 252 /* gimme Mhz */ 253 sc->sc_freq /= 1000000; 254 255 /* esc->sc_dma->sc_esp = esc;*/ 256 257 /* 258 * XXX More of this should be in ncr53c9x_attach(), but 259 * XXX should we really poke around the chip that much in 260 * XXX the MI code? Think about this more... 261 */ 262 263 /* 264 * Set up static configuration info. 265 */ 266 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 267 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 268 sc->sc_cfg3 = NCRCFG3_CDB; 269 sc->sc_rev = NCR_VARIANT_NCR53C94; 270 271 /* 272 * XXX minsync and maxxfer _should_ be set up in MI code, 273 * XXX but it appears to have some dependency on what sort 274 * XXX of DMA we're hooked up to, etc. 275 */ 276 277 /* 278 * This is the value used to start sync negotiations 279 * Note that the NCR register "SYNCTP" is programmed 280 * in "clocks per byte", and has a minimum value of 4. 281 * The SCSI period used in negotiation is one-fourth 282 * of the time (in nanoseconds) needed to transfer one byte. 283 * Since the chip's clock is given in MHz, we have the following 284 * formula: 4 * period = (1000 / freq) * 4 285 */ 286 sc->sc_minsync = 1000 / sc->sc_freq; 287 288 sc->sc_maxxfer = 64 * 1024; 289 290 /* and the interuppts */ 291 intr_establish(esc->sc_pri, IST_LEVEL, IPL_BIO, (void *)ncr53c9x_intr, 292 sc); 293 294 /* Reset SCSI bus when halt. */ 295 shutdownhook_establish(esp_shutdownhook, sc); 296 297 /* Do the common parts of attachment. */ 298 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 299 300 /* Turn on target selection using the `dma' method */ 301 ncr53c9x_dmaselect = 1; 302 } 303 304 /* 305 * Glue functions. 306 */ 307 308 u_char 309 esp_read_reg(sc, reg) 310 struct ncr53c9x_softc *sc; 311 int reg; 312 { 313 struct esp_softc *esc = (struct esp_softc *)sc; 314 315 return in8(&esc->sc_reg[reg * 16]); 316 /*return (esc->sc_reg[reg * 16]);*/ 317 } 318 319 void 320 esp_write_reg(sc, reg, val) 321 struct ncr53c9x_softc *sc; 322 int reg; 323 u_char val; 324 { 325 struct esp_softc *esc = (struct esp_softc *)sc; 326 u_char v = val; 327 328 out8(&esc->sc_reg[reg * 16], v); 329 /*esc->sc_reg[reg * 16] = v;*/ 330 } 331 332 int 333 esp_dma_isintr(sc) 334 struct ncr53c9x_softc *sc; 335 { 336 return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 337 } 338 339 void 340 esp_dma_reset(sc) 341 struct ncr53c9x_softc *sc; 342 { 343 struct esp_softc *esc = (struct esp_softc *)sc; 344 345 dbdma_stop(esc->sc_dmareg); 346 esc->sc_dmaactive = 0; 347 } 348 349 int 350 esp_dma_intr(sc) 351 struct ncr53c9x_softc *sc; 352 { 353 struct esp_softc *esc = (struct esp_softc *)sc; 354 355 return (espdmaintr(esc)); 356 } 357 358 int 359 esp_dma_setup(sc, addr, len, datain, dmasize) 360 struct ncr53c9x_softc *sc; 361 caddr_t *addr; 362 size_t *len; 363 int datain; 364 size_t *dmasize; 365 { 366 struct esp_softc *esc = (struct esp_softc *)sc; 367 dbdma_command_t *cmdp; 368 u_int cmd; 369 u_int va; 370 int count, offset; 371 372 cmdp = esc->sc_dmacmd; 373 cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 374 375 count = *dmasize; 376 377 if (count / NBPG > 32) 378 panic("esp: transfer size >= 128k"); 379 380 esc->sc_dmaaddr = addr; 381 esc->sc_dmalen = len; 382 esc->sc_dmasize = count; 383 384 va = (u_int)*esc->sc_dmaaddr; 385 offset = va & PGOFSET; 386 387 /* if va is not page-aligned, setup the first page */ 388 if (offset != 0) { 389 int rest = NBPG - offset; /* the rest of the page */ 390 391 if (count > rest) { /* if continues to next page */ 392 DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((caddr_t)va), 393 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 394 DBDMA_BRANCH_NEVER); 395 count -= rest; 396 va += rest; 397 cmdp++; 398 } 399 } 400 401 /* now va is page-aligned */ 402 while (count > NBPG) { 403 DBDMA_BUILD(cmdp, cmd, 0, NBPG, kvtop((caddr_t)va), 404 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 405 count -= NBPG; 406 va += NBPG; 407 cmdp++; 408 } 409 410 /* the last page (count <= NBPG here) */ 411 cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 412 DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((caddr_t)va), 413 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 414 cmdp++; 415 416 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 417 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 418 419 esc->sc_dma_direction = datain ? D_WRITE : 0; 420 421 return 0; 422 } 423 424 void 425 esp_dma_go(sc) 426 struct ncr53c9x_softc *sc; 427 { 428 struct esp_softc *esc = (struct esp_softc *)sc; 429 430 dbdma_start(esc->sc_dmareg, esc->sc_dmacmd); 431 esc->sc_dmaactive = 1; 432 } 433 434 void 435 esp_dma_stop(sc) 436 struct ncr53c9x_softc *sc; 437 { 438 struct esp_softc *esc = (struct esp_softc *)sc; 439 440 dbdma_stop(esc->sc_dmareg); 441 esc->sc_dmaactive = 0; 442 } 443 444 int 445 esp_dma_isactive(sc) 446 struct ncr53c9x_softc *sc; 447 { 448 struct esp_softc *esc = (struct esp_softc *)sc; 449 450 return (esc->sc_dmaactive); 451 } 452 453 454 /* 455 * Pseudo (chained) interrupt from the esp driver to kick the 456 * current running DMA transfer. I am replying on espintr() to 457 * pickup and clean errors for now 458 * 459 * return 1 if it was a DMA continue. 460 */ 461 int 462 espdmaintr(sc) 463 struct esp_softc *sc; 464 { 465 struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc; 466 int trans, resid; 467 u_long csr = sc->sc_dma_direction; 468 469 #if 0 470 if (csr & D_ERR_PEND) { 471 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 472 DMACSR(sc) |= D_INVALIDATE; 473 printf("%s: error: csr=%s\n", nsc->sc_dev.dv_xname, 474 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 475 return -1; 476 } 477 #endif 478 479 /* This is an "assertion" :) */ 480 if (sc->sc_dmaactive == 0) 481 panic("dmaintr: DMA wasn't active"); 482 483 /* dbdma_flush(sc->sc_dmareg); */ 484 485 /* DMA has stopped */ 486 dbdma_stop(sc->sc_dmareg); 487 sc->sc_dmaactive = 0; 488 489 if (sc->sc_dmasize == 0) { 490 /* A "Transfer Pad" operation completed */ 491 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 492 NCR_READ_REG(nsc, NCR_TCL) | 493 (NCR_READ_REG(nsc, NCR_TCM) << 8), 494 NCR_READ_REG(nsc, NCR_TCL), 495 NCR_READ_REG(nsc, NCR_TCM))); 496 return 0; 497 } 498 499 resid = 0; 500 /* 501 * If a transfer onto the SCSI bus gets interrupted by the device 502 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 503 * as residual since the ESP counter registers get decremented as 504 * bytes are clocked into the FIFO. 505 */ 506 if (!(csr & D_WRITE) && 507 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 508 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 509 } 510 511 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 512 /* 513 * `Terminal count' is off, so read the residue 514 * out of the ESP counter registers. 515 */ 516 resid += (NCR_READ_REG(nsc, NCR_TCL) | 517 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 518 ((nsc->sc_cfg2 & NCRCFG2_FE) 519 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 520 : 0)); 521 522 if (resid == 0 && sc->sc_dmasize == 65536 && 523 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 524 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 525 resid = 65536; 526 } 527 528 trans = sc->sc_dmasize - resid; 529 if (trans < 0) { /* transferred < 0 ? */ 530 #if 0 531 /* 532 * This situation can happen in perfectly normal operation 533 * if the ESP is reselected while using DMA to select 534 * another target. As such, don't print the warning. 535 */ 536 printf("%s: xfer (%d) > req (%d)\n", 537 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 538 #endif 539 trans = sc->sc_dmasize; 540 } 541 542 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 543 NCR_READ_REG(nsc, NCR_TCL), 544 NCR_READ_REG(nsc, NCR_TCM), 545 (nsc->sc_cfg2 & NCRCFG2_FE) 546 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 547 trans, resid)); 548 549 #if 0 550 if (csr & D_WRITE) 551 flushcache(*sc->sc_dmaaddr, trans); 552 #endif 553 554 *sc->sc_dmalen -= trans; 555 *sc->sc_dmaaddr += trans; 556 557 #if 0 /* this is not normal operation just yet */ 558 if (*sc->sc_dmalen == 0 || 559 nsc->sc_phase != nsc->sc_prevphase) 560 return 0; 561 562 /* and again */ 563 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 564 return 1; 565 #endif 566 return 0; 567 } 568 569 void 570 esp_shutdownhook(arg) 571 void *arg; 572 { 573 struct ncr53c9x_softc *sc = arg; 574 575 NCRCMD(sc, NCRCMD_RSTSCSI); 576 } 577
Indexes created Wed Oct 01 19:09:53 GMT 2025