esp.c revision 1.5
1 /* $NetBSD: esp.c,v 1.5 1998/08/15 04:16:55 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center and Charles M. Hannum. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * Copyright (c) 1995 Paul Kranenburg 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Peter Galbavy 56 * 4. The name of the author may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 61 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 62 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 67 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 68 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Based on aic6360 by Jarle Greipsland 74 * 75 * Acknowledgements: Many of the algorithms used in this driver are 76 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 77 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 78 */ 79 80 #include <sys/types.h> 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/errno.h> 85 #include <sys/ioctl.h> 86 #include <sys/device.h> 87 #include <sys/buf.h> 88 #include <sys/proc.h> 89 #include <sys/user.h> 90 #include <sys/queue.h> 91 #include <sys/malloc.h> 92 93 #include <vm/vm_param.h> /* for trunc_page */ 94 95 #include <dev/scsipi/scsi_all.h> 96 #include <dev/scsipi/scsipi_all.h> 97 #include <dev/scsipi/scsiconf.h> 98 #include <dev/scsipi/scsi_message.h> 99 100 #include <dev/ofw/openfirm.h> 101 102 #include <machine/cpu.h> 103 #include <machine/autoconf.h> 104 #include <machine/pio.h> 105 106 #include <dev/ic/ncr53c9xreg.h> 107 #include <dev/ic/ncr53c9xvar.h> 108 109 #include <macppc/dev/dbdma.h> 110 #include <macppc/dev/espvar.h> 111 112 void espattach __P((struct device *, struct device *, void *)); 113 int espmatch __P((struct device *, struct cfdata *, void *)); 114 115 /* Linkup to the rest of the kernel */ 116 struct cfattach esp_ca = { 117 sizeof(struct esp_softc), espmatch, espattach 118 }; 119 120 struct scsipi_adapter esp_switch = { 121 ncr53c9x_scsi_cmd, 122 minphys, /* no max at this level; handled by DMA code */ 123 NULL, 124 NULL, 125 }; 126 127 struct scsipi_device esp_dev = { 128 NULL, /* Use default error handler */ 129 NULL, /* have a queue, served by this */ 130 NULL, /* have no async handler */ 131 NULL, /* Use default 'done' routine */ 132 }; 133 134 /* 135 * Functions and the switch for the MI code. 136 */ 137 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 138 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 139 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 140 void esp_dma_reset __P((struct ncr53c9x_softc *)); 141 int esp_dma_intr __P((struct ncr53c9x_softc *)); 142 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 143 size_t *, int, size_t *)); 144 void esp_dma_go __P((struct ncr53c9x_softc *)); 145 void esp_dma_stop __P((struct ncr53c9x_softc *)); 146 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 147 148 struct ncr53c9x_glue esp_glue = { 149 esp_read_reg, 150 esp_write_reg, 151 esp_dma_isintr, 152 esp_dma_reset, 153 esp_dma_intr, 154 esp_dma_setup, 155 esp_dma_go, 156 esp_dma_stop, 157 esp_dma_isactive, 158 NULL, /* gl_clear_latched_intr */ 159 }; 160 161 static int espdmaintr __P((struct esp_softc *)); 162 static void esp_shutdownhook __P((void *)); 163 164 int 165 espmatch(parent, cf, aux) 166 struct device *parent; 167 struct cfdata *cf; 168 void *aux; 169 { 170 struct confargs *ca = aux; 171 172 if (strcmp(ca->ca_name, "53c94") != 0) 173 return 0; 174 175 if (ca->ca_nreg != 16) 176 return 0; 177 if (ca->ca_nintr != 8) 178 return 0; 179 180 return 1; 181 } 182 183 /* 184 * Attach this instance, and then all the sub-devices 185 */ 186 void 187 espattach(parent, self, aux) 188 struct device *parent, *self; 189 void *aux; 190 { 191 register struct confargs *ca = aux; 192 struct esp_softc *esc = (void *)self; 193 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 194 u_int *reg; 195 int sz; 196 197 /* 198 * Set up glue for MI code early; we use some of it here. 199 */ 200 sc->sc_glue = &esp_glue; 201 202 esc->sc_node = ca->ca_node; 203 esc->sc_pri = ca->ca_intr[0]; 204 printf(" irq %d", esc->sc_pri); 205 206 /* 207 * Map my registers in. 208 */ 209 reg = ca->ca_reg; 210 esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1]); 211 esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3]); 212 213 /* Allocate 16-byte aligned dma command space */ 214 esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 215 216 /* Other settings */ 217 sc->sc_id = 7; 218 sz = OF_getprop(ca->ca_node, "clock-frequency", 219 &sc->sc_freq, sizeof(int)); 220 if (sz != sizeof(int)) 221 sc->sc_freq = 25000000; 222 223 /* gimme Mhz */ 224 sc->sc_freq /= 1000000; 225 226 /* esc->sc_dma->sc_esp = esc;*/ 227 228 /* 229 * XXX More of this should be in ncr53c9x_attach(), but 230 * XXX should we really poke around the chip that much in 231 * XXX the MI code? Think about this more... 232 */ 233 234 /* 235 * Set up static configuration info. 236 */ 237 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 238 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 239 sc->sc_cfg3 = NCRCFG3_CDB; 240 sc->sc_rev = NCR_VARIANT_NCR53C94; 241 242 /* 243 * XXX minsync and maxxfer _should_ be set up in MI code, 244 * XXX but it appears to have some dependency on what sort 245 * XXX of DMA we're hooked up to, etc. 246 */ 247 248 /* 249 * This is the value used to start sync negotiations 250 * Note that the NCR register "SYNCTP" is programmed 251 * in "clocks per byte", and has a minimum value of 4. 252 * The SCSI period used in negotiation is one-fourth 253 * of the time (in nanoseconds) needed to transfer one byte. 254 * Since the chip's clock is given in MHz, we have the following 255 * formula: 4 * period = (1000 / freq) * 4 256 */ 257 sc->sc_minsync = 1000 / sc->sc_freq; 258 259 sc->sc_maxxfer = 64 * 1024; 260 261 /* and the interuppts */ 262 intr_establish(esc->sc_pri, IST_LEVEL, IPL_BIO, (void *)ncr53c9x_intr, 263 sc); 264 265 /* Reset SCSI bus when halt. */ 266 shutdownhook_establish(esp_shutdownhook, sc); 267 268 /* Do the common parts of attachment. */ 269 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 270 271 /* Turn on target selection using the `dma' method */ 272 ncr53c9x_dmaselect = 1; 273 } 274 275 /* 276 * Glue functions. 277 */ 278 279 u_char 280 esp_read_reg(sc, reg) 281 struct ncr53c9x_softc *sc; 282 int reg; 283 { 284 struct esp_softc *esc = (struct esp_softc *)sc; 285 286 return in8(&esc->sc_reg[reg * 16]); 287 /*return (esc->sc_reg[reg * 16]);*/ 288 } 289 290 void 291 esp_write_reg(sc, reg, val) 292 struct ncr53c9x_softc *sc; 293 int reg; 294 u_char val; 295 { 296 struct esp_softc *esc = (struct esp_softc *)sc; 297 u_char v = val; 298 299 out8(&esc->sc_reg[reg * 16], v); 300 /*esc->sc_reg[reg * 16] = v;*/ 301 } 302 303 int 304 esp_dma_isintr(sc) 305 struct ncr53c9x_softc *sc; 306 { 307 return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 308 } 309 310 void 311 esp_dma_reset(sc) 312 struct ncr53c9x_softc *sc; 313 { 314 struct esp_softc *esc = (struct esp_softc *)sc; 315 316 dbdma_stop(esc->sc_dmareg); 317 esc->sc_dmaactive = 0; 318 } 319 320 int 321 esp_dma_intr(sc) 322 struct ncr53c9x_softc *sc; 323 { 324 struct esp_softc *esc = (struct esp_softc *)sc; 325 326 return (espdmaintr(esc)); 327 } 328 329 int 330 esp_dma_setup(sc, addr, len, datain, dmasize) 331 struct ncr53c9x_softc *sc; 332 caddr_t *addr; 333 size_t *len; 334 int datain; 335 size_t *dmasize; 336 { 337 struct esp_softc *esc = (struct esp_softc *)sc; 338 dbdma_command_t *cmdp; 339 u_int cmd; 340 u_int va; 341 int count, offset; 342 343 cmdp = esc->sc_dmacmd; 344 cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 345 346 count = *dmasize; 347 348 if (count / NBPG > 32) 349 panic("esp: transfer size >= 128k"); 350 351 esc->sc_dmaaddr = addr; 352 esc->sc_dmalen = len; 353 esc->sc_dmasize = count; 354 355 va = (u_int)*esc->sc_dmaaddr; 356 offset = va & PGOFSET; 357 358 /* if va is not page-aligned, setup the first page */ 359 if (offset != 0) { 360 int rest = NBPG - offset; /* the rest of the page */ 361 362 if (count > rest) { /* if continues to next page */ 363 DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((caddr_t)va), 364 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 365 DBDMA_BRANCH_NEVER); 366 count -= rest; 367 va += rest; 368 cmdp++; 369 } 370 } 371 372 /* now va is page-aligned */ 373 while (count > NBPG) { 374 DBDMA_BUILD(cmdp, cmd, 0, NBPG, kvtop((caddr_t)va), 375 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 376 count -= NBPG; 377 va += NBPG; 378 cmdp++; 379 } 380 381 /* the last page (count <= NBPG here) */ 382 cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 383 DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((caddr_t)va), 384 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 385 cmdp++; 386 387 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 388 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 389 390 esc->sc_dma_direction = datain ? D_WRITE : 0; 391 392 return 0; 393 } 394 395 void 396 esp_dma_go(sc) 397 struct ncr53c9x_softc *sc; 398 { 399 struct esp_softc *esc = (struct esp_softc *)sc; 400 401 dbdma_start(esc->sc_dmareg, esc->sc_dmacmd); 402 esc->sc_dmaactive = 1; 403 } 404 405 void 406 esp_dma_stop(sc) 407 struct ncr53c9x_softc *sc; 408 { 409 struct esp_softc *esc = (struct esp_softc *)sc; 410 411 dbdma_stop(esc->sc_dmareg); 412 esc->sc_dmaactive = 0; 413 } 414 415 int 416 esp_dma_isactive(sc) 417 struct ncr53c9x_softc *sc; 418 { 419 struct esp_softc *esc = (struct esp_softc *)sc; 420 421 return (esc->sc_dmaactive); 422 } 423 424 425 /* 426 * Pseudo (chained) interrupt from the esp driver to kick the 427 * current running DMA transfer. I am replying on espintr() to 428 * pickup and clean errors for now 429 * 430 * return 1 if it was a DMA continue. 431 */ 432 int 433 espdmaintr(sc) 434 struct esp_softc *sc; 435 { 436 struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc; 437 int trans, resid; 438 u_long csr = sc->sc_dma_direction; 439 440 #if 0 441 if (csr & D_ERR_PEND) { 442 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 443 DMACSR(sc) |= D_INVALIDATE; 444 printf("%s: error: csr=%s\n", nsc->sc_dev.dv_xname, 445 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 446 return -1; 447 } 448 #endif 449 450 /* This is an "assertion" :) */ 451 if (sc->sc_dmaactive == 0) 452 panic("dmaintr: DMA wasn't active"); 453 454 /* dbdma_flush(sc->sc_dmareg); */ 455 456 /* DMA has stopped */ 457 dbdma_stop(sc->sc_dmareg); 458 sc->sc_dmaactive = 0; 459 460 if (sc->sc_dmasize == 0) { 461 /* A "Transfer Pad" operation completed */ 462 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 463 NCR_READ_REG(nsc, NCR_TCL) | 464 (NCR_READ_REG(nsc, NCR_TCM) << 8), 465 NCR_READ_REG(nsc, NCR_TCL), 466 NCR_READ_REG(nsc, NCR_TCM))); 467 return 0; 468 } 469 470 resid = 0; 471 /* 472 * If a transfer onto the SCSI bus gets interrupted by the device 473 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 474 * as residual since the ESP counter registers get decremented as 475 * bytes are clocked into the FIFO. 476 */ 477 if (!(csr & D_WRITE) && 478 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 479 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 480 } 481 482 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 483 /* 484 * `Terminal count' is off, so read the residue 485 * out of the ESP counter registers. 486 */ 487 resid += (NCR_READ_REG(nsc, NCR_TCL) | 488 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 489 ((nsc->sc_cfg2 & NCRCFG2_FE) 490 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 491 : 0)); 492 493 if (resid == 0 && sc->sc_dmasize == 65536 && 494 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 495 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 496 resid = 65536; 497 } 498 499 trans = sc->sc_dmasize - resid; 500 if (trans < 0) { /* transferred < 0 ? */ 501 #if 0 502 /* 503 * This situation can happen in perfectly normal operation 504 * if the ESP is reselected while using DMA to select 505 * another target. As such, don't print the warning. 506 */ 507 printf("%s: xfer (%d) > req (%d)\n", 508 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 509 #endif 510 trans = sc->sc_dmasize; 511 } 512 513 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 514 NCR_READ_REG(nsc, NCR_TCL), 515 NCR_READ_REG(nsc, NCR_TCM), 516 (nsc->sc_cfg2 & NCRCFG2_FE) 517 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 518 trans, resid)); 519 520 #if 0 521 if (csr & D_WRITE) 522 flushcache(*sc->sc_dmaaddr, trans); 523 #endif 524 525 *sc->sc_dmalen -= trans; 526 *sc->sc_dmaaddr += trans; 527 528 #if 0 /* this is not normal operation just yet */ 529 if (*sc->sc_dmalen == 0 || 530 nsc->sc_phase != nsc->sc_prevphase) 531 return 0; 532 533 /* and again */ 534 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 535 return 1; 536 #endif 537 return 0; 538 } 539 540 void 541 esp_shutdownhook(arg) 542 void *arg; 543 { 544 struct ncr53c9x_softc *sc = arg; 545 546 NCRCMD(sc, NCRCMD_RSTSCSI); 547 } 548
Indexes created Thu Oct 02 01:09:59 GMT 2025