esp.c revision 1.9
1 /* $NetBSD: esp.c,v 1.9 1998/11/19 21:46:41 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/errno.h> 84 #include <sys/ioctl.h> 85 #include <sys/device.h> 86 #include <sys/buf.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/queue.h> 90 #include <sys/malloc.h> 91 92 #include <vm/vm_param.h> /* for trunc_page */ 93 94 #include <dev/scsipi/scsi_all.h> 95 #include <dev/scsipi/scsipi_all.h> 96 #include <dev/scsipi/scsiconf.h> 97 #include <dev/scsipi/scsi_message.h> 98 99 #include <dev/ofw/openfirm.h> 100 101 #include <machine/cpu.h> 102 #include <machine/autoconf.h> 103 #include <machine/pio.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <macppc/dev/dbdma.h> 109 #include <macppc/dev/espvar.h> 110 111 void espattach __P((struct device *, struct device *, void *)); 112 int espmatch __P((struct device *, struct cfdata *, void *)); 113 114 /* Linkup to the rest of the kernel */ 115 struct cfattach esp_ca = { 116 sizeof(struct esp_softc), espmatch, espattach 117 }; 118 119 struct scsipi_device esp_dev = { 120 NULL, /* Use default error handler */ 121 NULL, /* have a queue, served by this */ 122 NULL, /* have no async handler */ 123 NULL, /* Use default 'done' routine */ 124 }; 125 126 /* 127 * Functions and the switch for the MI code. 128 */ 129 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 130 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 131 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 132 void esp_dma_reset __P((struct ncr53c9x_softc *)); 133 int esp_dma_intr __P((struct ncr53c9x_softc *)); 134 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 135 size_t *, int, size_t *)); 136 void esp_dma_go __P((struct ncr53c9x_softc *)); 137 void esp_dma_stop __P((struct ncr53c9x_softc *)); 138 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 139 140 struct ncr53c9x_glue esp_glue = { 141 esp_read_reg, 142 esp_write_reg, 143 esp_dma_isintr, 144 esp_dma_reset, 145 esp_dma_intr, 146 esp_dma_setup, 147 esp_dma_go, 148 esp_dma_stop, 149 esp_dma_isactive, 150 NULL, /* gl_clear_latched_intr */ 151 }; 152 153 static int espdmaintr __P((struct esp_softc *)); 154 static void esp_shutdownhook __P((void *)); 155 156 int 157 espmatch(parent, cf, aux) 158 struct device *parent; 159 struct cfdata *cf; 160 void *aux; 161 { 162 struct confargs *ca = aux; 163 164 if (strcmp(ca->ca_name, "53c94") != 0) 165 return 0; 166 167 if (ca->ca_nreg != 16) 168 return 0; 169 if (ca->ca_nintr != 8) 170 return 0; 171 172 return 1; 173 } 174 175 /* 176 * Attach this instance, and then all the sub-devices 177 */ 178 void 179 espattach(parent, self, aux) 180 struct device *parent, *self; 181 void *aux; 182 { 183 register struct confargs *ca = aux; 184 struct esp_softc *esc = (void *)self; 185 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 186 u_int *reg; 187 int sz; 188 189 /* 190 * Set up glue for MI code early; we use some of it here. 191 */ 192 sc->sc_glue = &esp_glue; 193 194 esc->sc_node = ca->ca_node; 195 esc->sc_pri = ca->ca_intr[0]; 196 printf(" irq %d", esc->sc_pri); 197 198 /* 199 * Map my registers in. 200 */ 201 reg = ca->ca_reg; 202 esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1]); 203 esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3]); 204 205 /* Allocate 16-byte aligned dma command space */ 206 esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 207 208 /* Other settings */ 209 sc->sc_id = 7; 210 sz = OF_getprop(ca->ca_node, "clock-frequency", 211 &sc->sc_freq, sizeof(int)); 212 if (sz != sizeof(int)) 213 sc->sc_freq = 25000000; 214 215 /* gimme Mhz */ 216 sc->sc_freq /= 1000000; 217 218 /* esc->sc_dma->sc_esp = esc;*/ 219 220 /* 221 * XXX More of this should be in ncr53c9x_attach(), but 222 * XXX should we really poke around the chip that much in 223 * XXX the MI code? Think about this more... 224 */ 225 226 /* 227 * Set up static configuration info. 228 */ 229 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 230 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 231 sc->sc_cfg3 = NCRCFG3_CDB; 232 sc->sc_rev = NCR_VARIANT_NCR53C94; 233 234 /* 235 * XXX minsync and maxxfer _should_ be set up in MI code, 236 * XXX but it appears to have some dependency on what sort 237 * XXX of DMA we're hooked up to, etc. 238 */ 239 240 /* 241 * This is the value used to start sync negotiations 242 * Note that the NCR register "SYNCTP" is programmed 243 * in "clocks per byte", and has a minimum value of 4. 244 * The SCSI period used in negotiation is one-fourth 245 * of the time (in nanoseconds) needed to transfer one byte. 246 * Since the chip's clock is given in MHz, we have the following 247 * formula: 4 * period = (1000 / freq) * 4 248 */ 249 sc->sc_minsync = 1000 / sc->sc_freq; 250 251 sc->sc_maxxfer = 64 * 1024; 252 253 /* and the interuppts */ 254 intr_establish(esc->sc_pri, IST_LEVEL, IPL_BIO, (void *)ncr53c9x_intr, 255 sc); 256 257 /* Reset SCSI bus when halt. */ 258 shutdownhook_establish(esp_shutdownhook, sc); 259 260 /* Do the common parts of attachment. */ 261 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 262 sc->sc_adapter.scsipi_minphys = minphys; 263 ncr53c9x_attach(sc, &esp_dev); 264 265 /* Turn on target selection using the `dma' method */ 266 ncr53c9x_dmaselect = 1; 267 } 268 269 /* 270 * Glue functions. 271 */ 272 273 u_char 274 esp_read_reg(sc, reg) 275 struct ncr53c9x_softc *sc; 276 int reg; 277 { 278 struct esp_softc *esc = (struct esp_softc *)sc; 279 280 return in8(&esc->sc_reg[reg * 16]); 281 /*return (esc->sc_reg[reg * 16]);*/ 282 } 283 284 void 285 esp_write_reg(sc, reg, val) 286 struct ncr53c9x_softc *sc; 287 int reg; 288 u_char val; 289 { 290 struct esp_softc *esc = (struct esp_softc *)sc; 291 u_char v = val; 292 293 out8(&esc->sc_reg[reg * 16], v); 294 /*esc->sc_reg[reg * 16] = v;*/ 295 } 296 297 int 298 esp_dma_isintr(sc) 299 struct ncr53c9x_softc *sc; 300 { 301 return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 302 } 303 304 void 305 esp_dma_reset(sc) 306 struct ncr53c9x_softc *sc; 307 { 308 struct esp_softc *esc = (struct esp_softc *)sc; 309 310 dbdma_stop(esc->sc_dmareg); 311 esc->sc_dmaactive = 0; 312 } 313 314 int 315 esp_dma_intr(sc) 316 struct ncr53c9x_softc *sc; 317 { 318 struct esp_softc *esc = (struct esp_softc *)sc; 319 320 return (espdmaintr(esc)); 321 } 322 323 int 324 esp_dma_setup(sc, addr, len, datain, dmasize) 325 struct ncr53c9x_softc *sc; 326 caddr_t *addr; 327 size_t *len; 328 int datain; 329 size_t *dmasize; 330 { 331 struct esp_softc *esc = (struct esp_softc *)sc; 332 dbdma_command_t *cmdp; 333 u_int cmd; 334 u_int va; 335 int count, offset; 336 337 cmdp = esc->sc_dmacmd; 338 cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 339 340 count = *dmasize; 341 342 if (count / NBPG > 32) 343 panic("esp: transfer size >= 128k"); 344 345 esc->sc_dmaaddr = addr; 346 esc->sc_dmalen = len; 347 esc->sc_dmasize = count; 348 349 va = (u_int)*esc->sc_dmaaddr; 350 offset = va & PGOFSET; 351 352 /* if va is not page-aligned, setup the first page */ 353 if (offset != 0) { 354 int rest = NBPG - offset; /* the rest of the page */ 355 356 if (count > rest) { /* if continues to next page */ 357 DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((caddr_t)va), 358 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 359 DBDMA_BRANCH_NEVER); 360 count -= rest; 361 va += rest; 362 cmdp++; 363 } 364 } 365 366 /* now va is page-aligned */ 367 while (count > NBPG) { 368 DBDMA_BUILD(cmdp, cmd, 0, NBPG, kvtop((caddr_t)va), 369 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 370 count -= NBPG; 371 va += NBPG; 372 cmdp++; 373 } 374 375 /* the last page (count <= NBPG here) */ 376 cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 377 DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((caddr_t)va), 378 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 379 cmdp++; 380 381 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 382 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 383 384 esc->sc_dma_direction = datain ? D_WRITE : 0; 385 386 return 0; 387 } 388 389 void 390 esp_dma_go(sc) 391 struct ncr53c9x_softc *sc; 392 { 393 struct esp_softc *esc = (struct esp_softc *)sc; 394 395 dbdma_start(esc->sc_dmareg, esc->sc_dmacmd); 396 esc->sc_dmaactive = 1; 397 } 398 399 void 400 esp_dma_stop(sc) 401 struct ncr53c9x_softc *sc; 402 { 403 struct esp_softc *esc = (struct esp_softc *)sc; 404 405 dbdma_stop(esc->sc_dmareg); 406 esc->sc_dmaactive = 0; 407 } 408 409 int 410 esp_dma_isactive(sc) 411 struct ncr53c9x_softc *sc; 412 { 413 struct esp_softc *esc = (struct esp_softc *)sc; 414 415 return (esc->sc_dmaactive); 416 } 417 418 419 /* 420 * Pseudo (chained) interrupt from the esp driver to kick the 421 * current running DMA transfer. I am replying on espintr() to 422 * pickup and clean errors for now 423 * 424 * return 1 if it was a DMA continue. 425 */ 426 int 427 espdmaintr(sc) 428 struct esp_softc *sc; 429 { 430 struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc; 431 int trans, resid; 432 u_long csr = sc->sc_dma_direction; 433 434 #if 0 435 if (csr & D_ERR_PEND) { 436 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 437 DMACSR(sc) |= D_INVALIDATE; 438 printf("%s: error: csr=%s\n", nsc->sc_dev.dv_xname, 439 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 440 return -1; 441 } 442 #endif 443 444 /* This is an "assertion" :) */ 445 if (sc->sc_dmaactive == 0) 446 panic("dmaintr: DMA wasn't active"); 447 448 /* dbdma_flush(sc->sc_dmareg); */ 449 450 /* DMA has stopped */ 451 dbdma_stop(sc->sc_dmareg); 452 sc->sc_dmaactive = 0; 453 454 if (sc->sc_dmasize == 0) { 455 /* A "Transfer Pad" operation completed */ 456 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 457 NCR_READ_REG(nsc, NCR_TCL) | 458 (NCR_READ_REG(nsc, NCR_TCM) << 8), 459 NCR_READ_REG(nsc, NCR_TCL), 460 NCR_READ_REG(nsc, NCR_TCM))); 461 return 0; 462 } 463 464 resid = 0; 465 /* 466 * If a transfer onto the SCSI bus gets interrupted by the device 467 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 468 * as residual since the ESP counter registers get decremented as 469 * bytes are clocked into the FIFO. 470 */ 471 if (!(csr & D_WRITE) && 472 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 473 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 474 } 475 476 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 477 /* 478 * `Terminal count' is off, so read the residue 479 * out of the ESP counter registers. 480 */ 481 resid += (NCR_READ_REG(nsc, NCR_TCL) | 482 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 483 ((nsc->sc_cfg2 & NCRCFG2_FE) 484 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 485 : 0)); 486 487 if (resid == 0 && sc->sc_dmasize == 65536 && 488 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 489 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 490 resid = 65536; 491 } 492 493 trans = sc->sc_dmasize - resid; 494 if (trans < 0) { /* transferred < 0 ? */ 495 #if 0 496 /* 497 * This situation can happen in perfectly normal operation 498 * if the ESP is reselected while using DMA to select 499 * another target. As such, don't print the warning. 500 */ 501 printf("%s: xfer (%d) > req (%d)\n", 502 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 503 #endif 504 trans = sc->sc_dmasize; 505 } 506 507 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 508 NCR_READ_REG(nsc, NCR_TCL), 509 NCR_READ_REG(nsc, NCR_TCM), 510 (nsc->sc_cfg2 & NCRCFG2_FE) 511 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 512 trans, resid)); 513 514 #if 0 515 if (csr & D_WRITE) 516 flushcache(*sc->sc_dmaaddr, trans); 517 #endif 518 519 *sc->sc_dmalen -= trans; 520 *sc->sc_dmaaddr += trans; 521 522 #if 0 /* this is not normal operation just yet */ 523 if (*sc->sc_dmalen == 0 || 524 nsc->sc_phase != nsc->sc_prevphase) 525 return 0; 526 527 /* and again */ 528 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 529 return 1; 530 #endif 531 return 0; 532 } 533 534 void 535 esp_shutdownhook(arg) 536 void *arg; 537 { 538 struct ncr53c9x_softc *sc = arg; 539 540 NCRCMD(sc, NCRCMD_RSTSCSI); 541 } 542
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