if_gm.c revision 1.15.6.2
1 1.15.6.2 nathanw /* $NetBSD: if_gm.c,v 1.15.6.2 2002/02/28 04:10:39 nathanw Exp $ */ 2 1.15.6.2 nathanw 3 1.15.6.2 nathanw /*- 4 1.15.6.2 nathanw * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 1.15.6.2 nathanw * 6 1.15.6.2 nathanw * Redistribution and use in source and binary forms, with or without 7 1.15.6.2 nathanw * modification, are permitted provided that the following conditions 8 1.15.6.2 nathanw * are met: 9 1.15.6.2 nathanw * 1. Redistributions of source code must retain the above copyright 10 1.15.6.2 nathanw * notice, this list of conditions and the following disclaimer. 11 1.15.6.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 12 1.15.6.2 nathanw * notice, this list of conditions and the following disclaimer in the 13 1.15.6.2 nathanw * documentation and/or other materials provided with the distribution. 14 1.15.6.2 nathanw * 3. The name of the author may not be used to endorse or promote products 15 1.15.6.2 nathanw * derived from this software without specific prior written permission. 16 1.15.6.2 nathanw * 17 1.15.6.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.15.6.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 1.15.6.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 1.15.6.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 1.15.6.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 1.15.6.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 1.15.6.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 1.15.6.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 1.15.6.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 1.15.6.2 nathanw * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 1.15.6.2 nathanw */ 28 1.15.6.2 nathanw 29 1.15.6.2 nathanw #include "opt_inet.h" 30 1.15.6.2 nathanw #include "opt_ns.h" 31 1.15.6.2 nathanw #include "rnd.h" 32 1.15.6.2 nathanw #include "bpfilter.h" 33 1.15.6.2 nathanw 34 1.15.6.2 nathanw #include <sys/param.h> 35 1.15.6.2 nathanw #include <sys/device.h> 36 1.15.6.2 nathanw #include <sys/ioctl.h> 37 1.15.6.2 nathanw #include <sys/kernel.h> 38 1.15.6.2 nathanw #include <sys/mbuf.h> 39 1.15.6.2 nathanw #include <sys/socket.h> 40 1.15.6.2 nathanw #include <sys/systm.h> 41 1.15.6.2 nathanw #include <sys/callout.h> 42 1.15.6.2 nathanw 43 1.15.6.2 nathanw #if NRND > 0 44 1.15.6.2 nathanw #include <sys/rnd.h> 45 1.15.6.2 nathanw #endif 46 1.15.6.2 nathanw 47 1.15.6.2 nathanw #include <uvm/uvm_extern.h> 48 1.15.6.2 nathanw 49 1.15.6.2 nathanw #include <net/if.h> 50 1.15.6.2 nathanw #include <net/if_ether.h> 51 1.15.6.2 nathanw #include <net/if_media.h> 52 1.15.6.2 nathanw 53 1.15.6.2 nathanw #if NBPFILTER > 0 54 1.15.6.2 nathanw #include <net/bpf.h> 55 1.15.6.2 nathanw #endif 56 1.15.6.2 nathanw 57 1.15.6.2 nathanw #ifdef INET 58 1.15.6.2 nathanw #include <netinet/in.h> 59 1.15.6.2 nathanw #include <netinet/if_inarp.h> 60 1.15.6.2 nathanw #endif 61 1.15.6.2 nathanw 62 1.15.6.2 nathanw #include <dev/mii/mii.h> 63 1.15.6.2 nathanw #include <dev/mii/miivar.h> 64 1.15.6.2 nathanw 65 1.15.6.2 nathanw #include <dev/pci/pcivar.h> 66 1.15.6.2 nathanw #include <dev/pci/pcireg.h> 67 1.15.6.2 nathanw #include <dev/pci/pcidevs.h> 68 1.15.6.2 nathanw 69 1.15.6.2 nathanw #include <dev/ofw/openfirm.h> 70 1.15.6.2 nathanw #include <macppc/dev/if_gmreg.h> 71 1.15.6.2 nathanw #include <machine/pio.h> 72 1.15.6.2 nathanw 73 1.15.6.2 nathanw #define NTXBUF 4 74 1.15.6.2 nathanw #define NRXBUF 32 75 1.15.6.2 nathanw 76 1.15.6.2 nathanw struct gmac_softc { 77 1.15.6.2 nathanw struct device sc_dev; 78 1.15.6.2 nathanw struct ethercom sc_ethercom; 79 1.15.6.2 nathanw vaddr_t sc_reg; 80 1.15.6.2 nathanw struct gmac_dma *sc_txlist; 81 1.15.6.2 nathanw struct gmac_dma *sc_rxlist; 82 1.15.6.2 nathanw int sc_txnext; 83 1.15.6.2 nathanw int sc_rxlast; 84 1.15.6.2 nathanw caddr_t sc_txbuf[NTXBUF]; 85 1.15.6.2 nathanw caddr_t sc_rxbuf[NRXBUF]; 86 1.15.6.2 nathanw struct mii_data sc_mii; 87 1.15.6.2 nathanw struct callout sc_tick_ch; 88 1.15.6.2 nathanw char sc_laddr[6]; 89 1.15.6.2 nathanw 90 1.15.6.2 nathanw #if NRND > 0 91 1.15.6.2 nathanw rndsource_element_t sc_rnd_source; /* random source */ 92 1.15.6.2 nathanw #endif 93 1.15.6.2 nathanw }; 94 1.15.6.2 nathanw 95 1.15.6.2 nathanw #define sc_if sc_ethercom.ec_if 96 1.15.6.2 nathanw 97 1.15.6.2 nathanw int gmac_match __P((struct device *, struct cfdata *, void *)); 98 1.15.6.2 nathanw void gmac_attach __P((struct device *, struct device *, void *)); 99 1.15.6.2 nathanw 100 1.15.6.2 nathanw static __inline u_int gmac_read_reg __P((struct gmac_softc *, int)); 101 1.15.6.2 nathanw static __inline void gmac_write_reg __P((struct gmac_softc *, int, u_int)); 102 1.15.6.2 nathanw 103 1.15.6.2 nathanw static __inline void gmac_start_txdma __P((struct gmac_softc *)); 104 1.15.6.2 nathanw static __inline void gmac_start_rxdma __P((struct gmac_softc *)); 105 1.15.6.2 nathanw static __inline void gmac_stop_txdma __P((struct gmac_softc *)); 106 1.15.6.2 nathanw static __inline void gmac_stop_rxdma __P((struct gmac_softc *)); 107 1.15.6.2 nathanw 108 1.15.6.2 nathanw int gmac_intr __P((void *)); 109 1.15.6.2 nathanw void gmac_tint __P((struct gmac_softc *)); 110 1.15.6.2 nathanw void gmac_rint __P((struct gmac_softc *)); 111 1.15.6.2 nathanw struct mbuf * gmac_get __P((struct gmac_softc *, caddr_t, int)); 112 1.15.6.2 nathanw void gmac_start __P((struct ifnet *)); 113 1.15.6.2 nathanw int gmac_put __P((struct gmac_softc *, caddr_t, struct mbuf *)); 114 1.15.6.2 nathanw 115 1.15.6.2 nathanw void gmac_stop __P((struct gmac_softc *)); 116 1.15.6.2 nathanw void gmac_reset __P((struct gmac_softc *)); 117 1.15.6.2 nathanw void gmac_init __P((struct gmac_softc *)); 118 1.15.6.2 nathanw void gmac_init_mac __P((struct gmac_softc *)); 119 1.15.6.2 nathanw void gmac_setladrf __P((struct gmac_softc *)); 120 1.15.6.2 nathanw 121 1.15.6.2 nathanw int gmac_ioctl __P((struct ifnet *, u_long, caddr_t)); 122 1.15.6.2 nathanw void gmac_watchdog __P((struct ifnet *)); 123 1.15.6.2 nathanw 124 1.15.6.2 nathanw int gmac_mediachange __P((struct ifnet *)); 125 1.15.6.2 nathanw void gmac_mediastatus __P((struct ifnet *, struct ifmediareq *)); 126 1.15.6.2 nathanw int gmac_mii_readreg __P((struct device *, int, int)); 127 1.15.6.2 nathanw void gmac_mii_writereg __P((struct device *, int, int, int)); 128 1.15.6.2 nathanw void gmac_mii_statchg __P((struct device *)); 129 1.15.6.2 nathanw void gmac_mii_tick __P((void *)); 130 1.15.6.2 nathanw 131 1.15.6.2 nathanw struct cfattach gm_ca = { 132 1.15.6.2 nathanw sizeof(struct gmac_softc), gmac_match, gmac_attach 133 1.15.6.2 nathanw }; 134 1.15.6.2 nathanw 135 1.15.6.2 nathanw int 136 1.15.6.2 nathanw gmac_match(parent, match, aux) 137 1.15.6.2 nathanw struct device *parent; 138 1.15.6.2 nathanw struct cfdata *match; 139 1.15.6.2 nathanw void *aux; 140 1.15.6.2 nathanw { 141 1.15.6.2 nathanw struct pci_attach_args *pa = aux; 142 1.15.6.2 nathanw 143 1.15.6.2 nathanw if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 144 1.15.6.2 nathanw (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 145 1.15.6.2 nathanw PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2)) 146 1.15.6.2 nathanw return 1; 147 1.15.6.2 nathanw 148 1.15.6.2 nathanw return 0; 149 1.15.6.2 nathanw } 150 1.15.6.2 nathanw 151 1.15.6.2 nathanw void 152 1.15.6.2 nathanw gmac_attach(parent, self, aux) 153 1.15.6.2 nathanw struct device *parent, *self; 154 1.15.6.2 nathanw void *aux; 155 1.15.6.2 nathanw { 156 1.15.6.2 nathanw struct gmac_softc *sc = (void *)self; 157 1.15.6.2 nathanw struct pci_attach_args *pa = aux; 158 1.15.6.2 nathanw struct ifnet *ifp = &sc->sc_if; 159 1.15.6.2 nathanw struct mii_data *mii = &sc->sc_mii; 160 1.15.6.2 nathanw pci_intr_handle_t ih; 161 1.15.6.2 nathanw const char *intrstr = NULL; 162 1.15.6.2 nathanw int node, i; 163 1.15.6.2 nathanw char *p; 164 1.15.6.2 nathanw struct gmac_dma *dp; 165 1.15.6.2 nathanw u_int32_t reg[10]; 166 1.15.6.2 nathanw u_char laddr[6]; 167 1.15.6.2 nathanw 168 1.15.6.2 nathanw node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 169 1.15.6.2 nathanw if (node == 0) { 170 1.15.6.2 nathanw printf(": cannot find gmac node\n"); 171 1.15.6.2 nathanw return; 172 1.15.6.2 nathanw } 173 1.15.6.2 nathanw 174 1.15.6.2 nathanw OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 175 1.15.6.2 nathanw OF_getprop(node, "assigned-addresses", reg, sizeof reg); 176 1.15.6.2 nathanw 177 1.15.6.2 nathanw memcpy(sc->sc_laddr, laddr, sizeof laddr); 178 1.15.6.2 nathanw sc->sc_reg = reg[2]; 179 1.15.6.2 nathanw 180 1.15.6.2 nathanw if (pci_intr_map(pa, &ih)) { 181 1.15.6.2 nathanw printf(": unable to map interrupt\n"); 182 1.15.6.2 nathanw return; 183 1.15.6.2 nathanw } 184 1.15.6.2 nathanw intrstr = pci_intr_string(pa->pa_pc, ih); 185 1.15.6.2 nathanw 186 1.15.6.2 nathanw if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 187 1.15.6.2 nathanw printf(": unable to establish interrupt"); 188 1.15.6.2 nathanw if (intrstr) 189 1.15.6.2 nathanw printf(" at %s", intrstr); 190 1.15.6.2 nathanw printf("\n"); 191 1.15.6.2 nathanw return; 192 1.15.6.2 nathanw } 193 1.15.6.2 nathanw 194 1.15.6.2 nathanw /* Setup packet buffers and dma descriptors. */ 195 1.15.6.2 nathanw p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 196 1.15.6.2 nathanw if (p == NULL) { 197 1.15.6.2 nathanw printf(": cannot malloc buffers\n"); 198 1.15.6.2 nathanw return; 199 1.15.6.2 nathanw } 200 1.15.6.2 nathanw p = (void *)roundup((vaddr_t)p, 0x800); 201 1.15.6.2 nathanw memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 202 1.15.6.2 nathanw 203 1.15.6.2 nathanw sc->sc_rxlist = (void *)p; 204 1.15.6.2 nathanw p += 0x800; 205 1.15.6.2 nathanw sc->sc_txlist = (void *)p; 206 1.15.6.2 nathanw p += 0x800; 207 1.15.6.2 nathanw 208 1.15.6.2 nathanw dp = sc->sc_rxlist; 209 1.15.6.2 nathanw for (i = 0; i < NRXBUF; i++) { 210 1.15.6.2 nathanw sc->sc_rxbuf[i] = p; 211 1.15.6.2 nathanw dp->address = htole32(vtophys((vaddr_t)p)); 212 1.15.6.2 nathanw dp->cmd = htole32(GMAC_OWN); 213 1.15.6.2 nathanw dp++; 214 1.15.6.2 nathanw p += 2048; 215 1.15.6.2 nathanw } 216 1.15.6.2 nathanw 217 1.15.6.2 nathanw dp = sc->sc_txlist; 218 1.15.6.2 nathanw for (i = 0; i < NTXBUF; i++) { 219 1.15.6.2 nathanw sc->sc_txbuf[i] = p; 220 1.15.6.2 nathanw dp->address = htole32(vtophys((vaddr_t)p)); 221 1.15.6.2 nathanw dp++; 222 1.15.6.2 nathanw p += 2048; 223 1.15.6.2 nathanw } 224 1.15.6.2 nathanw 225 1.15.6.2 nathanw printf(": Ethernet address %s\n", ether_sprintf(laddr)); 226 1.15.6.2 nathanw printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 227 1.15.6.2 nathanw 228 1.15.6.2 nathanw callout_init(&sc->sc_tick_ch); 229 1.15.6.2 nathanw 230 1.15.6.2 nathanw gmac_reset(sc); 231 1.15.6.2 nathanw gmac_init_mac(sc); 232 1.15.6.2 nathanw 233 1.15.6.2 nathanw memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 234 1.15.6.2 nathanw ifp->if_softc = sc; 235 1.15.6.2 nathanw ifp->if_ioctl = gmac_ioctl; 236 1.15.6.2 nathanw ifp->if_start = gmac_start; 237 1.15.6.2 nathanw ifp->if_watchdog = gmac_watchdog; 238 1.15.6.2 nathanw ifp->if_flags = 239 1.15.6.2 nathanw IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 240 1.15.6.2 nathanw 241 1.15.6.2 nathanw mii->mii_ifp = ifp; 242 1.15.6.2 nathanw mii->mii_readreg = gmac_mii_readreg; 243 1.15.6.2 nathanw mii->mii_writereg = gmac_mii_writereg; 244 1.15.6.2 nathanw mii->mii_statchg = gmac_mii_statchg; 245 1.15.6.2 nathanw 246 1.15.6.2 nathanw ifmedia_init(&mii->mii_media, 0, gmac_mediachange, gmac_mediastatus); 247 1.15.6.2 nathanw mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 248 1.15.6.2 nathanw 249 1.15.6.2 nathanw /* Choose a default media. */ 250 1.15.6.2 nathanw if (LIST_FIRST(&mii->mii_phys) == NULL) { 251 1.15.6.2 nathanw ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 252 1.15.6.2 nathanw ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 253 1.15.6.2 nathanw } else 254 1.15.6.2 nathanw ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 255 1.15.6.2 nathanw 256 1.15.6.2 nathanw if_attach(ifp); 257 1.15.6.2 nathanw ether_ifattach(ifp, laddr); 258 1.15.6.2 nathanw #if NRND > 0 259 1.15.6.2 nathanw rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 260 1.15.6.2 nathanw RND_TYPE_NET, 0); 261 1.15.6.2 nathanw #endif 262 1.15.6.2 nathanw } 263 1.15.6.2 nathanw 264 1.15.6.2 nathanw u_int 265 1.15.6.2 nathanw gmac_read_reg(sc, reg) 266 1.15.6.2 nathanw struct gmac_softc *sc; 267 1.15.6.2 nathanw int reg; 268 1.15.6.2 nathanw { 269 1.15.6.2 nathanw return in32rb(sc->sc_reg + reg); 270 1.15.6.2 nathanw } 271 1.15.6.2 nathanw 272 1.15.6.2 nathanw void 273 1.15.6.2 nathanw gmac_write_reg(sc, reg, val) 274 1.15.6.2 nathanw struct gmac_softc *sc; 275 1.15.6.2 nathanw int reg; 276 1.15.6.2 nathanw u_int val; 277 1.15.6.2 nathanw { 278 1.15.6.2 nathanw out32rb(sc->sc_reg + reg, val); 279 1.15.6.2 nathanw } 280 1.15.6.2 nathanw 281 1.15.6.2 nathanw void 282 1.15.6.2 nathanw gmac_start_txdma(sc) 283 1.15.6.2 nathanw struct gmac_softc *sc; 284 1.15.6.2 nathanw { 285 1.15.6.2 nathanw u_int x; 286 1.15.6.2 nathanw 287 1.15.6.2 nathanw x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 288 1.15.6.2 nathanw x |= 1; 289 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 290 1.15.6.2 nathanw x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 291 1.15.6.2 nathanw x |= 1; 292 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 293 1.15.6.2 nathanw } 294 1.15.6.2 nathanw 295 1.15.6.2 nathanw void 296 1.15.6.2 nathanw gmac_start_rxdma(sc) 297 1.15.6.2 nathanw struct gmac_softc *sc; 298 1.15.6.2 nathanw { 299 1.15.6.2 nathanw u_int x; 300 1.15.6.2 nathanw 301 1.15.6.2 nathanw x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 302 1.15.6.2 nathanw x |= 1; 303 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 304 1.15.6.2 nathanw x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 305 1.15.6.2 nathanw x |= 1; 306 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 307 1.15.6.2 nathanw } 308 1.15.6.2 nathanw 309 1.15.6.2 nathanw void 310 1.15.6.2 nathanw gmac_stop_txdma(sc) 311 1.15.6.2 nathanw struct gmac_softc *sc; 312 1.15.6.2 nathanw { 313 1.15.6.2 nathanw u_int x; 314 1.15.6.2 nathanw 315 1.15.6.2 nathanw x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 316 1.15.6.2 nathanw x &= ~1; 317 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 318 1.15.6.2 nathanw x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 319 1.15.6.2 nathanw x &= ~1; 320 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 321 1.15.6.2 nathanw } 322 1.15.6.2 nathanw 323 1.15.6.2 nathanw void 324 1.15.6.2 nathanw gmac_stop_rxdma(sc) 325 1.15.6.2 nathanw struct gmac_softc *sc; 326 1.15.6.2 nathanw { 327 1.15.6.2 nathanw u_int x; 328 1.15.6.2 nathanw 329 1.15.6.2 nathanw x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 330 1.15.6.2 nathanw x &= ~1; 331 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 332 1.15.6.2 nathanw x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 333 1.15.6.2 nathanw x &= ~1; 334 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 335 1.15.6.2 nathanw } 336 1.15.6.2 nathanw 337 1.15.6.2 nathanw int 338 1.15.6.2 nathanw gmac_intr(v) 339 1.15.6.2 nathanw void *v; 340 1.15.6.2 nathanw { 341 1.15.6.2 nathanw struct gmac_softc *sc = v; 342 1.15.6.2 nathanw u_int status; 343 1.15.6.2 nathanw 344 1.15.6.2 nathanw status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 345 1.15.6.2 nathanw if (status == 0) 346 1.15.6.2 nathanw return 0; 347 1.15.6.2 nathanw 348 1.15.6.2 nathanw if (status & GMAC_INT_RXDONE) 349 1.15.6.2 nathanw gmac_rint(sc); 350 1.15.6.2 nathanw 351 1.15.6.2 nathanw if (status & GMAC_INT_TXEMPTY) 352 1.15.6.2 nathanw gmac_tint(sc); 353 1.15.6.2 nathanw 354 1.15.6.2 nathanw #if NRND > 0 355 1.15.6.2 nathanw rnd_add_uint32(&sc->sc_rnd_source, status); 356 1.15.6.2 nathanw #endif 357 1.15.6.2 nathanw return 1; 358 1.15.6.2 nathanw } 359 1.15.6.2 nathanw 360 1.15.6.2 nathanw void 361 1.15.6.2 nathanw gmac_tint(sc) 362 1.15.6.2 nathanw struct gmac_softc *sc; 363 1.15.6.2 nathanw { 364 1.15.6.2 nathanw struct ifnet *ifp = &sc->sc_if; 365 1.15.6.2 nathanw 366 1.15.6.2 nathanw ifp->if_flags &= ~IFF_OACTIVE; 367 1.15.6.2 nathanw ifp->if_timer = 0; 368 1.15.6.2 nathanw gmac_start(ifp); 369 1.15.6.2 nathanw } 370 1.15.6.2 nathanw 371 1.15.6.2 nathanw void 372 1.15.6.2 nathanw gmac_rint(sc) 373 1.15.6.2 nathanw struct gmac_softc *sc; 374 1.15.6.2 nathanw { 375 1.15.6.2 nathanw struct ifnet *ifp = &sc->sc_if; 376 1.15.6.2 nathanw volatile struct gmac_dma *dp; 377 1.15.6.2 nathanw struct mbuf *m; 378 1.15.6.2 nathanw int i, j, len; 379 1.15.6.2 nathanw u_int cmd; 380 1.15.6.2 nathanw 381 1.15.6.2 nathanw for (i = sc->sc_rxlast;; i++) { 382 1.15.6.2 nathanw if (i == NRXBUF) 383 1.15.6.2 nathanw i = 0; 384 1.15.6.2 nathanw 385 1.15.6.2 nathanw dp = &sc->sc_rxlist[i]; 386 1.15.6.2 nathanw cmd = le32toh(dp->cmd); 387 1.15.6.2 nathanw if (cmd & GMAC_OWN) 388 1.15.6.2 nathanw break; 389 1.15.6.2 nathanw len = (cmd >> 16) & GMAC_LEN_MASK; 390 1.15.6.2 nathanw len -= 4; /* CRC */ 391 1.15.6.2 nathanw 392 1.15.6.2 nathanw if (le32toh(dp->cmd_hi) & 0x40000000) { 393 1.15.6.2 nathanw ifp->if_ierrors++; 394 1.15.6.2 nathanw goto next; 395 1.15.6.2 nathanw } 396 1.15.6.2 nathanw 397 1.15.6.2 nathanw m = gmac_get(sc, sc->sc_rxbuf[i], len); 398 1.15.6.2 nathanw if (m == NULL) { 399 1.15.6.2 nathanw ifp->if_ierrors++; 400 1.15.6.2 nathanw goto next; 401 1.15.6.2 nathanw } 402 1.15.6.2 nathanw 403 1.15.6.2 nathanw #if NBPFILTER > 0 404 1.15.6.2 nathanw /* 405 1.15.6.2 nathanw * Check if there's a BPF listener on this interface. 406 1.15.6.2 nathanw * If so, hand off the raw packet to BPF. 407 1.15.6.2 nathanw */ 408 1.15.6.2 nathanw if (ifp->if_bpf) 409 1.15.6.2 nathanw bpf_mtap(ifp->if_bpf, m); 410 1.15.6.2 nathanw #endif 411 1.15.6.2 nathanw (*ifp->if_input)(ifp, m); 412 1.15.6.2 nathanw ifp->if_ipackets++; 413 1.15.6.2 nathanw 414 1.15.6.2 nathanw next: 415 1.15.6.2 nathanw dp->cmd_hi = 0; 416 1.15.6.2 nathanw __asm __volatile ("sync"); 417 1.15.6.2 nathanw dp->cmd = htole32(GMAC_OWN); 418 1.15.6.2 nathanw } 419 1.15.6.2 nathanw sc->sc_rxlast = i; 420 1.15.6.2 nathanw 421 1.15.6.2 nathanw /* XXX Make sure free buffers have GMAC_OWN. */ 422 1.15.6.2 nathanw i++; 423 1.15.6.2 nathanw for (j = 1; j < NRXBUF; j++) { 424 1.15.6.2 nathanw if (i == NRXBUF) 425 1.15.6.2 nathanw i = 0; 426 1.15.6.2 nathanw dp = &sc->sc_rxlist[i++]; 427 1.15.6.2 nathanw dp->cmd = htole32(GMAC_OWN); 428 1.15.6.2 nathanw } 429 1.15.6.2 nathanw } 430 1.15.6.2 nathanw 431 1.15.6.2 nathanw struct mbuf * 432 1.15.6.2 nathanw gmac_get(sc, pkt, totlen) 433 1.15.6.2 nathanw struct gmac_softc *sc; 434 1.15.6.2 nathanw caddr_t pkt; 435 1.15.6.2 nathanw int totlen; 436 1.15.6.2 nathanw { 437 1.15.6.2 nathanw struct mbuf *m; 438 1.15.6.2 nathanw struct mbuf *top, **mp; 439 1.15.6.2 nathanw int len; 440 1.15.6.2 nathanw 441 1.15.6.2 nathanw MGETHDR(m, M_DONTWAIT, MT_DATA); 442 1.15.6.2 nathanw if (m == 0) 443 1.15.6.2 nathanw return 0; 444 1.15.6.2 nathanw m->m_pkthdr.rcvif = &sc->sc_if; 445 1.15.6.2 nathanw m->m_pkthdr.len = totlen; 446 1.15.6.2 nathanw len = MHLEN; 447 1.15.6.2 nathanw top = 0; 448 1.15.6.2 nathanw mp = ⊤ 449 1.15.6.2 nathanw 450 1.15.6.2 nathanw while (totlen > 0) { 451 1.15.6.2 nathanw if (top) { 452 1.15.6.2 nathanw MGET(m, M_DONTWAIT, MT_DATA); 453 1.15.6.2 nathanw if (m == 0) { 454 1.15.6.2 nathanw m_freem(top); 455 1.15.6.2 nathanw return 0; 456 1.15.6.2 nathanw } 457 1.15.6.2 nathanw len = MLEN; 458 1.15.6.2 nathanw } 459 1.15.6.2 nathanw if (totlen >= MINCLSIZE) { 460 1.15.6.2 nathanw MCLGET(m, M_DONTWAIT); 461 1.15.6.2 nathanw if ((m->m_flags & M_EXT) == 0) { 462 1.15.6.2 nathanw m_free(m); 463 1.15.6.2 nathanw m_freem(top); 464 1.15.6.2 nathanw return 0; 465 1.15.6.2 nathanw } 466 1.15.6.2 nathanw len = MCLBYTES; 467 1.15.6.2 nathanw } 468 1.15.6.2 nathanw m->m_len = len = min(totlen, len); 469 1.15.6.2 nathanw memcpy(mtod(m, caddr_t), pkt, len); 470 1.15.6.2 nathanw pkt += len; 471 1.15.6.2 nathanw totlen -= len; 472 1.15.6.2 nathanw *mp = m; 473 1.15.6.2 nathanw mp = &m->m_next; 474 1.15.6.2 nathanw } 475 1.15.6.2 nathanw 476 1.15.6.2 nathanw return top; 477 1.15.6.2 nathanw } 478 1.15.6.2 nathanw 479 1.15.6.2 nathanw void 480 1.15.6.2 nathanw gmac_start(ifp) 481 1.15.6.2 nathanw struct ifnet *ifp; 482 1.15.6.2 nathanw { 483 1.15.6.2 nathanw struct gmac_softc *sc = ifp->if_softc; 484 1.15.6.2 nathanw struct mbuf *m; 485 1.15.6.2 nathanw caddr_t buff; 486 1.15.6.2 nathanw int i, tlen; 487 1.15.6.2 nathanw volatile struct gmac_dma *dp; 488 1.15.6.2 nathanw 489 1.15.6.2 nathanw if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 490 1.15.6.2 nathanw return; 491 1.15.6.2 nathanw 492 1.15.6.2 nathanw for (;;) { 493 1.15.6.2 nathanw if (ifp->if_flags & IFF_OACTIVE) 494 1.15.6.2 nathanw break; 495 1.15.6.2 nathanw 496 1.15.6.2 nathanw IF_DEQUEUE(&ifp->if_snd, m); 497 1.15.6.2 nathanw if (m == 0) 498 1.15.6.2 nathanw break; 499 1.15.6.2 nathanw 500 1.15.6.2 nathanw /* 5 seconds to watch for failing to transmit */ 501 1.15.6.2 nathanw ifp->if_timer = 5; 502 1.15.6.2 nathanw ifp->if_opackets++; /* # of pkts */ 503 1.15.6.2 nathanw 504 1.15.6.2 nathanw i = sc->sc_txnext; 505 1.15.6.2 nathanw buff = sc->sc_txbuf[i]; 506 1.15.6.2 nathanw tlen = gmac_put(sc, buff, m); 507 1.15.6.2 nathanw 508 1.15.6.2 nathanw dp = &sc->sc_txlist[i]; 509 1.15.6.2 nathanw dp->cmd_hi = 0; 510 1.15.6.2 nathanw dp->address_hi = 0; 511 1.15.6.2 nathanw dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 512 1.15.6.2 nathanw 513 1.15.6.2 nathanw i++; 514 1.15.6.2 nathanw if (i == NTXBUF) 515 1.15.6.2 nathanw i = 0; 516 1.15.6.2 nathanw __asm __volatile ("sync"); 517 1.15.6.2 nathanw 518 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXDMAKICK, i); 519 1.15.6.2 nathanw sc->sc_txnext = i; 520 1.15.6.2 nathanw 521 1.15.6.2 nathanw #if NBPFILTER > 0 522 1.15.6.2 nathanw /* 523 1.15.6.2 nathanw * If BPF is listening on this interface, let it see the 524 1.15.6.2 nathanw * packet before we commit it to the wire. 525 1.15.6.2 nathanw */ 526 1.15.6.2 nathanw if (ifp->if_bpf) 527 1.15.6.2 nathanw bpf_mtap(ifp->if_bpf, m); 528 1.15.6.2 nathanw #endif 529 1.15.6.2 nathanw m_freem(m); 530 1.15.6.2 nathanw 531 1.15.6.2 nathanw i++; 532 1.15.6.2 nathanw if (i == NTXBUF) 533 1.15.6.2 nathanw i = 0; 534 1.15.6.2 nathanw if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 535 1.15.6.2 nathanw ifp->if_flags |= IFF_OACTIVE; 536 1.15.6.2 nathanw break; 537 1.15.6.2 nathanw } 538 1.15.6.2 nathanw } 539 1.15.6.2 nathanw } 540 1.15.6.2 nathanw 541 1.15.6.2 nathanw int 542 1.15.6.2 nathanw gmac_put(sc, buff, m) 543 1.15.6.2 nathanw struct gmac_softc *sc; 544 1.15.6.2 nathanw caddr_t buff; 545 1.15.6.2 nathanw struct mbuf *m; 546 1.15.6.2 nathanw { 547 1.15.6.2 nathanw int len, tlen = 0; 548 1.15.6.2 nathanw 549 1.15.6.2 nathanw for (; m; m = m->m_next) { 550 1.15.6.2 nathanw len = m->m_len; 551 1.15.6.2 nathanw if (len == 0) 552 1.15.6.2 nathanw continue; 553 1.15.6.2 nathanw memcpy(buff, mtod(m, caddr_t), len); 554 1.15.6.2 nathanw buff += len; 555 1.15.6.2 nathanw tlen += len; 556 1.15.6.2 nathanw } 557 1.15.6.2 nathanw if (tlen > 2048) 558 1.15.6.2 nathanw panic("%s: gmac_put packet overflow", sc->sc_dev.dv_xname); 559 1.15.6.2 nathanw 560 1.15.6.2 nathanw return tlen; 561 1.15.6.2 nathanw } 562 1.15.6.2 nathanw 563 1.15.6.2 nathanw void 564 1.15.6.2 nathanw gmac_reset(sc) 565 1.15.6.2 nathanw struct gmac_softc *sc; 566 1.15.6.2 nathanw { 567 1.15.6.2 nathanw int i, s; 568 1.15.6.2 nathanw 569 1.15.6.2 nathanw s = splnet(); 570 1.15.6.2 nathanw 571 1.15.6.2 nathanw gmac_stop_txdma(sc); 572 1.15.6.2 nathanw gmac_stop_rxdma(sc); 573 1.15.6.2 nathanw 574 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 575 1.15.6.2 nathanw for (i = 10; i > 0; i--) { 576 1.15.6.2 nathanw delay(300000); /* XXX long delay */ 577 1.15.6.2 nathanw if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 578 1.15.6.2 nathanw break; 579 1.15.6.2 nathanw } 580 1.15.6.2 nathanw if (i == 0) 581 1.15.6.2 nathanw printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 582 1.15.6.2 nathanw 583 1.15.6.2 nathanw sc->sc_txnext = 0; 584 1.15.6.2 nathanw sc->sc_rxlast = 0; 585 1.15.6.2 nathanw for (i = 0; i < NRXBUF; i++) 586 1.15.6.2 nathanw sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 587 1.15.6.2 nathanw __asm __volatile ("sync"); 588 1.15.6.2 nathanw 589 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 590 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 591 1.15.6.2 nathanw vtophys((vaddr_t)sc->sc_txlist)); 592 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 593 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 594 1.15.6.2 nathanw vtophys((vaddr_t)sc->sc_rxlist)); 595 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 596 1.15.6.2 nathanw 597 1.15.6.2 nathanw splx(s); 598 1.15.6.2 nathanw } 599 1.15.6.2 nathanw 600 1.15.6.2 nathanw void 601 1.15.6.2 nathanw gmac_stop(sc) 602 1.15.6.2 nathanw struct gmac_softc *sc; 603 1.15.6.2 nathanw { 604 1.15.6.2 nathanw struct ifnet *ifp = &sc->sc_if; 605 1.15.6.2 nathanw int s; 606 1.15.6.2 nathanw 607 1.15.6.2 nathanw s = splnet(); 608 1.15.6.2 nathanw 609 1.15.6.2 nathanw callout_stop(&sc->sc_tick_ch); 610 1.15.6.2 nathanw mii_down(&sc->sc_mii); 611 1.15.6.2 nathanw 612 1.15.6.2 nathanw gmac_stop_txdma(sc); 613 1.15.6.2 nathanw gmac_stop_rxdma(sc); 614 1.15.6.2 nathanw 615 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 616 1.15.6.2 nathanw 617 1.15.6.2 nathanw ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 618 1.15.6.2 nathanw ifp->if_timer = 0; 619 1.15.6.2 nathanw 620 1.15.6.2 nathanw splx(s); 621 1.15.6.2 nathanw } 622 1.15.6.2 nathanw 623 1.15.6.2 nathanw void 624 1.15.6.2 nathanw gmac_init_mac(sc) 625 1.15.6.2 nathanw struct gmac_softc *sc; 626 1.15.6.2 nathanw { 627 1.15.6.2 nathanw int i, tb; 628 1.15.6.2 nathanw char *laddr = sc->sc_laddr; 629 1.15.6.2 nathanw 630 1.15.6.2 nathanw __asm ("mftb %0" : "=r"(tb)); 631 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 632 1.15.6.2 nathanw 633 1.15.6.2 nathanw /* init-mii */ 634 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 635 1.15.6.2 nathanw gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 636 1.15.6.2 nathanw 637 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 638 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 639 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 640 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 641 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 642 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 643 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 644 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 645 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_PASIZE, 7); 646 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_JAMSIZE, 4); 647 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10); 648 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 649 1.15.6.2 nathanw 650 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 651 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 652 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 653 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 654 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 655 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 656 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 657 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 658 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 659 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 660 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 661 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 662 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 663 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 664 1.15.6.2 nathanw 665 1.15.6.2 nathanw for (i = 0; i < 0x6c; i += 4) 666 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 667 1.15.6.2 nathanw 668 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 669 1.15.6.2 nathanw 670 1.15.6.2 nathanw if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 671 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 672 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 673 1.15.6.2 nathanw } else { 674 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 675 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 676 1.15.6.2 nathanw } 677 1.15.6.2 nathanw 678 1.15.6.2 nathanw if (0) /* g-bit? */ 679 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 680 1.15.6.2 nathanw else 681 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 682 1.15.6.2 nathanw } 683 1.15.6.2 nathanw 684 1.15.6.2 nathanw void 685 1.15.6.2 nathanw gmac_setladrf(sc) 686 1.15.6.2 nathanw struct gmac_softc *sc; 687 1.15.6.2 nathanw { 688 1.15.6.2 nathanw struct ifnet *ifp = &sc->sc_if; 689 1.15.6.2 nathanw struct ether_multi *enm; 690 1.15.6.2 nathanw struct ether_multistep step; 691 1.15.6.2 nathanw struct ethercom *ec = &sc->sc_ethercom; 692 1.15.6.2 nathanw u_int32_t crc; 693 1.15.6.2 nathanw u_int32_t hash[16]; 694 1.15.6.2 nathanw u_int v; 695 1.15.6.2 nathanw int i; 696 1.15.6.2 nathanw 697 1.15.6.2 nathanw /* Clear hash table */ 698 1.15.6.2 nathanw for (i = 0; i < 16; i++) 699 1.15.6.2 nathanw hash[i] = 0; 700 1.15.6.2 nathanw 701 1.15.6.2 nathanw /* Get current RX configuration */ 702 1.15.6.2 nathanw v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 703 1.15.6.2 nathanw 704 1.15.6.2 nathanw if ((ifp->if_flags & IFF_PROMISC) != 0) { 705 1.15.6.2 nathanw /* Turn on promiscuous mode; turn off the hash filter */ 706 1.15.6.2 nathanw v |= GMAC_RXMAC_PR; 707 1.15.6.2 nathanw v &= ~GMAC_RXMAC_HEN; 708 1.15.6.2 nathanw ifp->if_flags |= IFF_ALLMULTI; 709 1.15.6.2 nathanw goto chipit; 710 1.15.6.2 nathanw } 711 1.15.6.2 nathanw 712 1.15.6.2 nathanw /* Turn off promiscuous mode; turn on the hash filter */ 713 1.15.6.2 nathanw v &= ~GMAC_RXMAC_PR; 714 1.15.6.2 nathanw v |= GMAC_RXMAC_HEN; 715 1.15.6.2 nathanw 716 1.15.6.2 nathanw /* 717 1.15.6.2 nathanw * Set up multicast address filter by passing all multicast addresses 718 1.15.6.2 nathanw * through a crc generator, and then using the high order 8 bits as an 719 1.15.6.2 nathanw * index into the 256 bit logical address filter. The high order bit 720 1.15.6.2 nathanw * selects the word, while the rest of the bits select the bit within 721 1.15.6.2 nathanw * the word. 722 1.15.6.2 nathanw */ 723 1.15.6.2 nathanw 724 1.15.6.2 nathanw ETHER_FIRST_MULTI(step, ec, enm); 725 1.15.6.2 nathanw while (enm != NULL) { 726 1.15.6.2 nathanw if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 727 1.15.6.2 nathanw /* 728 1.15.6.2 nathanw * We must listen to a range of multicast addresses. 729 1.15.6.2 nathanw * For now, just accept all multicasts, rather than 730 1.15.6.2 nathanw * trying to set only those filter bits needed to match 731 1.15.6.2 nathanw * the range. (At this time, the only use of address 732 1.15.6.2 nathanw * ranges is for IP multicast routing, for which the 733 1.15.6.2 nathanw * range is big enough to require all bits set.) 734 1.15.6.2 nathanw */ 735 1.15.6.2 nathanw for (i = 0; i < 16; i++) 736 1.15.6.2 nathanw hash[i] = 0xffff; 737 1.15.6.2 nathanw ifp->if_flags |= IFF_ALLMULTI; 738 1.15.6.2 nathanw goto chipit; 739 1.15.6.2 nathanw } 740 1.15.6.2 nathanw 741 1.15.6.2 nathanw crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 742 1.15.6.2 nathanw 743 1.15.6.2 nathanw /* Just want the 8 most significant bits. */ 744 1.15.6.2 nathanw crc >>= 24; 745 1.15.6.2 nathanw 746 1.15.6.2 nathanw /* Set the corresponding bit in the filter. */ 747 1.15.6.2 nathanw hash[crc >> 4] |= 1 << (crc & 0xf); 748 1.15.6.2 nathanw 749 1.15.6.2 nathanw ETHER_NEXT_MULTI(step, enm); 750 1.15.6.2 nathanw } 751 1.15.6.2 nathanw 752 1.15.6.2 nathanw ifp->if_flags &= ~IFF_ALLMULTI; 753 1.15.6.2 nathanw 754 1.15.6.2 nathanw chipit: 755 1.15.6.2 nathanw /* Now load the hash table into the chip */ 756 1.15.6.2 nathanw for (i = 0; i < 16; i++) 757 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 758 1.15.6.2 nathanw 759 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 760 1.15.6.2 nathanw } 761 1.15.6.2 nathanw 762 1.15.6.2 nathanw void 763 1.15.6.2 nathanw gmac_init(sc) 764 1.15.6.2 nathanw struct gmac_softc *sc; 765 1.15.6.2 nathanw { 766 1.15.6.2 nathanw struct ifnet *ifp = &sc->sc_if; 767 1.15.6.2 nathanw 768 1.15.6.2 nathanw gmac_stop_txdma(sc); 769 1.15.6.2 nathanw gmac_stop_rxdma(sc); 770 1.15.6.2 nathanw 771 1.15.6.2 nathanw gmac_init_mac(sc); 772 1.15.6.2 nathanw gmac_setladrf(sc); 773 1.15.6.2 nathanw 774 1.15.6.2 nathanw gmac_start_txdma(sc); 775 1.15.6.2 nathanw gmac_start_rxdma(sc); 776 1.15.6.2 nathanw 777 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 778 1.15.6.2 nathanw 779 1.15.6.2 nathanw ifp->if_flags |= IFF_RUNNING; 780 1.15.6.2 nathanw ifp->if_flags &= ~IFF_OACTIVE; 781 1.15.6.2 nathanw ifp->if_timer = 0; 782 1.15.6.2 nathanw 783 1.15.6.2 nathanw callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 784 1.15.6.2 nathanw 785 1.15.6.2 nathanw gmac_start(ifp); 786 1.15.6.2 nathanw } 787 1.15.6.2 nathanw 788 1.15.6.2 nathanw int 789 1.15.6.2 nathanw gmac_ioctl(ifp, cmd, data) 790 1.15.6.2 nathanw struct ifnet *ifp; 791 1.15.6.2 nathanw u_long cmd; 792 1.15.6.2 nathanw caddr_t data; 793 1.15.6.2 nathanw { 794 1.15.6.2 nathanw struct gmac_softc *sc = ifp->if_softc; 795 1.15.6.2 nathanw struct ifaddr *ifa = (struct ifaddr *)data; 796 1.15.6.2 nathanw struct ifreq *ifr = (struct ifreq *)data; 797 1.15.6.2 nathanw int s, error = 0; 798 1.15.6.2 nathanw 799 1.15.6.2 nathanw s = splnet(); 800 1.15.6.2 nathanw 801 1.15.6.2 nathanw switch (cmd) { 802 1.15.6.2 nathanw 803 1.15.6.2 nathanw case SIOCSIFADDR: 804 1.15.6.2 nathanw ifp->if_flags |= IFF_UP; 805 1.15.6.2 nathanw 806 1.15.6.2 nathanw switch (ifa->ifa_addr->sa_family) { 807 1.15.6.2 nathanw #ifdef INET 808 1.15.6.2 nathanw case AF_INET: 809 1.15.6.2 nathanw gmac_init(sc); 810 1.15.6.2 nathanw arp_ifinit(ifp, ifa); 811 1.15.6.2 nathanw break; 812 1.15.6.2 nathanw #endif 813 1.15.6.2 nathanw #ifdef NS 814 1.15.6.2 nathanw case AF_NS: 815 1.15.6.2 nathanw { 816 1.15.6.2 nathanw struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 817 1.15.6.2 nathanw 818 1.15.6.2 nathanw if (ns_nullhost(*ina)) 819 1.15.6.2 nathanw ina->x_host = 820 1.15.6.2 nathanw *(union ns_host *)LLADDR(ifp->if_sadl); 821 1.15.6.2 nathanw else { 822 1.15.6.2 nathanw memcpy(LLADDR(ifp->if_sadl), 823 1.15.6.2 nathanw ina->x_host.c_host, 824 1.15.6.2 nathanw sizeof(sc->sc_enaddr)); 825 1.15.6.2 nathanw } 826 1.15.6.2 nathanw /* Set new address. */ 827 1.15.6.2 nathanw gmac_init(sc); 828 1.15.6.2 nathanw break; 829 1.15.6.2 nathanw } 830 1.15.6.2 nathanw #endif 831 1.15.6.2 nathanw default: 832 1.15.6.2 nathanw gmac_init(sc); 833 1.15.6.2 nathanw break; 834 1.15.6.2 nathanw } 835 1.15.6.2 nathanw break; 836 1.15.6.2 nathanw 837 1.15.6.2 nathanw case SIOCSIFFLAGS: 838 1.15.6.2 nathanw if ((ifp->if_flags & IFF_UP) == 0 && 839 1.15.6.2 nathanw (ifp->if_flags & IFF_RUNNING) != 0) { 840 1.15.6.2 nathanw /* 841 1.15.6.2 nathanw * If interface is marked down and it is running, then 842 1.15.6.2 nathanw * stop it. 843 1.15.6.2 nathanw */ 844 1.15.6.2 nathanw gmac_stop(sc); 845 1.15.6.2 nathanw ifp->if_flags &= ~IFF_RUNNING; 846 1.15.6.2 nathanw } else if ((ifp->if_flags & IFF_UP) != 0 && 847 1.15.6.2 nathanw (ifp->if_flags & IFF_RUNNING) == 0) { 848 1.15.6.2 nathanw /* 849 1.15.6.2 nathanw * If interface is marked up and it is stopped, then 850 1.15.6.2 nathanw * start it. 851 1.15.6.2 nathanw */ 852 1.15.6.2 nathanw gmac_init(sc); 853 1.15.6.2 nathanw } else { 854 1.15.6.2 nathanw /* 855 1.15.6.2 nathanw * Reset the interface to pick up changes in any other 856 1.15.6.2 nathanw * flags that affect hardware registers. 857 1.15.6.2 nathanw */ 858 1.15.6.2 nathanw gmac_reset(sc); 859 1.15.6.2 nathanw gmac_init(sc); 860 1.15.6.2 nathanw } 861 1.15.6.2 nathanw #ifdef GMAC_DEBUG 862 1.15.6.2 nathanw if (ifp->if_flags & IFF_DEBUG) 863 1.15.6.2 nathanw sc->sc_flags |= GMAC_DEBUGFLAG; 864 1.15.6.2 nathanw #endif 865 1.15.6.2 nathanw break; 866 1.15.6.2 nathanw 867 1.15.6.2 nathanw case SIOCADDMULTI: 868 1.15.6.2 nathanw case SIOCDELMULTI: 869 1.15.6.2 nathanw error = (cmd == SIOCADDMULTI) ? 870 1.15.6.2 nathanw ether_addmulti(ifr, &sc->sc_ethercom) : 871 1.15.6.2 nathanw ether_delmulti(ifr, &sc->sc_ethercom); 872 1.15.6.2 nathanw 873 1.15.6.2 nathanw if (error == ENETRESET) { 874 1.15.6.2 nathanw /* 875 1.15.6.2 nathanw * Multicast list has changed; set the hardware filter 876 1.15.6.2 nathanw * accordingly. 877 1.15.6.2 nathanw */ 878 1.15.6.2 nathanw gmac_init(sc); 879 1.15.6.2 nathanw /* gmac_setladrf(sc); */ 880 1.15.6.2 nathanw error = 0; 881 1.15.6.2 nathanw } 882 1.15.6.2 nathanw break; 883 1.15.6.2 nathanw 884 1.15.6.2 nathanw case SIOCGIFMEDIA: 885 1.15.6.2 nathanw case SIOCSIFMEDIA: 886 1.15.6.2 nathanw error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 887 1.15.6.2 nathanw break; 888 1.15.6.2 nathanw 889 1.15.6.2 nathanw default: 890 1.15.6.2 nathanw error = EINVAL; 891 1.15.6.2 nathanw } 892 1.15.6.2 nathanw 893 1.15.6.2 nathanw splx(s); 894 1.15.6.2 nathanw return error; 895 1.15.6.2 nathanw } 896 1.15.6.2 nathanw 897 1.15.6.2 nathanw void 898 1.15.6.2 nathanw gmac_watchdog(ifp) 899 1.15.6.2 nathanw struct ifnet *ifp; 900 1.15.6.2 nathanw { 901 1.15.6.2 nathanw struct gmac_softc *sc = ifp->if_softc; 902 1.15.6.2 nathanw 903 1.15.6.2 nathanw printf("%s: device timeout\n", ifp->if_xname); 904 1.15.6.2 nathanw ifp->if_oerrors++; 905 1.15.6.2 nathanw 906 1.15.6.2 nathanw gmac_reset(sc); 907 1.15.6.2 nathanw gmac_init(sc); 908 1.15.6.2 nathanw } 909 1.15.6.2 nathanw 910 1.15.6.2 nathanw int 911 1.15.6.2 nathanw gmac_mediachange(ifp) 912 1.15.6.2 nathanw struct ifnet *ifp; 913 1.15.6.2 nathanw { 914 1.15.6.2 nathanw struct gmac_softc *sc = ifp->if_softc; 915 1.15.6.2 nathanw 916 1.15.6.2 nathanw return mii_mediachg(&sc->sc_mii); 917 1.15.6.2 nathanw } 918 1.15.6.2 nathanw 919 1.15.6.2 nathanw void 920 1.15.6.2 nathanw gmac_mediastatus(ifp, ifmr) 921 1.15.6.2 nathanw struct ifnet *ifp; 922 1.15.6.2 nathanw struct ifmediareq *ifmr; 923 1.15.6.2 nathanw { 924 1.15.6.2 nathanw struct gmac_softc *sc = ifp->if_softc; 925 1.15.6.2 nathanw 926 1.15.6.2 nathanw mii_pollstat(&sc->sc_mii); 927 1.15.6.2 nathanw 928 1.15.6.2 nathanw ifmr->ifm_status = sc->sc_mii.mii_media_status; 929 1.15.6.2 nathanw ifmr->ifm_active = sc->sc_mii.mii_media_active; 930 1.15.6.2 nathanw } 931 1.15.6.2 nathanw 932 1.15.6.2 nathanw int 933 1.15.6.2 nathanw gmac_mii_readreg(dev, phy, reg) 934 1.15.6.2 nathanw struct device *dev; 935 1.15.6.2 nathanw int phy, reg; 936 1.15.6.2 nathanw { 937 1.15.6.2 nathanw struct gmac_softc *sc = (void *)dev; 938 1.15.6.2 nathanw int i; 939 1.15.6.2 nathanw 940 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 941 1.15.6.2 nathanw 0x60020000 | (phy << 23) | (reg << 18)); 942 1.15.6.2 nathanw 943 1.15.6.2 nathanw for (i = 1000; i >= 0; i -= 10) { 944 1.15.6.2 nathanw if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 945 1.15.6.2 nathanw break; 946 1.15.6.2 nathanw delay(10); 947 1.15.6.2 nathanw } 948 1.15.6.2 nathanw if (i < 0) { 949 1.15.6.2 nathanw printf("%s: gmac_mii_readreg: timeout\n", sc->sc_dev.dv_xname); 950 1.15.6.2 nathanw return 0; 951 1.15.6.2 nathanw } 952 1.15.6.2 nathanw 953 1.15.6.2 nathanw return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 954 1.15.6.2 nathanw } 955 1.15.6.2 nathanw 956 1.15.6.2 nathanw void 957 1.15.6.2 nathanw gmac_mii_writereg(dev, phy, reg, val) 958 1.15.6.2 nathanw struct device *dev; 959 1.15.6.2 nathanw int phy, reg, val; 960 1.15.6.2 nathanw { 961 1.15.6.2 nathanw struct gmac_softc *sc = (void *)dev; 962 1.15.6.2 nathanw int i; 963 1.15.6.2 nathanw 964 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 965 1.15.6.2 nathanw 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 966 1.15.6.2 nathanw 967 1.15.6.2 nathanw for (i = 1000; i >= 0; i -= 10) { 968 1.15.6.2 nathanw if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 969 1.15.6.2 nathanw break; 970 1.15.6.2 nathanw delay(10); 971 1.15.6.2 nathanw } 972 1.15.6.2 nathanw if (i < 0) 973 1.15.6.2 nathanw printf("%s: gmac_mii_writereg: timeout\n", sc->sc_dev.dv_xname); 974 1.15.6.2 nathanw } 975 1.15.6.2 nathanw 976 1.15.6.2 nathanw void 977 1.15.6.2 nathanw gmac_mii_statchg(dev) 978 1.15.6.2 nathanw struct device *dev; 979 1.15.6.2 nathanw { 980 1.15.6.2 nathanw struct gmac_softc *sc = (void *)dev; 981 1.15.6.2 nathanw 982 1.15.6.2 nathanw gmac_stop_txdma(sc); 983 1.15.6.2 nathanw gmac_stop_rxdma(sc); 984 1.15.6.2 nathanw 985 1.15.6.2 nathanw if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 986 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 987 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 988 1.15.6.2 nathanw } else { 989 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 990 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 991 1.15.6.2 nathanw } 992 1.15.6.2 nathanw 993 1.15.6.2 nathanw if (0) /* g-bit? */ 994 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 995 1.15.6.2 nathanw else 996 1.15.6.2 nathanw gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 997 1.15.6.2 nathanw 998 1.15.6.2 nathanw gmac_start_txdma(sc); 999 1.15.6.2 nathanw gmac_start_rxdma(sc); 1000 1.15.6.2 nathanw } 1001 1.15.6.2 nathanw 1002 1.15.6.2 nathanw void 1003 1.15.6.2 nathanw gmac_mii_tick(v) 1004 1.15.6.2 nathanw void *v; 1005 1.15.6.2 nathanw { 1006 1.15.6.2 nathanw struct gmac_softc *sc = v; 1007 1.15.6.2 nathanw int s; 1008 1.15.6.2 nathanw 1009 1.15.6.2 nathanw s = splnet(); 1010 1.15.6.2 nathanw mii_tick(&sc->sc_mii); 1011 1.15.6.2 nathanw splx(s); 1012 1.15.6.2 nathanw 1013 1.15.6.2 nathanw callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 1014 1.15.6.2 nathanw } 1015
Indexes created Tue Oct 21 16:10:11 GMT 2025