if_gm.c revision 1.11
1 /* $NetBSD: if_gm.c,v 1.11 2001/04/20 01:18:47 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_inet.h" 30 #include "opt_ns.h" 31 #include "bpfilter.h" 32 33 #include <sys/param.h> 34 #include <sys/device.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/mbuf.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/callout.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <net/if.h> 45 #include <net/if_ether.h> 46 #include <net/if_media.h> 47 48 #if NBPFILTER > 0 49 #include <net/bpf.h> 50 #endif 51 52 #ifdef INET 53 #include <netinet/in.h> 54 #include <netinet/if_inarp.h> 55 #endif 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/ofw/openfirm.h> 65 #include <macppc/dev/if_gmreg.h> 66 #include <machine/pio.h> 67 68 #define NTXBUF 4 69 #define NRXBUF 32 70 71 struct gmac_softc { 72 struct device sc_dev; 73 struct ethercom sc_ethercom; 74 vaddr_t sc_reg; 75 struct gmac_dma *sc_txlist; 76 struct gmac_dma *sc_rxlist; 77 int sc_txnext; 78 int sc_rxlast; 79 caddr_t sc_txbuf[NTXBUF]; 80 caddr_t sc_rxbuf[NRXBUF]; 81 struct mii_data sc_mii; 82 struct callout sc_tick_ch; 83 char sc_laddr[6]; 84 }; 85 86 #define sc_if sc_ethercom.ec_if 87 88 int gmac_match __P((struct device *, struct cfdata *, void *)); 89 void gmac_attach __P((struct device *, struct device *, void *)); 90 91 static __inline u_int gmac_read_reg __P((struct gmac_softc *, int)); 92 static __inline void gmac_write_reg __P((struct gmac_softc *, int, u_int)); 93 94 static __inline void gmac_start_txdma __P((struct gmac_softc *)); 95 static __inline void gmac_start_rxdma __P((struct gmac_softc *)); 96 static __inline void gmac_stop_txdma __P((struct gmac_softc *)); 97 static __inline void gmac_stop_rxdma __P((struct gmac_softc *)); 98 99 int gmac_intr __P((void *)); 100 void gmac_tint __P((struct gmac_softc *)); 101 void gmac_rint __P((struct gmac_softc *)); 102 struct mbuf * gmac_get __P((struct gmac_softc *, caddr_t, int)); 103 void gmac_start __P((struct ifnet *)); 104 int gmac_put __P((struct gmac_softc *, caddr_t, struct mbuf *)); 105 106 void gmac_stop __P((struct gmac_softc *)); 107 void gmac_reset __P((struct gmac_softc *)); 108 void gmac_init __P((struct gmac_softc *)); 109 void gmac_init_mac __P((struct gmac_softc *)); 110 void gmac_setladrf __P((struct gmac_softc *)); 111 112 int gmac_ioctl __P((struct ifnet *, u_long, caddr_t)); 113 void gmac_watchdog __P((struct ifnet *)); 114 115 int gmac_mediachange __P((struct ifnet *)); 116 void gmac_mediastatus __P((struct ifnet *, struct ifmediareq *)); 117 int gmac_mii_readreg __P((struct device *, int, int)); 118 void gmac_mii_writereg __P((struct device *, int, int, int)); 119 void gmac_mii_statchg __P((struct device *)); 120 void gmac_mii_tick __P((void *)); 121 122 struct cfattach gm_ca = { 123 sizeof(struct gmac_softc), gmac_match, gmac_attach 124 }; 125 126 int 127 gmac_match(parent, match, aux) 128 struct device *parent; 129 struct cfdata *match; 130 void *aux; 131 { 132 struct pci_attach_args *pa = aux; 133 134 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 135 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC) 136 return 1; 137 138 return 0; 139 } 140 141 void 142 gmac_attach(parent, self, aux) 143 struct device *parent, *self; 144 void *aux; 145 { 146 struct gmac_softc *sc = (void *)self; 147 struct pci_attach_args *pa = aux; 148 struct ifnet *ifp = &sc->sc_if; 149 struct mii_data *mii = &sc->sc_mii; 150 pci_intr_handle_t ih; 151 const char *intrstr = NULL; 152 int node, i; 153 char *p; 154 struct gmac_dma *dp; 155 u_int32_t reg[10]; 156 u_char laddr[6]; 157 158 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 159 if (node == 0) { 160 printf(": cannot find gmac node\n"); 161 return; 162 } 163 164 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 165 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 166 167 bcopy(laddr, sc->sc_laddr, sizeof laddr); 168 sc->sc_reg = reg[2]; 169 170 if (pci_intr_map(pa, &ih)) { 171 printf(": unable to map interrupt\n"); 172 return; 173 } 174 intrstr = pci_intr_string(pa->pa_pc, ih); 175 176 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 177 printf(": unable to establish interrupt"); 178 if (intrstr) 179 printf(" at %s", intrstr); 180 printf("\n"); 181 return; 182 } 183 184 /* Setup packet buffers and dma descriptors. */ 185 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 186 if (p == NULL) { 187 printf(": cannot malloc buffers\n"); 188 return; 189 } 190 p = (void *)roundup((vaddr_t)p, 0x800); 191 bzero(p, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 192 193 sc->sc_rxlist = (void *)p; 194 p += 0x800; 195 sc->sc_txlist = (void *)p; 196 p += 0x800; 197 198 dp = sc->sc_rxlist; 199 for (i = 0; i < NRXBUF; i++) { 200 sc->sc_rxbuf[i] = p; 201 dp->address = htole32(vtophys((vaddr_t)p)); 202 dp->cmd = htole32(GMAC_OWN); 203 dp++; 204 p += 2048; 205 } 206 207 dp = sc->sc_txlist; 208 for (i = 0; i < NTXBUF; i++) { 209 sc->sc_txbuf[i] = p; 210 dp->address = htole32(vtophys((vaddr_t)p)); 211 dp++; 212 p += 2048; 213 } 214 215 printf(": Ethernet address %s\n", ether_sprintf(laddr)); 216 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 217 218 callout_init(&sc->sc_tick_ch); 219 220 gmac_reset(sc); 221 gmac_init_mac(sc); 222 223 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 224 ifp->if_softc = sc; 225 ifp->if_ioctl = gmac_ioctl; 226 ifp->if_start = gmac_start; 227 ifp->if_watchdog = gmac_watchdog; 228 ifp->if_flags = 229 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 230 231 mii->mii_ifp = ifp; 232 mii->mii_readreg = gmac_mii_readreg; 233 mii->mii_writereg = gmac_mii_writereg; 234 mii->mii_statchg = gmac_mii_statchg; 235 236 ifmedia_init(&mii->mii_media, 0, gmac_mediachange, gmac_mediastatus); 237 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 238 239 /* Choose a default media. */ 240 if (LIST_FIRST(&mii->mii_phys) == NULL) { 241 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 242 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 243 } else 244 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 245 246 if_attach(ifp); 247 ether_ifattach(ifp, laddr); 248 } 249 250 u_int 251 gmac_read_reg(sc, reg) 252 struct gmac_softc *sc; 253 int reg; 254 { 255 return in32rb(sc->sc_reg + reg); 256 } 257 258 void 259 gmac_write_reg(sc, reg, val) 260 struct gmac_softc *sc; 261 int reg; 262 u_int val; 263 { 264 out32rb(sc->sc_reg + reg, val); 265 } 266 267 void 268 gmac_start_txdma(sc) 269 struct gmac_softc *sc; 270 { 271 u_int x; 272 273 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 274 x |= 1; 275 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 276 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 277 x |= 1; 278 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 279 } 280 281 void 282 gmac_start_rxdma(sc) 283 struct gmac_softc *sc; 284 { 285 u_int x; 286 287 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 288 x |= 1; 289 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 290 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 291 x |= 1; 292 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 293 } 294 295 void 296 gmac_stop_txdma(sc) 297 struct gmac_softc *sc; 298 { 299 u_int x; 300 301 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 302 x &= ~1; 303 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 304 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 305 x &= ~1; 306 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 307 } 308 309 void 310 gmac_stop_rxdma(sc) 311 struct gmac_softc *sc; 312 { 313 u_int x; 314 315 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 316 x &= ~1; 317 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 318 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 319 x &= ~1; 320 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 321 } 322 323 int 324 gmac_intr(v) 325 void *v; 326 { 327 struct gmac_softc *sc = v; 328 u_int status; 329 330 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 331 if (status == 0) 332 return 0; 333 334 if (status & GMAC_INT_RXDONE) 335 gmac_rint(sc); 336 337 if (status & GMAC_INT_TXEMPTY) 338 gmac_tint(sc); 339 340 return 1; 341 } 342 343 void 344 gmac_tint(sc) 345 struct gmac_softc *sc; 346 { 347 struct ifnet *ifp = &sc->sc_if; 348 349 ifp->if_flags &= ~IFF_OACTIVE; 350 ifp->if_timer = 0; 351 gmac_start(ifp); 352 } 353 354 void 355 gmac_rint(sc) 356 struct gmac_softc *sc; 357 { 358 struct ifnet *ifp = &sc->sc_if; 359 volatile struct gmac_dma *dp; 360 struct mbuf *m; 361 int i, len; 362 u_int cmd; 363 364 for (i = sc->sc_rxlast;; i++) { 365 if (i == NRXBUF) 366 i = 0; 367 368 dp = &sc->sc_rxlist[i]; 369 cmd = le32toh(dp->cmd); 370 if (cmd & GMAC_OWN) 371 break; 372 len = (cmd >> 16) & GMAC_LEN_MASK; 373 len -= 4; /* CRC */ 374 375 if (le32toh(dp->cmd_hi) & 0x40000000) { 376 ifp->if_ierrors++; 377 goto next; 378 } 379 380 m = gmac_get(sc, sc->sc_rxbuf[i], len); 381 if (m == NULL) { 382 ifp->if_ierrors++; 383 goto next; 384 } 385 386 #if NBPFILTER > 0 387 /* 388 * Check if there's a BPF listener on this interface. 389 * If so, hand off the raw packet to BPF. 390 */ 391 if (ifp->if_bpf) 392 bpf_tap(ifp->if_bpf, sc->sc_rxbuf[i], len); 393 #endif 394 (*ifp->if_input)(ifp, m); 395 ifp->if_ipackets++; 396 397 next: 398 dp->cmd_hi = 0; 399 __asm __volatile ("sync"); 400 dp->cmd = htole32(GMAC_OWN); 401 __asm __volatile ("eieio"); /* force out the OWN bit */ 402 } 403 sc->sc_rxlast = i; 404 } 405 406 struct mbuf * 407 gmac_get(sc, pkt, totlen) 408 struct gmac_softc *sc; 409 caddr_t pkt; 410 int totlen; 411 { 412 struct mbuf *m; 413 struct mbuf *top, **mp; 414 int len; 415 416 MGETHDR(m, M_DONTWAIT, MT_DATA); 417 if (m == 0) 418 return 0; 419 m->m_pkthdr.rcvif = &sc->sc_if; 420 m->m_pkthdr.len = totlen; 421 len = MHLEN; 422 top = 0; 423 mp = ⊤ 424 425 while (totlen > 0) { 426 if (top) { 427 MGET(m, M_DONTWAIT, MT_DATA); 428 if (m == 0) { 429 m_freem(top); 430 return 0; 431 } 432 len = MLEN; 433 } 434 if (totlen >= MINCLSIZE) { 435 MCLGET(m, M_DONTWAIT); 436 if ((m->m_flags & M_EXT) == 0) { 437 m_free(m); 438 m_freem(top); 439 return 0; 440 } 441 len = MCLBYTES; 442 } 443 m->m_len = len = min(totlen, len); 444 bcopy(pkt, mtod(m, caddr_t), len); 445 pkt += len; 446 totlen -= len; 447 *mp = m; 448 mp = &m->m_next; 449 } 450 451 return top; 452 } 453 454 void 455 gmac_start(ifp) 456 struct ifnet *ifp; 457 { 458 struct gmac_softc *sc = ifp->if_softc; 459 struct mbuf *m; 460 caddr_t buff; 461 int i, tlen; 462 volatile struct gmac_dma *dp; 463 464 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 465 return; 466 467 for (;;) { 468 if (ifp->if_flags & IFF_OACTIVE) 469 break; 470 471 IF_DEQUEUE(&ifp->if_snd, m); 472 if (m == 0) 473 break; 474 475 /* 5 seconds to watch for failing to transmit */ 476 ifp->if_timer = 5; 477 ifp->if_opackets++; /* # of pkts */ 478 479 i = sc->sc_txnext; 480 buff = sc->sc_txbuf[i]; 481 tlen = gmac_put(sc, buff, m); 482 483 dp = &sc->sc_txlist[i]; 484 dp->cmd_hi = 0; 485 dp->address_hi = 0; 486 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 487 488 i++; 489 if (i == NTXBUF) 490 i = 0; 491 __asm __volatile ("sync"); 492 493 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 494 sc->sc_txnext = i; 495 496 #if NBPFILTER > 0 497 /* 498 * If BPF is listening on this interface, let it see the 499 * packet before we commit it to the wire. 500 */ 501 if (ifp->if_bpf) 502 bpf_tap(ifp->if_bpf, buff, tlen); 503 #endif 504 505 i++; 506 if (i == NTXBUF) 507 i = 0; 508 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 509 ifp->if_flags |= IFF_OACTIVE; 510 break; 511 } 512 } 513 } 514 515 int 516 gmac_put(sc, buff, m) 517 struct gmac_softc *sc; 518 caddr_t buff; 519 struct mbuf *m; 520 { 521 struct mbuf *n; 522 int len, tlen = 0; 523 524 for (; m; m = n) { 525 len = m->m_len; 526 if (len == 0) { 527 MFREE(m, n); 528 continue; 529 } 530 bcopy(mtod(m, caddr_t), buff, len); 531 buff += len; 532 tlen += len; 533 MFREE(m, n); 534 } 535 if (tlen > 2048) 536 panic("%s: gmac_put packet overflow", sc->sc_dev.dv_xname); 537 538 return tlen; 539 } 540 541 void 542 gmac_reset(sc) 543 struct gmac_softc *sc; 544 { 545 int i, s; 546 547 s = splnet(); 548 549 gmac_stop_txdma(sc); 550 gmac_stop_rxdma(sc); 551 552 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 553 for (i = 10; i > 0; i--) { 554 delay(300000); /* XXX long delay */ 555 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 556 break; 557 } 558 if (i == 0) 559 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 560 561 sc->sc_txnext = 0; 562 sc->sc_rxlast = 0; 563 for (i = 0; i < NRXBUF; i++) 564 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 565 __asm __volatile ("sync"); 566 567 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 568 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 569 vtophys((vaddr_t)sc->sc_txlist)); 570 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 571 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 572 vtophys((vaddr_t)sc->sc_rxlist)); 573 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 574 575 splx(s); 576 } 577 578 void 579 gmac_stop(sc) 580 struct gmac_softc *sc; 581 { 582 struct ifnet *ifp = &sc->sc_if; 583 int s; 584 585 s = splnet(); 586 587 callout_stop(&sc->sc_tick_ch); 588 mii_down(&sc->sc_mii); 589 590 gmac_stop_txdma(sc); 591 gmac_stop_rxdma(sc); 592 593 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 594 595 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 596 ifp->if_timer = 0; 597 598 splx(s); 599 } 600 601 void 602 gmac_init_mac(sc) 603 struct gmac_softc *sc; 604 { 605 int i, tb; 606 char *laddr = sc->sc_laddr; 607 608 __asm ("mftb %0" : "=r"(tb)); 609 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 610 611 /* init-mii */ 612 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 613 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 614 615 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 616 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 617 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 618 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 619 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 620 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 621 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 622 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 623 gmac_write_reg(sc, GMAC_PASIZE, 7); 624 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 625 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10); 626 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 627 628 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 629 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 630 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 631 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 632 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 633 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 634 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 635 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 636 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 637 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 638 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 639 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 640 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 641 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 642 643 for (i = 0; i < 0x6c; i += 4) 644 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 645 646 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 647 648 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 649 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 650 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 651 } else { 652 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 653 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 654 } 655 656 if (0) /* g-bit? */ 657 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 658 else 659 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 660 } 661 662 void 663 gmac_setladrf(sc) 664 struct gmac_softc *sc; 665 { 666 struct ifnet *ifp = &sc->sc_if; 667 struct ether_multi *enm; 668 struct ether_multistep step; 669 struct ethercom *ec = &sc->sc_ethercom; 670 u_int32_t crc; 671 u_int32_t hash[16]; 672 u_int v; 673 int i; 674 675 /* Clear hash table */ 676 for (i = 0; i < 16; i++) 677 hash[i] = 0; 678 679 /* Get current RX configuration */ 680 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 681 682 if ((ifp->if_flags & IFF_PROMISC) != 0) { 683 /* Turn on promiscuous mode; turn off the hash filter */ 684 v |= GMAC_RXMAC_PR; 685 v &= ~GMAC_RXMAC_HEN; 686 ifp->if_flags |= IFF_ALLMULTI; 687 goto chipit; 688 } 689 690 /* Turn off promiscuous mode; turn on the hash filter */ 691 v &= ~GMAC_RXMAC_PR; 692 v |= GMAC_RXMAC_HEN; 693 694 /* 695 * Set up multicast address filter by passing all multicast addresses 696 * through a crc generator, and then using the high order 8 bits as an 697 * index into the 256 bit logical address filter. The high order bit 698 * selects the word, while the rest of the bits select the bit within 699 * the word. 700 */ 701 702 ETHER_FIRST_MULTI(step, ec, enm); 703 while (enm != NULL) { 704 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 705 /* 706 * We must listen to a range of multicast addresses. 707 * For now, just accept all multicasts, rather than 708 * trying to set only those filter bits needed to match 709 * the range. (At this time, the only use of address 710 * ranges is for IP multicast routing, for which the 711 * range is big enough to require all bits set.) 712 */ 713 for (i = 0; i < 16; i++) 714 hash[i] = 0xffff; 715 ifp->if_flags |= IFF_ALLMULTI; 716 goto chipit; 717 } 718 719 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 720 721 /* Just want the 8 most significant bits. */ 722 crc >>= 24; 723 724 /* Set the corresponding bit in the filter. */ 725 hash[crc >> 4] |= 1 << (crc & 0xf); 726 727 ETHER_NEXT_MULTI(step, enm); 728 } 729 730 ifp->if_flags &= ~IFF_ALLMULTI; 731 732 chipit: 733 /* Now load the hash table into the chip */ 734 for (i = 0; i < 16; i++) 735 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 736 737 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 738 } 739 740 void 741 gmac_init(sc) 742 struct gmac_softc *sc; 743 { 744 struct ifnet *ifp = &sc->sc_if; 745 746 gmac_stop_txdma(sc); 747 gmac_stop_rxdma(sc); 748 749 gmac_init_mac(sc); 750 gmac_setladrf(sc); 751 752 gmac_start_txdma(sc); 753 gmac_start_rxdma(sc); 754 755 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 756 757 ifp->if_flags |= IFF_RUNNING; 758 ifp->if_flags &= ~IFF_OACTIVE; 759 ifp->if_timer = 0; 760 761 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 762 763 gmac_start(ifp); 764 } 765 766 int 767 gmac_ioctl(ifp, cmd, data) 768 struct ifnet *ifp; 769 u_long cmd; 770 caddr_t data; 771 { 772 struct gmac_softc *sc = ifp->if_softc; 773 struct ifaddr *ifa = (struct ifaddr *)data; 774 struct ifreq *ifr = (struct ifreq *)data; 775 int s, error = 0; 776 777 s = splnet(); 778 779 switch (cmd) { 780 781 case SIOCSIFADDR: 782 ifp->if_flags |= IFF_UP; 783 784 switch (ifa->ifa_addr->sa_family) { 785 #ifdef INET 786 case AF_INET: 787 gmac_init(sc); 788 arp_ifinit(ifp, ifa); 789 break; 790 #endif 791 #ifdef NS 792 case AF_NS: 793 { 794 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 795 796 if (ns_nullhost(*ina)) 797 ina->x_host = 798 *(union ns_host *)LLADDR(ifp->if_sadl); 799 else { 800 bcopy(ina->x_host.c_host, 801 LLADDR(ifp->if_sadl), 802 sizeof(sc->sc_enaddr)); 803 } 804 /* Set new address. */ 805 gmac_init(sc); 806 break; 807 } 808 #endif 809 default: 810 gmac_init(sc); 811 break; 812 } 813 break; 814 815 case SIOCSIFFLAGS: 816 if ((ifp->if_flags & IFF_UP) == 0 && 817 (ifp->if_flags & IFF_RUNNING) != 0) { 818 /* 819 * If interface is marked down and it is running, then 820 * stop it. 821 */ 822 gmac_stop(sc); 823 ifp->if_flags &= ~IFF_RUNNING; 824 } else if ((ifp->if_flags & IFF_UP) != 0 && 825 (ifp->if_flags & IFF_RUNNING) == 0) { 826 /* 827 * If interface is marked up and it is stopped, then 828 * start it. 829 */ 830 gmac_init(sc); 831 } else { 832 /* 833 * Reset the interface to pick up changes in any other 834 * flags that affect hardware registers. 835 */ 836 gmac_reset(sc); 837 gmac_init(sc); 838 } 839 #ifdef GMAC_DEBUG 840 if (ifp->if_flags & IFF_DEBUG) 841 sc->sc_flags |= GMAC_DEBUGFLAG; 842 #endif 843 break; 844 845 case SIOCADDMULTI: 846 case SIOCDELMULTI: 847 error = (cmd == SIOCADDMULTI) ? 848 ether_addmulti(ifr, &sc->sc_ethercom) : 849 ether_delmulti(ifr, &sc->sc_ethercom); 850 851 if (error == ENETRESET) { 852 /* 853 * Multicast list has changed; set the hardware filter 854 * accordingly. 855 */ 856 gmac_init(sc); 857 /* gmac_setladrf(sc); */ 858 error = 0; 859 } 860 break; 861 862 case SIOCGIFMEDIA: 863 case SIOCSIFMEDIA: 864 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 865 break; 866 867 default: 868 error = EINVAL; 869 } 870 871 splx(s); 872 return error; 873 } 874 875 void 876 gmac_watchdog(ifp) 877 struct ifnet *ifp; 878 { 879 struct gmac_softc *sc = ifp->if_softc; 880 881 printf("%s: device timeout\n", ifp->if_xname); 882 ifp->if_oerrors++; 883 884 gmac_reset(sc); 885 gmac_init(sc); 886 } 887 888 int 889 gmac_mediachange(ifp) 890 struct ifnet *ifp; 891 { 892 struct gmac_softc *sc = ifp->if_softc; 893 894 return mii_mediachg(&sc->sc_mii); 895 } 896 897 void 898 gmac_mediastatus(ifp, ifmr) 899 struct ifnet *ifp; 900 struct ifmediareq *ifmr; 901 { 902 struct gmac_softc *sc = ifp->if_softc; 903 904 mii_pollstat(&sc->sc_mii); 905 906 ifmr->ifm_status = sc->sc_mii.mii_media_status; 907 ifmr->ifm_active = sc->sc_mii.mii_media_active; 908 } 909 910 int 911 gmac_mii_readreg(dev, phy, reg) 912 struct device *dev; 913 int phy, reg; 914 { 915 struct gmac_softc *sc = (void *)dev; 916 int i; 917 918 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 919 0x60020000 | (phy << 23) | (reg << 18)); 920 921 for (i = 1000; i >= 0; i -= 10) { 922 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 923 break; 924 delay(10); 925 } 926 if (i < 0) { 927 printf("%s: gmac_mii_readreg: timeout\n", sc->sc_dev.dv_xname); 928 return 0; 929 } 930 931 return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 932 } 933 934 void 935 gmac_mii_writereg(dev, phy, reg, val) 936 struct device *dev; 937 int phy, reg, val; 938 { 939 struct gmac_softc *sc = (void *)dev; 940 int i; 941 942 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 943 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 944 945 for (i = 1000; i >= 0; i -= 10) { 946 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 947 break; 948 delay(10); 949 } 950 if (i < 0) 951 printf("%s: gmac_mii_writereg: timeout\n", sc->sc_dev.dv_xname); 952 } 953 954 void 955 gmac_mii_statchg(dev) 956 struct device *dev; 957 { 958 struct gmac_softc *sc = (void *)dev; 959 960 gmac_stop_txdma(sc); 961 gmac_stop_rxdma(sc); 962 963 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 964 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 965 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 966 } else { 967 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 968 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 969 } 970 971 if (0) /* g-bit? */ 972 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 973 else 974 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 975 976 gmac_start_txdma(sc); 977 gmac_start_rxdma(sc); 978 } 979 980 void 981 gmac_mii_tick(v) 982 void *v; 983 { 984 struct gmac_softc *sc = v; 985 int s; 986 987 s = splnet(); 988 mii_tick(&sc->sc_mii); 989 splx(s); 990 991 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 992 } 993
Indexes created Wed Oct 01 13:09:50 GMT 2025