if_gm.c revision 1.15 1 /* $NetBSD: if_gm.c,v 1.15 2001/07/26 21:31:45 mjl Exp $ */
2
3 /*-
4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include "opt_inet.h"
30 #include "opt_ns.h"
31 #include "rnd.h"
32 #include "bpfilter.h"
33
34 #include <sys/param.h>
35 #include <sys/device.h>
36 #include <sys/ioctl.h>
37 #include <sys/kernel.h>
38 #include <sys/mbuf.h>
39 #include <sys/socket.h>
40 #include <sys/systm.h>
41 #include <sys/callout.h>
42
43 #if NRND > 0
44 #include <sys/rnd.h>
45 #endif
46
47 #include <uvm/uvm_extern.h>
48
49 #include <net/if.h>
50 #include <net/if_ether.h>
51 #include <net/if_media.h>
52
53 #if NBPFILTER > 0
54 #include <net/bpf.h>
55 #endif
56
57 #ifdef INET
58 #include <netinet/in.h>
59 #include <netinet/if_inarp.h>
60 #endif
61
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
64
65 #include <dev/pci/pcivar.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcidevs.h>
68
69 #include <dev/ofw/openfirm.h>
70 #include <macppc/dev/if_gmreg.h>
71 #include <machine/pio.h>
72
73 #define NTXBUF 4
74 #define NRXBUF 32
75
76 struct gmac_softc {
77 struct device sc_dev;
78 struct ethercom sc_ethercom;
79 vaddr_t sc_reg;
80 struct gmac_dma *sc_txlist;
81 struct gmac_dma *sc_rxlist;
82 int sc_txnext;
83 int sc_rxlast;
84 caddr_t sc_txbuf[NTXBUF];
85 caddr_t sc_rxbuf[NRXBUF];
86 struct mii_data sc_mii;
87 struct callout sc_tick_ch;
88 char sc_laddr[6];
89
90 #if NRND > 0
91 rndsource_element_t sc_rnd_source; /* random source */
92 #endif
93 };
94
95 #define sc_if sc_ethercom.ec_if
96
97 int gmac_match __P((struct device *, struct cfdata *, void *));
98 void gmac_attach __P((struct device *, struct device *, void *));
99
100 static __inline u_int gmac_read_reg __P((struct gmac_softc *, int));
101 static __inline void gmac_write_reg __P((struct gmac_softc *, int, u_int));
102
103 static __inline void gmac_start_txdma __P((struct gmac_softc *));
104 static __inline void gmac_start_rxdma __P((struct gmac_softc *));
105 static __inline void gmac_stop_txdma __P((struct gmac_softc *));
106 static __inline void gmac_stop_rxdma __P((struct gmac_softc *));
107
108 int gmac_intr __P((void *));
109 void gmac_tint __P((struct gmac_softc *));
110 void gmac_rint __P((struct gmac_softc *));
111 struct mbuf * gmac_get __P((struct gmac_softc *, caddr_t, int));
112 void gmac_start __P((struct ifnet *));
113 int gmac_put __P((struct gmac_softc *, caddr_t, struct mbuf *));
114
115 void gmac_stop __P((struct gmac_softc *));
116 void gmac_reset __P((struct gmac_softc *));
117 void gmac_init __P((struct gmac_softc *));
118 void gmac_init_mac __P((struct gmac_softc *));
119 void gmac_setladrf __P((struct gmac_softc *));
120
121 int gmac_ioctl __P((struct ifnet *, u_long, caddr_t));
122 void gmac_watchdog __P((struct ifnet *));
123
124 int gmac_mediachange __P((struct ifnet *));
125 void gmac_mediastatus __P((struct ifnet *, struct ifmediareq *));
126 int gmac_mii_readreg __P((struct device *, int, int));
127 void gmac_mii_writereg __P((struct device *, int, int, int));
128 void gmac_mii_statchg __P((struct device *));
129 void gmac_mii_tick __P((void *));
130
131 struct cfattach gm_ca = {
132 sizeof(struct gmac_softc), gmac_match, gmac_attach
133 };
134
135 int
136 gmac_match(parent, match, aux)
137 struct device *parent;
138 struct cfdata *match;
139 void *aux;
140 {
141 struct pci_attach_args *pa = aux;
142
143 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE &&
144 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC ||
145 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2))
146 return 1;
147
148 return 0;
149 }
150
151 void
152 gmac_attach(parent, self, aux)
153 struct device *parent, *self;
154 void *aux;
155 {
156 struct gmac_softc *sc = (void *)self;
157 struct pci_attach_args *pa = aux;
158 struct ifnet *ifp = &sc->sc_if;
159 struct mii_data *mii = &sc->sc_mii;
160 pci_intr_handle_t ih;
161 const char *intrstr = NULL;
162 int node, i;
163 char *p;
164 struct gmac_dma *dp;
165 u_int32_t reg[10];
166 u_char laddr[6];
167
168 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag);
169 if (node == 0) {
170 printf(": cannot find gmac node\n");
171 return;
172 }
173
174 OF_getprop(node, "local-mac-address", laddr, sizeof laddr);
175 OF_getprop(node, "assigned-addresses", reg, sizeof reg);
176
177 memcpy(sc->sc_laddr, laddr, sizeof laddr);
178 sc->sc_reg = reg[2];
179
180 if (pci_intr_map(pa, &ih)) {
181 printf(": unable to map interrupt\n");
182 return;
183 }
184 intrstr = pci_intr_string(pa->pa_pc, ih);
185
186 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) {
187 printf(": unable to establish interrupt");
188 if (intrstr)
189 printf(" at %s", intrstr);
190 printf("\n");
191 return;
192 }
193
194 /* Setup packet buffers and dma descriptors. */
195 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT);
196 if (p == NULL) {
197 printf(": cannot malloc buffers\n");
198 return;
199 }
200 p = (void *)roundup((vaddr_t)p, 0x800);
201 memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800);
202
203 sc->sc_rxlist = (void *)p;
204 p += 0x800;
205 sc->sc_txlist = (void *)p;
206 p += 0x800;
207
208 dp = sc->sc_rxlist;
209 for (i = 0; i < NRXBUF; i++) {
210 sc->sc_rxbuf[i] = p;
211 dp->address = htole32(vtophys((vaddr_t)p));
212 dp->cmd = htole32(GMAC_OWN);
213 dp++;
214 p += 2048;
215 }
216
217 dp = sc->sc_txlist;
218 for (i = 0; i < NTXBUF; i++) {
219 sc->sc_txbuf[i] = p;
220 dp->address = htole32(vtophys((vaddr_t)p));
221 dp++;
222 p += 2048;
223 }
224
225 printf(": Ethernet address %s\n", ether_sprintf(laddr));
226 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
227
228 callout_init(&sc->sc_tick_ch);
229
230 gmac_reset(sc);
231 gmac_init_mac(sc);
232
233 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
234 ifp->if_softc = sc;
235 ifp->if_ioctl = gmac_ioctl;
236 ifp->if_start = gmac_start;
237 ifp->if_watchdog = gmac_watchdog;
238 ifp->if_flags =
239 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
240
241 mii->mii_ifp = ifp;
242 mii->mii_readreg = gmac_mii_readreg;
243 mii->mii_writereg = gmac_mii_writereg;
244 mii->mii_statchg = gmac_mii_statchg;
245
246 ifmedia_init(&mii->mii_media, 0, gmac_mediachange, gmac_mediastatus);
247 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
248
249 /* Choose a default media. */
250 if (LIST_FIRST(&mii->mii_phys) == NULL) {
251 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
252 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE);
253 } else
254 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO);
255
256 if_attach(ifp);
257 ether_ifattach(ifp, laddr);
258 #if NRND > 0
259 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname,
260 RND_TYPE_NET, 0);
261 #endif
262 }
263
264 u_int
265 gmac_read_reg(sc, reg)
266 struct gmac_softc *sc;
267 int reg;
268 {
269 return in32rb(sc->sc_reg + reg);
270 }
271
272 void
273 gmac_write_reg(sc, reg, val)
274 struct gmac_softc *sc;
275 int reg;
276 u_int val;
277 {
278 out32rb(sc->sc_reg + reg, val);
279 }
280
281 void
282 gmac_start_txdma(sc)
283 struct gmac_softc *sc;
284 {
285 u_int x;
286
287 x = gmac_read_reg(sc, GMAC_TXDMACONFIG);
288 x |= 1;
289 gmac_write_reg(sc, GMAC_TXDMACONFIG, x);
290 x = gmac_read_reg(sc, GMAC_TXMACCONFIG);
291 x |= 1;
292 gmac_write_reg(sc, GMAC_TXMACCONFIG, x);
293 }
294
295 void
296 gmac_start_rxdma(sc)
297 struct gmac_softc *sc;
298 {
299 u_int x;
300
301 x = gmac_read_reg(sc, GMAC_RXDMACONFIG);
302 x |= 1;
303 gmac_write_reg(sc, GMAC_RXDMACONFIG, x);
304 x = gmac_read_reg(sc, GMAC_RXMACCONFIG);
305 x |= 1;
306 gmac_write_reg(sc, GMAC_RXMACCONFIG, x);
307 }
308
309 void
310 gmac_stop_txdma(sc)
311 struct gmac_softc *sc;
312 {
313 u_int x;
314
315 x = gmac_read_reg(sc, GMAC_TXDMACONFIG);
316 x &= ~1;
317 gmac_write_reg(sc, GMAC_TXDMACONFIG, x);
318 x = gmac_read_reg(sc, GMAC_TXMACCONFIG);
319 x &= ~1;
320 gmac_write_reg(sc, GMAC_TXMACCONFIG, x);
321 }
322
323 void
324 gmac_stop_rxdma(sc)
325 struct gmac_softc *sc;
326 {
327 u_int x;
328
329 x = gmac_read_reg(sc, GMAC_RXDMACONFIG);
330 x &= ~1;
331 gmac_write_reg(sc, GMAC_RXDMACONFIG, x);
332 x = gmac_read_reg(sc, GMAC_RXMACCONFIG);
333 x &= ~1;
334 gmac_write_reg(sc, GMAC_RXMACCONFIG, x);
335 }
336
337 int
338 gmac_intr(v)
339 void *v;
340 {
341 struct gmac_softc *sc = v;
342 u_int status;
343
344 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff;
345 if (status == 0)
346 return 0;
347
348 if (status & GMAC_INT_RXDONE)
349 gmac_rint(sc);
350
351 if (status & GMAC_INT_TXEMPTY)
352 gmac_tint(sc);
353
354 #if NRND > 0
355 rnd_add_uint32(&sc->sc_rnd_source, status);
356 #endif
357 return 1;
358 }
359
360 void
361 gmac_tint(sc)
362 struct gmac_softc *sc;
363 {
364 struct ifnet *ifp = &sc->sc_if;
365
366 ifp->if_flags &= ~IFF_OACTIVE;
367 ifp->if_timer = 0;
368 gmac_start(ifp);
369 }
370
371 void
372 gmac_rint(sc)
373 struct gmac_softc *sc;
374 {
375 struct ifnet *ifp = &sc->sc_if;
376 volatile struct gmac_dma *dp;
377 struct mbuf *m;
378 int i, j, len;
379 u_int cmd;
380
381 for (i = sc->sc_rxlast;; i++) {
382 if (i == NRXBUF)
383 i = 0;
384
385 dp = &sc->sc_rxlist[i];
386 cmd = le32toh(dp->cmd);
387 if (cmd & GMAC_OWN)
388 break;
389 len = (cmd >> 16) & GMAC_LEN_MASK;
390 len -= 4; /* CRC */
391
392 if (le32toh(dp->cmd_hi) & 0x40000000) {
393 ifp->if_ierrors++;
394 goto next;
395 }
396
397 m = gmac_get(sc, sc->sc_rxbuf[i], len);
398 if (m == NULL) {
399 ifp->if_ierrors++;
400 goto next;
401 }
402
403 #if NBPFILTER > 0
404 /*
405 * Check if there's a BPF listener on this interface.
406 * If so, hand off the raw packet to BPF.
407 */
408 if (ifp->if_bpf)
409 bpf_tap(ifp->if_bpf, sc->sc_rxbuf[i], len);
410 #endif
411 (*ifp->if_input)(ifp, m);
412 ifp->if_ipackets++;
413
414 next:
415 dp->cmd_hi = 0;
416 __asm __volatile ("sync");
417 dp->cmd = htole32(GMAC_OWN);
418 }
419 sc->sc_rxlast = i;
420
421 /* XXX Make sure free buffers have GMAC_OWN. */
422 i++;
423 for (j = 1; j < NRXBUF; j++) {
424 if (i == NRXBUF)
425 i = 0;
426 dp = &sc->sc_rxlist[i++];
427 dp->cmd = htole32(GMAC_OWN);
428 }
429 }
430
431 struct mbuf *
432 gmac_get(sc, pkt, totlen)
433 struct gmac_softc *sc;
434 caddr_t pkt;
435 int totlen;
436 {
437 struct mbuf *m;
438 struct mbuf *top, **mp;
439 int len;
440
441 MGETHDR(m, M_DONTWAIT, MT_DATA);
442 if (m == 0)
443 return 0;
444 m->m_pkthdr.rcvif = &sc->sc_if;
445 m->m_pkthdr.len = totlen;
446 len = MHLEN;
447 top = 0;
448 mp = ⊤
449
450 while (totlen > 0) {
451 if (top) {
452 MGET(m, M_DONTWAIT, MT_DATA);
453 if (m == 0) {
454 m_freem(top);
455 return 0;
456 }
457 len = MLEN;
458 }
459 if (totlen >= MINCLSIZE) {
460 MCLGET(m, M_DONTWAIT);
461 if ((m->m_flags & M_EXT) == 0) {
462 m_free(m);
463 m_freem(top);
464 return 0;
465 }
466 len = MCLBYTES;
467 }
468 m->m_len = len = min(totlen, len);
469 memcpy(mtod(m, caddr_t), pkt, len);
470 pkt += len;
471 totlen -= len;
472 *mp = m;
473 mp = &m->m_next;
474 }
475
476 return top;
477 }
478
479 void
480 gmac_start(ifp)
481 struct ifnet *ifp;
482 {
483 struct gmac_softc *sc = ifp->if_softc;
484 struct mbuf *m;
485 caddr_t buff;
486 int i, tlen;
487 volatile struct gmac_dma *dp;
488
489 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
490 return;
491
492 for (;;) {
493 if (ifp->if_flags & IFF_OACTIVE)
494 break;
495
496 IF_DEQUEUE(&ifp->if_snd, m);
497 if (m == 0)
498 break;
499
500 /* 5 seconds to watch for failing to transmit */
501 ifp->if_timer = 5;
502 ifp->if_opackets++; /* # of pkts */
503
504 i = sc->sc_txnext;
505 buff = sc->sc_txbuf[i];
506 tlen = gmac_put(sc, buff, m);
507
508 dp = &sc->sc_txlist[i];
509 dp->cmd_hi = 0;
510 dp->address_hi = 0;
511 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP);
512
513 i++;
514 if (i == NTXBUF)
515 i = 0;
516 __asm __volatile ("sync");
517
518 gmac_write_reg(sc, GMAC_TXDMAKICK, i);
519 sc->sc_txnext = i;
520
521 #if NBPFILTER > 0
522 /*
523 * If BPF is listening on this interface, let it see the
524 * packet before we commit it to the wire.
525 */
526 if (ifp->if_bpf)
527 bpf_tap(ifp->if_bpf, buff, tlen);
528 #endif
529
530 i++;
531 if (i == NTXBUF)
532 i = 0;
533 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) {
534 ifp->if_flags |= IFF_OACTIVE;
535 break;
536 }
537 }
538 }
539
540 int
541 gmac_put(sc, buff, m)
542 struct gmac_softc *sc;
543 caddr_t buff;
544 struct mbuf *m;
545 {
546 struct mbuf *n;
547 int len, tlen = 0;
548
549 for (; m; m = n) {
550 len = m->m_len;
551 if (len == 0) {
552 MFREE(m, n);
553 continue;
554 }
555 memcpy(buff, mtod(m, caddr_t), len);
556 buff += len;
557 tlen += len;
558 MFREE(m, n);
559 }
560 if (tlen > 2048)
561 panic("%s: gmac_put packet overflow", sc->sc_dev.dv_xname);
562
563 return tlen;
564 }
565
566 void
567 gmac_reset(sc)
568 struct gmac_softc *sc;
569 {
570 int i, s;
571
572 s = splnet();
573
574 gmac_stop_txdma(sc);
575 gmac_stop_rxdma(sc);
576
577 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3);
578 for (i = 10; i > 0; i--) {
579 delay(300000); /* XXX long delay */
580 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0)
581 break;
582 }
583 if (i == 0)
584 printf("%s: reset timeout\n", sc->sc_dev.dv_xname);
585
586 sc->sc_txnext = 0;
587 sc->sc_rxlast = 0;
588 for (i = 0; i < NRXBUF; i++)
589 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN);
590 __asm __volatile ("sync");
591
592 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0);
593 gmac_write_reg(sc, GMAC_TXDMADESCBASELO,
594 vtophys((vaddr_t)sc->sc_txlist));
595 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0);
596 gmac_write_reg(sc, GMAC_RXDMADESCBASELO,
597 vtophys((vaddr_t)sc->sc_rxlist));
598 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF);
599
600 splx(s);
601 }
602
603 void
604 gmac_stop(sc)
605 struct gmac_softc *sc;
606 {
607 struct ifnet *ifp = &sc->sc_if;
608 int s;
609
610 s = splnet();
611
612 callout_stop(&sc->sc_tick_ch);
613 mii_down(&sc->sc_mii);
614
615 gmac_stop_txdma(sc);
616 gmac_stop_rxdma(sc);
617
618 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff);
619
620 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING);
621 ifp->if_timer = 0;
622
623 splx(s);
624 }
625
626 void
627 gmac_init_mac(sc)
628 struct gmac_softc *sc;
629 {
630 int i, tb;
631 char *laddr = sc->sc_laddr;
632
633 __asm ("mftb %0" : "=r"(tb));
634 gmac_write_reg(sc, GMAC_RANDOMSEED, tb);
635
636 /* init-mii */
637 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4);
638 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000);
639
640 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00);
641 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0);
642 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0);
643 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0);
644 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8);
645 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4);
646 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN);
647 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN);
648 gmac_write_reg(sc, GMAC_PASIZE, 7);
649 gmac_write_reg(sc, GMAC_JAMSIZE, 4);
650 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10);
651 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808);
652
653 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]);
654 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]);
655 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]);
656 gmac_write_reg(sc, GMAC_MACADDRESS3, 0);
657 gmac_write_reg(sc, GMAC_MACADDRESS4, 0);
658 gmac_write_reg(sc, GMAC_MACADDRESS5, 0);
659 gmac_write_reg(sc, GMAC_MACADDRESS6, 1);
660 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200);
661 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180);
662 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0);
663 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0);
664 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0);
665 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0);
666 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0);
667
668 for (i = 0; i < 0x6c; i += 4)
669 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0);
670
671 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40);
672
673 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) {
674 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6);
675 gmac_write_reg(sc, GMAC_XIFCONFIG, 1);
676 } else {
677 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0);
678 gmac_write_reg(sc, GMAC_XIFCONFIG, 5);
679 }
680
681 if (0) /* g-bit? */
682 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3);
683 else
684 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0);
685 }
686
687 void
688 gmac_setladrf(sc)
689 struct gmac_softc *sc;
690 {
691 struct ifnet *ifp = &sc->sc_if;
692 struct ether_multi *enm;
693 struct ether_multistep step;
694 struct ethercom *ec = &sc->sc_ethercom;
695 u_int32_t crc;
696 u_int32_t hash[16];
697 u_int v;
698 int i;
699
700 /* Clear hash table */
701 for (i = 0; i < 16; i++)
702 hash[i] = 0;
703
704 /* Get current RX configuration */
705 v = gmac_read_reg(sc, GMAC_RXMACCONFIG);
706
707 if ((ifp->if_flags & IFF_PROMISC) != 0) {
708 /* Turn on promiscuous mode; turn off the hash filter */
709 v |= GMAC_RXMAC_PR;
710 v &= ~GMAC_RXMAC_HEN;
711 ifp->if_flags |= IFF_ALLMULTI;
712 goto chipit;
713 }
714
715 /* Turn off promiscuous mode; turn on the hash filter */
716 v &= ~GMAC_RXMAC_PR;
717 v |= GMAC_RXMAC_HEN;
718
719 /*
720 * Set up multicast address filter by passing all multicast addresses
721 * through a crc generator, and then using the high order 8 bits as an
722 * index into the 256 bit logical address filter. The high order bit
723 * selects the word, while the rest of the bits select the bit within
724 * the word.
725 */
726
727 ETHER_FIRST_MULTI(step, ec, enm);
728 while (enm != NULL) {
729 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) {
730 /*
731 * We must listen to a range of multicast addresses.
732 * For now, just accept all multicasts, rather than
733 * trying to set only those filter bits needed to match
734 * the range. (At this time, the only use of address
735 * ranges is for IP multicast routing, for which the
736 * range is big enough to require all bits set.)
737 */
738 for (i = 0; i < 16; i++)
739 hash[i] = 0xffff;
740 ifp->if_flags |= IFF_ALLMULTI;
741 goto chipit;
742 }
743
744 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
745
746 /* Just want the 8 most significant bits. */
747 crc >>= 24;
748
749 /* Set the corresponding bit in the filter. */
750 hash[crc >> 4] |= 1 << (crc & 0xf);
751
752 ETHER_NEXT_MULTI(step, enm);
753 }
754
755 ifp->if_flags &= ~IFF_ALLMULTI;
756
757 chipit:
758 /* Now load the hash table into the chip */
759 for (i = 0; i < 16; i++)
760 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]);
761
762 gmac_write_reg(sc, GMAC_RXMACCONFIG, v);
763 }
764
765 void
766 gmac_init(sc)
767 struct gmac_softc *sc;
768 {
769 struct ifnet *ifp = &sc->sc_if;
770
771 gmac_stop_txdma(sc);
772 gmac_stop_rxdma(sc);
773
774 gmac_init_mac(sc);
775 gmac_setladrf(sc);
776
777 gmac_start_txdma(sc);
778 gmac_start_rxdma(sc);
779
780 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE));
781
782 ifp->if_flags |= IFF_RUNNING;
783 ifp->if_flags &= ~IFF_OACTIVE;
784 ifp->if_timer = 0;
785
786 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc);
787
788 gmac_start(ifp);
789 }
790
791 int
792 gmac_ioctl(ifp, cmd, data)
793 struct ifnet *ifp;
794 u_long cmd;
795 caddr_t data;
796 {
797 struct gmac_softc *sc = ifp->if_softc;
798 struct ifaddr *ifa = (struct ifaddr *)data;
799 struct ifreq *ifr = (struct ifreq *)data;
800 int s, error = 0;
801
802 s = splnet();
803
804 switch (cmd) {
805
806 case SIOCSIFADDR:
807 ifp->if_flags |= IFF_UP;
808
809 switch (ifa->ifa_addr->sa_family) {
810 #ifdef INET
811 case AF_INET:
812 gmac_init(sc);
813 arp_ifinit(ifp, ifa);
814 break;
815 #endif
816 #ifdef NS
817 case AF_NS:
818 {
819 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
820
821 if (ns_nullhost(*ina))
822 ina->x_host =
823 *(union ns_host *)LLADDR(ifp->if_sadl);
824 else {
825 memcpy(LLADDR(ifp->if_sadl),
826 ina->x_host.c_host,
827 sizeof(sc->sc_enaddr));
828 }
829 /* Set new address. */
830 gmac_init(sc);
831 break;
832 }
833 #endif
834 default:
835 gmac_init(sc);
836 break;
837 }
838 break;
839
840 case SIOCSIFFLAGS:
841 if ((ifp->if_flags & IFF_UP) == 0 &&
842 (ifp->if_flags & IFF_RUNNING) != 0) {
843 /*
844 * If interface is marked down and it is running, then
845 * stop it.
846 */
847 gmac_stop(sc);
848 ifp->if_flags &= ~IFF_RUNNING;
849 } else if ((ifp->if_flags & IFF_UP) != 0 &&
850 (ifp->if_flags & IFF_RUNNING) == 0) {
851 /*
852 * If interface is marked up and it is stopped, then
853 * start it.
854 */
855 gmac_init(sc);
856 } else {
857 /*
858 * Reset the interface to pick up changes in any other
859 * flags that affect hardware registers.
860 */
861 gmac_reset(sc);
862 gmac_init(sc);
863 }
864 #ifdef GMAC_DEBUG
865 if (ifp->if_flags & IFF_DEBUG)
866 sc->sc_flags |= GMAC_DEBUGFLAG;
867 #endif
868 break;
869
870 case SIOCADDMULTI:
871 case SIOCDELMULTI:
872 error = (cmd == SIOCADDMULTI) ?
873 ether_addmulti(ifr, &sc->sc_ethercom) :
874 ether_delmulti(ifr, &sc->sc_ethercom);
875
876 if (error == ENETRESET) {
877 /*
878 * Multicast list has changed; set the hardware filter
879 * accordingly.
880 */
881 gmac_init(sc);
882 /* gmac_setladrf(sc); */
883 error = 0;
884 }
885 break;
886
887 case SIOCGIFMEDIA:
888 case SIOCSIFMEDIA:
889 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
890 break;
891
892 default:
893 error = EINVAL;
894 }
895
896 splx(s);
897 return error;
898 }
899
900 void
901 gmac_watchdog(ifp)
902 struct ifnet *ifp;
903 {
904 struct gmac_softc *sc = ifp->if_softc;
905
906 printf("%s: device timeout\n", ifp->if_xname);
907 ifp->if_oerrors++;
908
909 gmac_reset(sc);
910 gmac_init(sc);
911 }
912
913 int
914 gmac_mediachange(ifp)
915 struct ifnet *ifp;
916 {
917 struct gmac_softc *sc = ifp->if_softc;
918
919 return mii_mediachg(&sc->sc_mii);
920 }
921
922 void
923 gmac_mediastatus(ifp, ifmr)
924 struct ifnet *ifp;
925 struct ifmediareq *ifmr;
926 {
927 struct gmac_softc *sc = ifp->if_softc;
928
929 mii_pollstat(&sc->sc_mii);
930
931 ifmr->ifm_status = sc->sc_mii.mii_media_status;
932 ifmr->ifm_active = sc->sc_mii.mii_media_active;
933 }
934
935 int
936 gmac_mii_readreg(dev, phy, reg)
937 struct device *dev;
938 int phy, reg;
939 {
940 struct gmac_softc *sc = (void *)dev;
941 int i;
942
943 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT,
944 0x60020000 | (phy << 23) | (reg << 18));
945
946 for (i = 1000; i >= 0; i -= 10) {
947 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000)
948 break;
949 delay(10);
950 }
951 if (i < 0) {
952 printf("%s: gmac_mii_readreg: timeout\n", sc->sc_dev.dv_xname);
953 return 0;
954 }
955
956 return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff;
957 }
958
959 void
960 gmac_mii_writereg(dev, phy, reg, val)
961 struct device *dev;
962 int phy, reg, val;
963 {
964 struct gmac_softc *sc = (void *)dev;
965 int i;
966
967 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT,
968 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff));
969
970 for (i = 1000; i >= 0; i -= 10) {
971 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000)
972 break;
973 delay(10);
974 }
975 if (i < 0)
976 printf("%s: gmac_mii_writereg: timeout\n", sc->sc_dev.dv_xname);
977 }
978
979 void
980 gmac_mii_statchg(dev)
981 struct device *dev;
982 {
983 struct gmac_softc *sc = (void *)dev;
984
985 gmac_stop_txdma(sc);
986 gmac_stop_rxdma(sc);
987
988 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) {
989 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6);
990 gmac_write_reg(sc, GMAC_XIFCONFIG, 1);
991 } else {
992 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0);
993 gmac_write_reg(sc, GMAC_XIFCONFIG, 5);
994 }
995
996 if (0) /* g-bit? */
997 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3);
998 else
999 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0);
1000
1001 gmac_start_txdma(sc);
1002 gmac_start_rxdma(sc);
1003 }
1004
1005 void
1006 gmac_mii_tick(v)
1007 void *v;
1008 {
1009 struct gmac_softc *sc = v;
1010 int s;
1011
1012 s = splnet();
1013 mii_tick(&sc->sc_mii);
1014 splx(s);
1015
1016 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc);
1017 }
1018