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if_gm.c revision 1.17
      1 /*	$NetBSD: if_gm.c,v 1.17 2002/03/05 04:12:57 itojun Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_inet.h"
     30 #include "opt_ns.h"
     31 #include "rnd.h"
     32 #include "bpfilter.h"
     33 
     34 #include <sys/param.h>
     35 #include <sys/device.h>
     36 #include <sys/ioctl.h>
     37 #include <sys/kernel.h>
     38 #include <sys/mbuf.h>
     39 #include <sys/socket.h>
     40 #include <sys/systm.h>
     41 #include <sys/callout.h>
     42 
     43 #if NRND > 0
     44 #include <sys/rnd.h>
     45 #endif
     46 
     47 #include <uvm/uvm_extern.h>
     48 
     49 #include <net/if.h>
     50 #include <net/if_ether.h>
     51 #include <net/if_media.h>
     52 
     53 #if NBPFILTER > 0
     54 #include <net/bpf.h>
     55 #endif
     56 
     57 #ifdef INET
     58 #include <netinet/in.h>
     59 #include <netinet/if_inarp.h>
     60 #endif
     61 
     62 #include <dev/mii/mii.h>
     63 #include <dev/mii/miivar.h>
     64 
     65 #include <dev/pci/pcivar.h>
     66 #include <dev/pci/pcireg.h>
     67 #include <dev/pci/pcidevs.h>
     68 
     69 #include <dev/ofw/openfirm.h>
     70 #include <macppc/dev/if_gmreg.h>
     71 #include <machine/pio.h>
     72 
     73 #define NTXBUF 4
     74 #define NRXBUF 32
     75 
     76 struct gmac_softc {
     77 	struct device sc_dev;
     78 	struct ethercom sc_ethercom;
     79 	vaddr_t sc_reg;
     80 	struct gmac_dma *sc_txlist;
     81 	struct gmac_dma *sc_rxlist;
     82 	int sc_txnext;
     83 	int sc_rxlast;
     84 	caddr_t sc_txbuf[NTXBUF];
     85 	caddr_t sc_rxbuf[NRXBUF];
     86 	struct mii_data sc_mii;
     87 	struct callout sc_tick_ch;
     88 	char sc_laddr[6];
     89 
     90 #if NRND > 0
     91 	rndsource_element_t sc_rnd_source; /* random source */
     92 #endif
     93 };
     94 
     95 #define sc_if sc_ethercom.ec_if
     96 
     97 int gmac_match __P((struct device *, struct cfdata *, void *));
     98 void gmac_attach __P((struct device *, struct device *, void *));
     99 
    100 static __inline u_int gmac_read_reg __P((struct gmac_softc *, int));
    101 static __inline void gmac_write_reg __P((struct gmac_softc *, int, u_int));
    102 
    103 static __inline void gmac_start_txdma __P((struct gmac_softc *));
    104 static __inline void gmac_start_rxdma __P((struct gmac_softc *));
    105 static __inline void gmac_stop_txdma __P((struct gmac_softc *));
    106 static __inline void gmac_stop_rxdma __P((struct gmac_softc *));
    107 
    108 int gmac_intr __P((void *));
    109 void gmac_tint __P((struct gmac_softc *));
    110 void gmac_rint __P((struct gmac_softc *));
    111 struct mbuf * gmac_get __P((struct gmac_softc *, caddr_t, int));
    112 void gmac_start __P((struct ifnet *));
    113 int gmac_put __P((struct gmac_softc *, caddr_t, struct mbuf *));
    114 
    115 void gmac_stop __P((struct gmac_softc *));
    116 void gmac_reset __P((struct gmac_softc *));
    117 void gmac_init __P((struct gmac_softc *));
    118 void gmac_init_mac __P((struct gmac_softc *));
    119 void gmac_setladrf __P((struct gmac_softc *));
    120 
    121 int gmac_ioctl __P((struct ifnet *, u_long, caddr_t));
    122 void gmac_watchdog __P((struct ifnet *));
    123 
    124 int gmac_mediachange __P((struct ifnet *));
    125 void gmac_mediastatus __P((struct ifnet *, struct ifmediareq *));
    126 int gmac_mii_readreg __P((struct device *, int, int));
    127 void gmac_mii_writereg __P((struct device *, int, int, int));
    128 void gmac_mii_statchg __P((struct device *));
    129 void gmac_mii_tick __P((void *));
    130 
    131 struct cfattach gm_ca = {
    132 	sizeof(struct gmac_softc), gmac_match, gmac_attach
    133 };
    134 
    135 int
    136 gmac_match(parent, match, aux)
    137 	struct device *parent;
    138 	struct cfdata *match;
    139 	void *aux;
    140 {
    141 	struct pci_attach_args *pa = aux;
    142 
    143 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE &&
    144 	    (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC ||
    145 	     PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2))
    146 		return 1;
    147 
    148 	return 0;
    149 }
    150 
    151 void
    152 gmac_attach(parent, self, aux)
    153 	struct device *parent, *self;
    154 	void *aux;
    155 {
    156 	struct gmac_softc *sc = (void *)self;
    157 	struct pci_attach_args *pa = aux;
    158 	struct ifnet *ifp = &sc->sc_if;
    159 	struct mii_data *mii = &sc->sc_mii;
    160 	pci_intr_handle_t ih;
    161 	const char *intrstr = NULL;
    162 	int node, i;
    163 	char *p;
    164 	struct gmac_dma *dp;
    165 	u_int32_t reg[10];
    166 	u_char laddr[6];
    167 
    168 	node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag);
    169 	if (node == 0) {
    170 		printf(": cannot find gmac node\n");
    171 		return;
    172 	}
    173 
    174 	OF_getprop(node, "local-mac-address", laddr, sizeof laddr);
    175 	OF_getprop(node, "assigned-addresses", reg, sizeof reg);
    176 
    177 	memcpy(sc->sc_laddr, laddr, sizeof laddr);
    178 	sc->sc_reg = reg[2];
    179 
    180 	if (pci_intr_map(pa, &ih)) {
    181 		printf(": unable to map interrupt\n");
    182 		return;
    183 	}
    184 	intrstr = pci_intr_string(pa->pa_pc, ih);
    185 
    186 	if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) {
    187 		printf(": unable to establish interrupt");
    188 		if (intrstr)
    189 			printf(" at %s", intrstr);
    190 		printf("\n");
    191 		return;
    192 	}
    193 
    194 	/* Setup packet buffers and dma descriptors. */
    195 	p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT);
    196 	if (p == NULL) {
    197 		printf(": cannot malloc buffers\n");
    198 		return;
    199 	}
    200 	p = (void *)roundup((vaddr_t)p, 0x800);
    201 	memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800);
    202 
    203 	sc->sc_rxlist = (void *)p;
    204 	p += 0x800;
    205 	sc->sc_txlist = (void *)p;
    206 	p += 0x800;
    207 
    208 	dp = sc->sc_rxlist;
    209 	for (i = 0; i < NRXBUF; i++) {
    210 		sc->sc_rxbuf[i] = p;
    211 		dp->address = htole32(vtophys((vaddr_t)p));
    212 		dp->cmd = htole32(GMAC_OWN);
    213 		dp++;
    214 		p += 2048;
    215 	}
    216 
    217 	dp = sc->sc_txlist;
    218 	for (i = 0; i < NTXBUF; i++) {
    219 		sc->sc_txbuf[i] = p;
    220 		dp->address = htole32(vtophys((vaddr_t)p));
    221 		dp++;
    222 		p += 2048;
    223 	}
    224 
    225 	printf(": Ethernet address %s\n", ether_sprintf(laddr));
    226 	printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
    227 
    228 	callout_init(&sc->sc_tick_ch);
    229 
    230 	gmac_reset(sc);
    231 	gmac_init_mac(sc);
    232 
    233 	memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
    234 	ifp->if_softc = sc;
    235 	ifp->if_ioctl = gmac_ioctl;
    236 	ifp->if_start = gmac_start;
    237 	ifp->if_watchdog = gmac_watchdog;
    238 	ifp->if_flags =
    239 		IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
    240 	IFQ_SET_READY(&ifp->if_snd);
    241 
    242 	mii->mii_ifp = ifp;
    243 	mii->mii_readreg = gmac_mii_readreg;
    244 	mii->mii_writereg = gmac_mii_writereg;
    245 	mii->mii_statchg = gmac_mii_statchg;
    246 
    247 	ifmedia_init(&mii->mii_media, 0, gmac_mediachange, gmac_mediastatus);
    248 	mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
    249 
    250 	/* Choose a default media. */
    251 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
    252 		ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
    253 		ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE);
    254 	} else
    255 		ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO);
    256 
    257 	if_attach(ifp);
    258 	ether_ifattach(ifp, laddr);
    259 #if NRND > 0
    260 	rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname,
    261 	    RND_TYPE_NET, 0);
    262 #endif
    263 }
    264 
    265 u_int
    266 gmac_read_reg(sc, reg)
    267 	struct gmac_softc *sc;
    268 	int reg;
    269 {
    270 	return in32rb(sc->sc_reg + reg);
    271 }
    272 
    273 void
    274 gmac_write_reg(sc, reg, val)
    275 	struct gmac_softc *sc;
    276 	int reg;
    277 	u_int val;
    278 {
    279 	out32rb(sc->sc_reg + reg, val);
    280 }
    281 
    282 void
    283 gmac_start_txdma(sc)
    284 	struct gmac_softc *sc;
    285 {
    286 	u_int x;
    287 
    288 	x = gmac_read_reg(sc, GMAC_TXDMACONFIG);
    289 	x |= 1;
    290 	gmac_write_reg(sc, GMAC_TXDMACONFIG, x);
    291 	x = gmac_read_reg(sc, GMAC_TXMACCONFIG);
    292 	x |= 1;
    293 	gmac_write_reg(sc, GMAC_TXMACCONFIG, x);
    294 }
    295 
    296 void
    297 gmac_start_rxdma(sc)
    298 	struct gmac_softc *sc;
    299 {
    300 	u_int x;
    301 
    302 	x = gmac_read_reg(sc, GMAC_RXDMACONFIG);
    303 	x |= 1;
    304 	gmac_write_reg(sc, GMAC_RXDMACONFIG, x);
    305 	x = gmac_read_reg(sc, GMAC_RXMACCONFIG);
    306 	x |= 1;
    307 	gmac_write_reg(sc, GMAC_RXMACCONFIG, x);
    308 }
    309 
    310 void
    311 gmac_stop_txdma(sc)
    312 	struct gmac_softc *sc;
    313 {
    314 	u_int x;
    315 
    316 	x = gmac_read_reg(sc, GMAC_TXDMACONFIG);
    317 	x &= ~1;
    318 	gmac_write_reg(sc, GMAC_TXDMACONFIG, x);
    319 	x = gmac_read_reg(sc, GMAC_TXMACCONFIG);
    320 	x &= ~1;
    321 	gmac_write_reg(sc, GMAC_TXMACCONFIG, x);
    322 }
    323 
    324 void
    325 gmac_stop_rxdma(sc)
    326 	struct gmac_softc *sc;
    327 {
    328 	u_int x;
    329 
    330 	x = gmac_read_reg(sc, GMAC_RXDMACONFIG);
    331 	x &= ~1;
    332 	gmac_write_reg(sc, GMAC_RXDMACONFIG, x);
    333 	x = gmac_read_reg(sc, GMAC_RXMACCONFIG);
    334 	x &= ~1;
    335 	gmac_write_reg(sc, GMAC_RXMACCONFIG, x);
    336 }
    337 
    338 int
    339 gmac_intr(v)
    340 	void *v;
    341 {
    342 	struct gmac_softc *sc = v;
    343 	u_int status;
    344 
    345 	status = gmac_read_reg(sc, GMAC_STATUS) & 0xff;
    346 	if (status == 0)
    347 		return 0;
    348 
    349 	if (status & GMAC_INT_RXDONE)
    350 		gmac_rint(sc);
    351 
    352 	if (status & GMAC_INT_TXEMPTY)
    353 		gmac_tint(sc);
    354 
    355 #if NRND > 0
    356 	rnd_add_uint32(&sc->sc_rnd_source, status);
    357 #endif
    358 	return 1;
    359 }
    360 
    361 void
    362 gmac_tint(sc)
    363 	struct gmac_softc *sc;
    364 {
    365 	struct ifnet *ifp = &sc->sc_if;
    366 
    367 	ifp->if_flags &= ~IFF_OACTIVE;
    368 	ifp->if_timer = 0;
    369 	gmac_start(ifp);
    370 }
    371 
    372 void
    373 gmac_rint(sc)
    374 	struct gmac_softc *sc;
    375 {
    376 	struct ifnet *ifp = &sc->sc_if;
    377 	volatile struct gmac_dma *dp;
    378 	struct mbuf *m;
    379 	int i, j, len;
    380 	u_int cmd;
    381 
    382 	for (i = sc->sc_rxlast;; i++) {
    383 		if (i == NRXBUF)
    384 			i = 0;
    385 
    386 		dp = &sc->sc_rxlist[i];
    387 		cmd = le32toh(dp->cmd);
    388 		if (cmd & GMAC_OWN)
    389 			break;
    390 		len = (cmd >> 16) & GMAC_LEN_MASK;
    391 		len -= 4;	/* CRC */
    392 
    393 		if (le32toh(dp->cmd_hi) & 0x40000000) {
    394 			ifp->if_ierrors++;
    395 			goto next;
    396 		}
    397 
    398 		m = gmac_get(sc, sc->sc_rxbuf[i], len);
    399 		if (m == NULL) {
    400 			ifp->if_ierrors++;
    401 			goto next;
    402 		}
    403 
    404 #if NBPFILTER > 0
    405 		/*
    406 		 * Check if there's a BPF listener on this interface.
    407 		 * If so, hand off the raw packet to BPF.
    408 		 */
    409 		if (ifp->if_bpf)
    410 			bpf_mtap(ifp->if_bpf, m);
    411 #endif
    412 		(*ifp->if_input)(ifp, m);
    413 		ifp->if_ipackets++;
    414 
    415 next:
    416 		dp->cmd_hi = 0;
    417 		__asm __volatile ("sync");
    418 		dp->cmd = htole32(GMAC_OWN);
    419 	}
    420 	sc->sc_rxlast = i;
    421 
    422 	/* XXX Make sure free buffers have GMAC_OWN. */
    423 	i++;
    424 	for (j = 1; j < NRXBUF; j++) {
    425 		if (i == NRXBUF)
    426 			i = 0;
    427 		dp = &sc->sc_rxlist[i++];
    428 		dp->cmd = htole32(GMAC_OWN);
    429 	}
    430 }
    431 
    432 struct mbuf *
    433 gmac_get(sc, pkt, totlen)
    434 	struct gmac_softc *sc;
    435 	caddr_t pkt;
    436 	int totlen;
    437 {
    438 	struct mbuf *m;
    439 	struct mbuf *top, **mp;
    440 	int len;
    441 
    442 	MGETHDR(m, M_DONTWAIT, MT_DATA);
    443 	if (m == 0)
    444 		return 0;
    445 	m->m_pkthdr.rcvif = &sc->sc_if;
    446 	m->m_pkthdr.len = totlen;
    447 	len = MHLEN;
    448 	top = 0;
    449 	mp = &top;
    450 
    451 	while (totlen > 0) {
    452 		if (top) {
    453 			MGET(m, M_DONTWAIT, MT_DATA);
    454 			if (m == 0) {
    455 				m_freem(top);
    456 				return 0;
    457 			}
    458 			len = MLEN;
    459 		}
    460 		if (totlen >= MINCLSIZE) {
    461 			MCLGET(m, M_DONTWAIT);
    462 			if ((m->m_flags & M_EXT) == 0) {
    463 				m_free(m);
    464 				m_freem(top);
    465 				return 0;
    466 			}
    467 			len = MCLBYTES;
    468 		}
    469 		m->m_len = len = min(totlen, len);
    470 		memcpy(mtod(m, caddr_t), pkt, len);
    471 		pkt += len;
    472 		totlen -= len;
    473 		*mp = m;
    474 		mp = &m->m_next;
    475 	}
    476 
    477 	return top;
    478 }
    479 
    480 void
    481 gmac_start(ifp)
    482 	struct ifnet *ifp;
    483 {
    484 	struct gmac_softc *sc = ifp->if_softc;
    485 	struct mbuf *m;
    486 	caddr_t buff;
    487 	int i, tlen;
    488 	volatile struct gmac_dma *dp;
    489 
    490 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
    491 		return;
    492 
    493 	for (;;) {
    494 		if (ifp->if_flags & IFF_OACTIVE)
    495 			break;
    496 
    497 		IFQ_DEQUEUE(&ifp->if_snd, m);
    498 		if (m == 0)
    499 			break;
    500 
    501 		/* 5 seconds to watch for failing to transmit */
    502 		ifp->if_timer = 5;
    503 		ifp->if_opackets++;		/* # of pkts */
    504 
    505 		i = sc->sc_txnext;
    506 		buff = sc->sc_txbuf[i];
    507 		tlen = gmac_put(sc, buff, m);
    508 
    509 		dp = &sc->sc_txlist[i];
    510 		dp->cmd_hi = 0;
    511 		dp->address_hi = 0;
    512 		dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP);
    513 
    514 		i++;
    515 		if (i == NTXBUF)
    516 			i = 0;
    517 		__asm __volatile ("sync");
    518 
    519 		gmac_write_reg(sc, GMAC_TXDMAKICK, i);
    520 		sc->sc_txnext = i;
    521 
    522 #if NBPFILTER > 0
    523 		/*
    524 		 * If BPF is listening on this interface, let it see the
    525 		 * packet before we commit it to the wire.
    526 		 */
    527 		if (ifp->if_bpf)
    528 			bpf_mtap(ifp->if_bpf, m);
    529 #endif
    530 		m_freem(m);
    531 
    532 		i++;
    533 		if (i == NTXBUF)
    534 			i = 0;
    535 		if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) {
    536 			ifp->if_flags |= IFF_OACTIVE;
    537 			break;
    538 		}
    539 	}
    540 }
    541 
    542 int
    543 gmac_put(sc, buff, m)
    544 	struct gmac_softc *sc;
    545 	caddr_t buff;
    546 	struct mbuf *m;
    547 {
    548 	int len, tlen = 0;
    549 
    550 	for (; m; m = m->m_next) {
    551 		len = m->m_len;
    552 		if (len == 0)
    553 			continue;
    554 		memcpy(buff, mtod(m, caddr_t), len);
    555 		buff += len;
    556 		tlen += len;
    557 	}
    558 	if (tlen > 2048)
    559 		panic("%s: gmac_put packet overflow", sc->sc_dev.dv_xname);
    560 
    561 	return tlen;
    562 }
    563 
    564 void
    565 gmac_reset(sc)
    566 	struct gmac_softc *sc;
    567 {
    568 	int i, s;
    569 
    570 	s = splnet();
    571 
    572 	gmac_stop_txdma(sc);
    573 	gmac_stop_rxdma(sc);
    574 
    575 	gmac_write_reg(sc, GMAC_SOFTWARERESET, 3);
    576 	for (i = 10; i > 0; i--) {
    577 		delay(300000);				/* XXX long delay */
    578 		if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0)
    579 			break;
    580 	}
    581 	if (i == 0)
    582 		printf("%s: reset timeout\n", sc->sc_dev.dv_xname);
    583 
    584 	sc->sc_txnext = 0;
    585 	sc->sc_rxlast = 0;
    586 	for (i = 0; i < NRXBUF; i++)
    587 		sc->sc_rxlist[i].cmd = htole32(GMAC_OWN);
    588 	__asm __volatile ("sync");
    589 
    590 	gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0);
    591 	gmac_write_reg(sc, GMAC_TXDMADESCBASELO,
    592 		       vtophys((vaddr_t)sc->sc_txlist));
    593 	gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0);
    594 	gmac_write_reg(sc, GMAC_RXDMADESCBASELO,
    595 		       vtophys((vaddr_t)sc->sc_rxlist));
    596 	gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF);
    597 
    598 	splx(s);
    599 }
    600 
    601 void
    602 gmac_stop(sc)
    603 	struct gmac_softc *sc;
    604 {
    605 	struct ifnet *ifp = &sc->sc_if;
    606 	int s;
    607 
    608 	s = splnet();
    609 
    610 	callout_stop(&sc->sc_tick_ch);
    611 	mii_down(&sc->sc_mii);
    612 
    613 	gmac_stop_txdma(sc);
    614 	gmac_stop_rxdma(sc);
    615 
    616 	gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff);
    617 
    618 	ifp->if_flags &= ~(IFF_UP | IFF_RUNNING);
    619 	ifp->if_timer = 0;
    620 
    621 	splx(s);
    622 }
    623 
    624 void
    625 gmac_init_mac(sc)
    626 	struct gmac_softc *sc;
    627 {
    628 	int i, tb;
    629 	char *laddr = sc->sc_laddr;
    630 
    631 	__asm ("mftb %0" : "=r"(tb));
    632 	gmac_write_reg(sc, GMAC_RANDOMSEED, tb);
    633 
    634 	/* init-mii */
    635 	gmac_write_reg(sc, GMAC_DATAPATHMODE, 4);
    636 	gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000);
    637 
    638 	gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00);
    639 	gmac_write_reg(sc, GMAC_RXDMACONFIG, 0);
    640 	gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0);
    641 	gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0);
    642 	gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8);
    643 	gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4);
    644 	gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN);
    645 	gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN);
    646 	gmac_write_reg(sc, GMAC_PASIZE, 7);
    647 	gmac_write_reg(sc, GMAC_JAMSIZE, 4);
    648 	gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10);
    649 	gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808);
    650 
    651 	gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]);
    652 	gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]);
    653 	gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]);
    654 	gmac_write_reg(sc, GMAC_MACADDRESS3, 0);
    655 	gmac_write_reg(sc, GMAC_MACADDRESS4, 0);
    656 	gmac_write_reg(sc, GMAC_MACADDRESS5, 0);
    657 	gmac_write_reg(sc, GMAC_MACADDRESS6, 1);
    658 	gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200);
    659 	gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180);
    660 	gmac_write_reg(sc, GMAC_MACADDRFILT0, 0);
    661 	gmac_write_reg(sc, GMAC_MACADDRFILT1, 0);
    662 	gmac_write_reg(sc, GMAC_MACADDRFILT2, 0);
    663 	gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0);
    664 	gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0);
    665 
    666 	for (i = 0; i < 0x6c; i += 4)
    667 		gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0);
    668 
    669 	gmac_write_reg(sc, GMAC_SLOTTIME, 0x40);
    670 
    671 	if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) {
    672 		gmac_write_reg(sc, GMAC_TXMACCONFIG, 6);
    673 		gmac_write_reg(sc, GMAC_XIFCONFIG, 1);
    674 	} else {
    675 		gmac_write_reg(sc, GMAC_TXMACCONFIG, 0);
    676 		gmac_write_reg(sc, GMAC_XIFCONFIG, 5);
    677 	}
    678 
    679 	if (0)	/* g-bit? */
    680 		gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3);
    681 	else
    682 		gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0);
    683 }
    684 
    685 void
    686 gmac_setladrf(sc)
    687 	struct gmac_softc *sc;
    688 {
    689 	struct ifnet *ifp = &sc->sc_if;
    690 	struct ether_multi *enm;
    691 	struct ether_multistep step;
    692 	struct ethercom *ec = &sc->sc_ethercom;
    693 	u_int32_t crc;
    694 	u_int32_t hash[16];
    695 	u_int v;
    696 	int i;
    697 
    698 	/* Clear hash table */
    699 	for (i = 0; i < 16; i++)
    700 		hash[i] = 0;
    701 
    702 	/* Get current RX configuration */
    703 	v = gmac_read_reg(sc, GMAC_RXMACCONFIG);
    704 
    705 	if ((ifp->if_flags & IFF_PROMISC) != 0) {
    706 		/* Turn on promiscuous mode; turn off the hash filter */
    707 		v |= GMAC_RXMAC_PR;
    708 		v &= ~GMAC_RXMAC_HEN;
    709 		ifp->if_flags |= IFF_ALLMULTI;
    710 		goto chipit;
    711 	}
    712 
    713 	/* Turn off promiscuous mode; turn on the hash filter */
    714 	v &= ~GMAC_RXMAC_PR;
    715 	v |= GMAC_RXMAC_HEN;
    716 
    717 	/*
    718 	 * Set up multicast address filter by passing all multicast addresses
    719 	 * through a crc generator, and then using the high order 8 bits as an
    720 	 * index into the 256 bit logical address filter.  The high order bit
    721 	 * selects the word, while the rest of the bits select the bit within
    722 	 * the word.
    723 	 */
    724 
    725 	ETHER_FIRST_MULTI(step, ec, enm);
    726 	while (enm != NULL) {
    727 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) {
    728 			/*
    729 			 * We must listen to a range of multicast addresses.
    730 			 * For now, just accept all multicasts, rather than
    731 			 * trying to set only those filter bits needed to match
    732 			 * the range.  (At this time, the only use of address
    733 			 * ranges is for IP multicast routing, for which the
    734 			 * range is big enough to require all bits set.)
    735 			 */
    736 			for (i = 0; i < 16; i++)
    737 				hash[i] = 0xffff;
    738 			ifp->if_flags |= IFF_ALLMULTI;
    739 			goto chipit;
    740 		}
    741 
    742 		crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
    743 
    744 		/* Just want the 8 most significant bits. */
    745 		crc >>= 24;
    746 
    747 		/* Set the corresponding bit in the filter. */
    748 		hash[crc >> 4] |= 1 << (crc & 0xf);
    749 
    750 		ETHER_NEXT_MULTI(step, enm);
    751 	}
    752 
    753 	ifp->if_flags &= ~IFF_ALLMULTI;
    754 
    755 chipit:
    756 	/* Now load the hash table into the chip */
    757 	for (i = 0; i < 16; i++)
    758 		gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]);
    759 
    760 	gmac_write_reg(sc, GMAC_RXMACCONFIG, v);
    761 }
    762 
    763 void
    764 gmac_init(sc)
    765 	struct gmac_softc *sc;
    766 {
    767 	struct ifnet *ifp = &sc->sc_if;
    768 
    769 	gmac_stop_txdma(sc);
    770 	gmac_stop_rxdma(sc);
    771 
    772 	gmac_init_mac(sc);
    773 	gmac_setladrf(sc);
    774 
    775 	gmac_start_txdma(sc);
    776 	gmac_start_rxdma(sc);
    777 
    778 	gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE));
    779 
    780 	ifp->if_flags |= IFF_RUNNING;
    781 	ifp->if_flags &= ~IFF_OACTIVE;
    782 	ifp->if_timer = 0;
    783 
    784 	callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc);
    785 
    786 	gmac_start(ifp);
    787 }
    788 
    789 int
    790 gmac_ioctl(ifp, cmd, data)
    791 	struct ifnet *ifp;
    792 	u_long cmd;
    793 	caddr_t data;
    794 {
    795 	struct gmac_softc *sc = ifp->if_softc;
    796 	struct ifaddr *ifa = (struct ifaddr *)data;
    797 	struct ifreq *ifr = (struct ifreq *)data;
    798 	int s, error = 0;
    799 
    800 	s = splnet();
    801 
    802 	switch (cmd) {
    803 
    804 	case SIOCSIFADDR:
    805 		ifp->if_flags |= IFF_UP;
    806 
    807 		switch (ifa->ifa_addr->sa_family) {
    808 #ifdef INET
    809 		case AF_INET:
    810 			gmac_init(sc);
    811 			arp_ifinit(ifp, ifa);
    812 			break;
    813 #endif
    814 #ifdef NS
    815 		case AF_NS:
    816 		    {
    817 			struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
    818 
    819 			if (ns_nullhost(*ina))
    820 				ina->x_host =
    821 				    *(union ns_host *)LLADDR(ifp->if_sadl);
    822 			else {
    823 				memcpy(LLADDR(ifp->if_sadl),
    824 				    ina->x_host.c_host,
    825 				    sizeof(sc->sc_enaddr));
    826 			}
    827 			/* Set new address. */
    828 			gmac_init(sc);
    829 			break;
    830 		    }
    831 #endif
    832 		default:
    833 			gmac_init(sc);
    834 			break;
    835 		}
    836 		break;
    837 
    838 	case SIOCSIFFLAGS:
    839 		if ((ifp->if_flags & IFF_UP) == 0 &&
    840 		    (ifp->if_flags & IFF_RUNNING) != 0) {
    841 			/*
    842 			 * If interface is marked down and it is running, then
    843 			 * stop it.
    844 			 */
    845 			gmac_stop(sc);
    846 			ifp->if_flags &= ~IFF_RUNNING;
    847 		} else if ((ifp->if_flags & IFF_UP) != 0 &&
    848 		    (ifp->if_flags & IFF_RUNNING) == 0) {
    849 			/*
    850 			 * If interface is marked up and it is stopped, then
    851 			 * start it.
    852 			 */
    853 			gmac_init(sc);
    854 		} else {
    855 			/*
    856 			 * Reset the interface to pick up changes in any other
    857 			 * flags that affect hardware registers.
    858 			 */
    859 			gmac_reset(sc);
    860 			gmac_init(sc);
    861 		}
    862 #ifdef GMAC_DEBUG
    863 		if (ifp->if_flags & IFF_DEBUG)
    864 			sc->sc_flags |= GMAC_DEBUGFLAG;
    865 #endif
    866 		break;
    867 
    868 	case SIOCADDMULTI:
    869 	case SIOCDELMULTI:
    870 		error = (cmd == SIOCADDMULTI) ?
    871 		    ether_addmulti(ifr, &sc->sc_ethercom) :
    872 		    ether_delmulti(ifr, &sc->sc_ethercom);
    873 
    874 		if (error == ENETRESET) {
    875 			/*
    876 			 * Multicast list has changed; set the hardware filter
    877 			 * accordingly.
    878 			 */
    879 			gmac_init(sc);
    880 			/* gmac_setladrf(sc); */
    881 			error = 0;
    882 		}
    883 		break;
    884 
    885 	case SIOCGIFMEDIA:
    886 	case SIOCSIFMEDIA:
    887 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
    888 		break;
    889 
    890 	default:
    891 		error = EINVAL;
    892 	}
    893 
    894 	splx(s);
    895 	return error;
    896 }
    897 
    898 void
    899 gmac_watchdog(ifp)
    900 	struct ifnet *ifp;
    901 {
    902 	struct gmac_softc *sc = ifp->if_softc;
    903 
    904 	printf("%s: device timeout\n", ifp->if_xname);
    905 	ifp->if_oerrors++;
    906 
    907 	gmac_reset(sc);
    908 	gmac_init(sc);
    909 }
    910 
    911 int
    912 gmac_mediachange(ifp)
    913 	struct ifnet *ifp;
    914 {
    915 	struct gmac_softc *sc = ifp->if_softc;
    916 
    917 	return mii_mediachg(&sc->sc_mii);
    918 }
    919 
    920 void
    921 gmac_mediastatus(ifp, ifmr)
    922 	struct ifnet *ifp;
    923 	struct ifmediareq *ifmr;
    924 {
    925 	struct gmac_softc *sc = ifp->if_softc;
    926 
    927 	mii_pollstat(&sc->sc_mii);
    928 
    929 	ifmr->ifm_status = sc->sc_mii.mii_media_status;
    930 	ifmr->ifm_active = sc->sc_mii.mii_media_active;
    931 }
    932 
    933 int
    934 gmac_mii_readreg(dev, phy, reg)
    935 	struct device *dev;
    936 	int phy, reg;
    937 {
    938 	struct gmac_softc *sc = (void *)dev;
    939 	int i;
    940 
    941 	gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT,
    942 		0x60020000 | (phy << 23) | (reg << 18));
    943 
    944 	for (i = 1000; i >= 0; i -= 10) {
    945 		if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000)
    946 			break;
    947 		delay(10);
    948 	}
    949 	if (i < 0) {
    950 		printf("%s: gmac_mii_readreg: timeout\n", sc->sc_dev.dv_xname);
    951 		return 0;
    952 	}
    953 
    954 	return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff;
    955 }
    956 
    957 void
    958 gmac_mii_writereg(dev, phy, reg, val)
    959 	struct device *dev;
    960 	int phy, reg, val;
    961 {
    962 	struct gmac_softc *sc = (void *)dev;
    963 	int i;
    964 
    965 	gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT,
    966 		0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff));
    967 
    968 	for (i = 1000; i >= 0; i -= 10) {
    969 		if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000)
    970 			break;
    971 		delay(10);
    972 	}
    973 	if (i < 0)
    974 		printf("%s: gmac_mii_writereg: timeout\n", sc->sc_dev.dv_xname);
    975 }
    976 
    977 void
    978 gmac_mii_statchg(dev)
    979 	struct device *dev;
    980 {
    981 	struct gmac_softc *sc = (void *)dev;
    982 
    983 	gmac_stop_txdma(sc);
    984 	gmac_stop_rxdma(sc);
    985 
    986 	if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) {
    987 		gmac_write_reg(sc, GMAC_TXMACCONFIG, 6);
    988 		gmac_write_reg(sc, GMAC_XIFCONFIG, 1);
    989 	} else {
    990 		gmac_write_reg(sc, GMAC_TXMACCONFIG, 0);
    991 		gmac_write_reg(sc, GMAC_XIFCONFIG, 5);
    992 	}
    993 
    994 	if (0)	/* g-bit? */
    995 		gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3);
    996 	else
    997 		gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0);
    998 
    999 	gmac_start_txdma(sc);
   1000 	gmac_start_rxdma(sc);
   1001 }
   1002 
   1003 void
   1004 gmac_mii_tick(v)
   1005 	void *v;
   1006 {
   1007 	struct gmac_softc *sc = v;
   1008 	int s;
   1009 
   1010 	s = splnet();
   1011 	mii_tick(&sc->sc_mii);
   1012 	splx(s);
   1013 
   1014 	callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc);
   1015 }
   1016