if_gm.c revision 1.2
1 /* $NetBSD: if_gm.c,v 1.2 2000/03/04 11:17:00 tsubai Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_inet.h" 30 #include "opt_ns.h" 31 #include "bpfilter.h" 32 33 #include <sys/param.h> 34 #include <sys/device.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/mbuf.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 41 #include <vm/vm.h> 42 43 #include <net/if.h> 44 #include <net/if_ether.h> 45 #include <net/if_media.h> 46 47 #if NBPFILTER > 0 48 #include <net/bpf.h> 49 #endif 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/if_inarp.h> 54 #endif 55 56 #include <dev/mii/mii.h> 57 #include <dev/mii/miivar.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/ofw/openfirm.h> 64 #include <macppc/dev/if_gmreg.h> 65 #include <machine/pio.h> 66 67 #define NTXBUF 4 68 #define NRXBUF 32 69 70 struct gmac_softc { 71 struct device sc_dev; 72 struct ethercom sc_ethercom; 73 vaddr_t sc_reg; 74 struct gmac_dma *sc_txlist; 75 struct gmac_dma *sc_rxlist; 76 int sc_txnext; 77 int sc_rxlast; 78 caddr_t sc_txbuf[NTXBUF]; 79 caddr_t sc_rxbuf[NRXBUF]; 80 struct mii_data sc_mii; 81 char sc_laddr[6]; 82 }; 83 84 #define sc_if sc_ethercom.ec_if 85 86 int gmac_match __P((struct device *, struct cfdata *, void *)); 87 void gmac_attach __P((struct device *, struct device *, void *)); 88 89 static __inline u_int gmac_read_reg __P((struct gmac_softc *, int)); 90 static __inline void gmac_write_reg __P((struct gmac_softc *, int, u_int)); 91 92 static __inline void gmac_start_txdma __P((struct gmac_softc *)); 93 static __inline void gmac_start_rxdma __P((struct gmac_softc *)); 94 static __inline void gmac_stop_txdma __P((struct gmac_softc *)); 95 static __inline void gmac_stop_rxdma __P((struct gmac_softc *)); 96 97 int gmac_intr __P((void *)); 98 void gmac_tint __P((struct gmac_softc *)); 99 void gmac_rint __P((struct gmac_softc *)); 100 struct mbuf * gmac_get __P((struct gmac_softc *, caddr_t, int)); 101 void gmac_start __P((struct ifnet *)); 102 int gmac_put __P((struct gmac_softc *, caddr_t, struct mbuf *)); 103 104 void gmac_stop __P((struct gmac_softc *)); 105 void gmac_reset __P((struct gmac_softc *)); 106 void gmac_init __P((struct gmac_softc *)); 107 void gmac_init_mac __P((struct gmac_softc *)); 108 109 int gmac_ioctl __P((struct ifnet *, u_long, caddr_t)); 110 void gmac_watchdog __P((struct ifnet *)); 111 112 int gmac_mediachange __P((struct ifnet *)); 113 void gmac_mediastatus __P((struct ifnet *, struct ifmediareq *)); 114 int gmac_mii_readreg __P((struct device *, int, int)); 115 void gmac_mii_writereg __P((struct device *, int, int, int)); 116 void gmac_mii_statchg __P((struct device *)); 117 void gmac_mii_tick __P((void *)); 118 119 struct cfattach gm_ca = { 120 sizeof(struct gmac_softc), gmac_match, gmac_attach 121 }; 122 123 int 124 gmac_match(parent, match, aux) 125 struct device *parent; 126 struct cfdata *match; 127 void *aux; 128 { 129 struct pci_attach_args *pa = aux; 130 131 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 132 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC) 133 return 1; 134 135 return 0; 136 } 137 138 void 139 gmac_attach(parent, self, aux) 140 struct device *parent, *self; 141 void *aux; 142 { 143 struct gmac_softc *sc = (void *)self; 144 struct pci_attach_args *pa = aux; 145 struct ifnet *ifp = &sc->sc_if; 146 struct mii_data *mii = &sc->sc_mii; 147 pci_intr_handle_t ih; 148 const char *intrstr = NULL; 149 int node, i; 150 char *p; 151 struct gmac_dma *dp; 152 u_int32_t reg[10]; 153 u_char laddr[6]; 154 155 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 156 if (node == 0) { 157 printf(": cannot find gmac node\n"); 158 return; 159 } 160 161 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 162 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 163 164 bcopy(laddr, sc->sc_laddr, sizeof laddr); 165 sc->sc_reg = reg[2]; 166 167 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 168 pa->pa_intrline, &ih)) { 169 printf(": unable to map interrupt\n"); 170 return; 171 } 172 intrstr = pci_intr_string(pa->pa_pc, ih); 173 174 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 175 printf(": unable to establish interrupt"); 176 if (intrstr) 177 printf(" at %s", intrstr); 178 printf("\n"); 179 return; 180 } 181 182 /* Setup packet buffers and dma descriptors. */ 183 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 184 if (p == NULL) { 185 printf(": cannot malloc buffers\n"); 186 return; 187 } 188 p = (void *)roundup((vaddr_t)p, 0x800); 189 bzero(p, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 190 191 sc->sc_rxlist = (void *)p; 192 p += 0x800; 193 sc->sc_txlist = (void *)p; 194 p += 0x800; 195 196 dp = sc->sc_rxlist; 197 for (i = 0; i < NRXBUF; i++) { 198 sc->sc_rxbuf[i] = p; 199 dp->address = htole32(vtophys(p)); 200 dp->cmd = htole32(GMAC_OWN); 201 dp++; 202 p += 2048; 203 } 204 205 dp = sc->sc_txlist; 206 for (i = 0; i < NTXBUF; i++) { 207 sc->sc_txbuf[i] = p; 208 dp->address = htole32(vtophys(p)); 209 dp++; 210 p += 2048; 211 } 212 213 printf(": Ethernet address %s\n", ether_sprintf(laddr)); 214 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 215 216 gmac_reset(sc); 217 gmac_init_mac(sc); 218 219 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 220 ifp->if_softc = sc; 221 ifp->if_ioctl = gmac_ioctl; 222 ifp->if_start = gmac_start; 223 ifp->if_watchdog = gmac_watchdog; 224 ifp->if_flags = 225 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 226 ifp->if_flags |= IFF_ALLMULTI; 227 228 mii->mii_ifp = ifp; 229 mii->mii_readreg = gmac_mii_readreg; 230 mii->mii_writereg = gmac_mii_writereg; 231 mii->mii_statchg = gmac_mii_statchg; 232 233 ifmedia_init(&mii->mii_media, 0, gmac_mediachange, gmac_mediastatus); 234 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 235 236 /* Choose a default media. */ 237 if (LIST_FIRST(&mii->mii_phys) == NULL) { 238 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 239 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 240 } else 241 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 242 243 if_attach(ifp); 244 ether_ifattach(ifp, laddr); 245 246 #if NBPFILTER > 0 247 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 248 #endif 249 } 250 251 u_int 252 gmac_read_reg(sc, reg) 253 struct gmac_softc *sc; 254 int reg; 255 { 256 return in32rb(sc->sc_reg + reg); 257 } 258 259 void 260 gmac_write_reg(sc, reg, val) 261 struct gmac_softc *sc; 262 int reg; 263 u_int val; 264 { 265 out32rb(sc->sc_reg + reg, val); 266 } 267 268 void 269 gmac_start_txdma(sc) 270 struct gmac_softc *sc; 271 { 272 u_int x; 273 274 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 275 x |= 1; 276 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 277 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 278 x |= 1; 279 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 280 } 281 282 void 283 gmac_start_rxdma(sc) 284 struct gmac_softc *sc; 285 { 286 u_int x; 287 288 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 289 x |= 1; 290 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 291 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 292 x |= 1; 293 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 294 } 295 296 void 297 gmac_stop_txdma(sc) 298 struct gmac_softc *sc; 299 { 300 u_int x; 301 302 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 303 x &= ~1; 304 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 305 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 306 x &= ~1; 307 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 308 } 309 310 void 311 gmac_stop_rxdma(sc) 312 struct gmac_softc *sc; 313 { 314 u_int x; 315 316 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 317 x &= ~1; 318 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 319 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 320 x &= ~1; 321 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 322 } 323 324 int 325 gmac_intr(v) 326 void *v; 327 { 328 struct gmac_softc *sc = v; 329 u_int status; 330 331 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 332 if (status == 0) 333 return 0; 334 335 if (status & GMAC_INT_RXDONE) 336 gmac_rint(sc); 337 338 if (status & GMAC_INT_TXDONE) 339 gmac_tint(sc); 340 341 return 1; 342 } 343 344 void 345 gmac_tint(sc) 346 struct gmac_softc *sc; 347 { 348 struct ifnet *ifp = &sc->sc_if; 349 volatile struct gmac_dma *dp; 350 int i; 351 352 i = gmac_read_reg(sc, GMAC_TXDMACOMPLETE); 353 dp = &sc->sc_txlist[i]; 354 dp->cmd = 0; /* to be safe */ 355 __asm __volatile ("sync"); 356 357 ifp->if_flags &= ~IFF_OACTIVE; 358 ifp->if_timer = 0; 359 ifp->if_opackets++; 360 gmac_start(ifp); 361 } 362 363 void 364 gmac_rint(sc) 365 struct gmac_softc *sc; 366 { 367 struct ifnet *ifp = &sc->sc_if; 368 volatile struct gmac_dma *dp; 369 struct mbuf *m; 370 int i, len; 371 u_int cmd; 372 373 for (i = sc->sc_rxlast;; i++) { 374 if (i == NRXBUF) 375 i = 0; 376 377 dp = &sc->sc_rxlist[i]; 378 cmd = le32toh(dp->cmd); 379 if (cmd & GMAC_OWN) 380 break; 381 len = (cmd >> 16) & GMAC_LEN_MASK; 382 len -= 4; /* CRC */ 383 384 if (le32toh(dp->cmd_hi) & 0x40000000) { 385 ifp->if_ierrors++; 386 goto next; 387 } 388 389 m = gmac_get(sc, sc->sc_rxbuf[i], len); 390 if (m == NULL) { 391 ifp->if_ierrors++; 392 goto next; 393 } 394 395 #if NBPFILTER > 0 396 /* 397 * Check if there's a BPF listener on this interface. 398 * If so, hand off the raw packet to BPF. 399 */ 400 if (ifp->if_bpf) 401 bpf_tap(ifp->if_bpf, sc->sc_rxbuf[i], len); 402 #endif 403 (*ifp->if_input)(ifp, m); 404 ifp->if_ipackets++; 405 406 next: 407 dp->cmd_hi = 0; 408 __asm __volatile ("sync"); 409 dp->cmd = htole32(GMAC_OWN); 410 } 411 sc->sc_rxlast = i; 412 } 413 414 struct mbuf * 415 gmac_get(sc, pkt, totlen) 416 struct gmac_softc *sc; 417 caddr_t pkt; 418 int totlen; 419 { 420 struct mbuf *m; 421 struct mbuf *top, **mp; 422 int len; 423 424 MGETHDR(m, M_DONTWAIT, MT_DATA); 425 if (m == 0) 426 return 0; 427 m->m_pkthdr.rcvif = &sc->sc_if; 428 m->m_pkthdr.len = totlen; 429 len = MHLEN; 430 top = 0; 431 mp = ⊤ 432 433 while (totlen > 0) { 434 if (top) { 435 MGET(m, M_DONTWAIT, MT_DATA); 436 if (m == 0) { 437 m_freem(top); 438 return 0; 439 } 440 len = MLEN; 441 } 442 if (totlen >= MINCLSIZE) { 443 MCLGET(m, M_DONTWAIT); 444 if ((m->m_flags & M_EXT) == 0) { 445 m_free(m); 446 m_freem(top); 447 return 0; 448 } 449 len = MCLBYTES; 450 } 451 m->m_len = len = min(totlen, len); 452 bcopy(pkt, mtod(m, caddr_t), len); 453 pkt += len; 454 totlen -= len; 455 *mp = m; 456 mp = &m->m_next; 457 } 458 459 return top; 460 } 461 462 void 463 gmac_start(ifp) 464 struct ifnet *ifp; 465 { 466 struct gmac_softc *sc = ifp->if_softc; 467 struct mbuf *m; 468 caddr_t buff; 469 int i, tlen; 470 volatile struct gmac_dma *dp; 471 472 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 473 return; 474 475 for (;;) { 476 if (ifp->if_flags & IFF_OACTIVE) 477 break; 478 479 IF_DEQUEUE(&ifp->if_snd, m); 480 if (m == 0) 481 break; 482 483 ifp->if_flags |= IFF_OACTIVE; 484 485 /* 5 seconds to watch for failing to transmit */ 486 ifp->if_timer = 5; 487 ifp->if_opackets++; /* # of pkts */ 488 489 i = sc->sc_txnext; 490 buff = sc->sc_txbuf[i]; 491 tlen = gmac_put(sc, buff, m); 492 493 dp = &sc->sc_txlist[i]; 494 dp->cmd_hi = 0; 495 dp->address_hi = 0; 496 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 497 498 i++; 499 if (i == NTXBUF) 500 i = 0; 501 __asm __volatile ("sync"); 502 503 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 504 sc->sc_txnext = i; 505 506 #if NBPFILTER > 0 507 /* 508 * If BPF is listening on this interface, let it see the 509 * packet before we commit it to the wire. 510 */ 511 if (ifp->if_bpf) 512 bpf_tap(ifp->if_bpf, buff, tlen); 513 #endif 514 } 515 } 516 517 int 518 gmac_put(sc, buff, m) 519 struct gmac_softc *sc; 520 caddr_t buff; 521 struct mbuf *m; 522 { 523 struct mbuf *n; 524 int len, tlen = 0; 525 526 for (; m; m = n) { 527 len = m->m_len; 528 if (len == 0) { 529 MFREE(m, n); 530 continue; 531 } 532 bcopy(mtod(m, caddr_t), buff, len); 533 buff += len; 534 tlen += len; 535 MFREE(m, n); 536 } 537 if (tlen > 2048) 538 panic("%s: gmac_put packet overflow", sc->sc_dev.dv_xname); 539 540 return tlen; 541 } 542 543 void 544 gmac_reset(sc) 545 struct gmac_softc *sc; 546 { 547 int i, s; 548 549 s = splnet(); 550 551 gmac_stop_txdma(sc); 552 gmac_stop_rxdma(sc); 553 554 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 555 for (i = 10; i > 0; i--) { 556 delay(300000); /* XXX long delay */ 557 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 558 break; 559 } 560 if (i == 0) 561 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 562 563 sc->sc_txnext = 0; 564 sc->sc_rxlast = 0; 565 for (i = 0; i < NRXBUF; i++) 566 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 567 __asm __volatile ("sync"); 568 569 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 570 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, vtophys(sc->sc_txlist)); 571 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 572 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, vtophys(sc->sc_rxlist)); 573 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 574 575 splx(s); 576 } 577 578 void 579 gmac_stop(sc) 580 struct gmac_softc *sc; 581 { 582 struct ifnet *ifp = &sc->sc_if; 583 int s; 584 585 s = splnet(); 586 587 untimeout(gmac_mii_tick, sc); 588 mii_down(&sc->sc_mii); 589 590 gmac_stop_txdma(sc); 591 gmac_stop_rxdma(sc); 592 593 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 594 595 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 596 ifp->if_timer = 0; 597 598 splx(s); 599 } 600 601 void 602 gmac_init_mac(sc) 603 struct gmac_softc *sc; 604 { 605 int i, tb; 606 char *laddr = sc->sc_laddr; 607 608 __asm ("mftb %0" : "=r"(tb)); 609 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 610 611 /* init-mii */ 612 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 613 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 614 615 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 616 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 617 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 618 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 619 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 620 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 621 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 622 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 623 gmac_write_reg(sc, GMAC_PASIZE, 7); 624 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 625 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10); 626 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 627 628 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 629 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 630 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 631 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 632 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 633 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 634 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 635 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 636 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 637 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 638 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 639 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 640 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 641 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 642 643 for (i = 0; i < 0x6c; i+= 4) 644 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 645 646 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 647 648 /* XXX */ 649 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 650 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 651 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 652 } 653 654 void 655 gmac_init(sc) 656 struct gmac_softc *sc; 657 { 658 struct ifnet *ifp = &sc->sc_if; 659 u_int x; 660 int i; 661 662 gmac_stop_txdma(sc); 663 gmac_stop_rxdma(sc); 664 665 gmac_init_mac(sc); 666 667 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 668 if (ifp->if_flags & IFF_PROMISC) 669 x |= GMAC_RXMAC_PR; 670 else 671 x &= ~GMAC_RXMAC_PR; 672 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 673 674 gmac_start_txdma(sc); 675 gmac_start_rxdma(sc); 676 677 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXDONE | GMAC_INT_RXDONE)); 678 679 ifp->if_flags |= IFF_RUNNING; 680 ifp->if_flags &= ~IFF_OACTIVE; 681 ifp->if_timer = 0; 682 683 untimeout(gmac_mii_tick, sc); 684 timeout(gmac_mii_tick, sc, 1); 685 686 gmac_start(ifp); 687 } 688 689 int 690 gmac_ioctl(ifp, cmd, data) 691 struct ifnet *ifp; 692 u_long cmd; 693 caddr_t data; 694 { 695 struct gmac_softc *sc = ifp->if_softc; 696 struct ifaddr *ifa = (struct ifaddr *)data; 697 struct ifreq *ifr = (struct ifreq *)data; 698 int s, error = 0; 699 700 s = splnet(); 701 702 switch (cmd) { 703 704 case SIOCSIFADDR: 705 ifp->if_flags |= IFF_UP; 706 707 switch (ifa->ifa_addr->sa_family) { 708 #ifdef INET 709 case AF_INET: 710 gmac_init(sc); 711 arp_ifinit(ifp, ifa); 712 break; 713 #endif 714 #ifdef NS 715 case AF_NS: 716 { 717 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 718 719 if (ns_nullhost(*ina)) 720 ina->x_host = 721 *(union ns_host *)LLADDR(ifp->if_sadl); 722 else { 723 bcopy(ina->x_host.c_host, 724 LLADDR(ifp->if_sadl), 725 sizeof(sc->sc_enaddr)); 726 } 727 /* Set new address. */ 728 gmac_init(sc); 729 break; 730 } 731 #endif 732 default: 733 gmac_init(sc); 734 break; 735 } 736 break; 737 738 case SIOCSIFFLAGS: 739 if ((ifp->if_flags & IFF_UP) == 0 && 740 (ifp->if_flags & IFF_RUNNING) != 0) { 741 /* 742 * If interface is marked down and it is running, then 743 * stop it. 744 */ 745 gmac_stop(sc); 746 ifp->if_flags &= ~IFF_RUNNING; 747 } else if ((ifp->if_flags & IFF_UP) != 0 && 748 (ifp->if_flags & IFF_RUNNING) == 0) { 749 /* 750 * If interface is marked up and it is stopped, then 751 * start it. 752 */ 753 gmac_init(sc); 754 } else { 755 /* 756 * Reset the interface to pick up changes in any other 757 * flags that affect hardware registers. 758 */ 759 gmac_reset(sc); 760 gmac_init(sc); 761 } 762 #ifdef GMAC_DEBUG 763 if (ifp->if_flags & IFF_DEBUG) 764 sc->sc_flags |= GMAC_DEBUGFLAG; 765 #endif 766 break; 767 768 case SIOCADDMULTI: 769 case SIOCDELMULTI: 770 error = (cmd == SIOCADDMULTI) ? 771 ether_addmulti(ifr, &sc->sc_ethercom) : 772 ether_delmulti(ifr, &sc->sc_ethercom); 773 774 if (error == ENETRESET) { 775 /* 776 * Multicast list has changed; set the hardware filter 777 * accordingly. 778 */ 779 gmac_init(sc); 780 /* gmac_setladrf(sc); */ 781 error = 0; 782 } 783 break; 784 785 case SIOCGIFMEDIA: 786 case SIOCSIFMEDIA: 787 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 788 break; 789 790 default: 791 error = EINVAL; 792 } 793 794 splx(s); 795 return error; 796 } 797 798 void 799 gmac_watchdog(ifp) 800 struct ifnet *ifp; 801 { 802 struct gmac_softc *sc = ifp->if_softc; 803 804 printf("%s: device timeout\n", ifp->if_xname); 805 ifp->if_oerrors++; 806 807 gmac_reset(sc); 808 gmac_init(sc); 809 } 810 811 int 812 gmac_mediachange(ifp) 813 struct ifnet *ifp; 814 { 815 struct gmac_softc *sc = ifp->if_softc; 816 817 return mii_mediachg(&sc->sc_mii); 818 } 819 820 void 821 gmac_mediastatus(ifp, ifmr) 822 struct ifnet *ifp; 823 struct ifmediareq *ifmr; 824 { 825 struct gmac_softc *sc = ifp->if_softc; 826 827 mii_pollstat(&sc->sc_mii); 828 829 ifmr->ifm_status = sc->sc_mii.mii_media_status; 830 ifmr->ifm_active = sc->sc_mii.mii_media_active; 831 } 832 833 int 834 gmac_mii_readreg(dev, phy, reg) 835 struct device *dev; 836 int phy, reg; 837 { 838 struct gmac_softc *sc = (void *)dev; 839 int i; 840 841 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 842 0x60020000 | (phy << 23) | (reg << 18)); 843 844 for (i = 1000; i >= 0; i -= 10) { 845 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 846 break; 847 delay(10); 848 } 849 if (i < 0) { 850 printf("%s: gmac_mii_readreg: timeout\n", sc->sc_dev.dv_xname); 851 return 0; 852 } 853 854 return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 855 } 856 857 void 858 gmac_mii_writereg(dev, phy, reg, val) 859 struct device *dev; 860 int phy, reg, val; 861 { 862 struct gmac_softc *sc = (void *)dev; 863 int i; 864 865 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 866 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 867 868 for (i = 1000; i >= 0; i -= 10) { 869 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 870 break; 871 delay(10); 872 } 873 if (i < 0) 874 printf("%s: gmac_mii_writereg: timeout\n", sc->sc_dev.dv_xname); 875 } 876 877 void 878 gmac_mii_statchg(dev) 879 struct device *dev; 880 { 881 struct gmac_softc *sc = (void *)dev; 882 883 gmac_stop_txdma(sc); 884 gmac_stop_rxdma(sc); 885 886 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 887 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 888 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 889 } else { 890 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 891 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 892 } 893 894 if (0) /* g-bit? */ 895 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 896 else 897 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 898 899 gmac_start_txdma(sc); 900 gmac_start_rxdma(sc); 901 } 902 903 void 904 gmac_mii_tick(v) 905 void *v; 906 { 907 struct gmac_softc *sc = v; 908 int s; 909 910 s = splnet(); 911 mii_tick(&sc->sc_mii); 912 splx(s); 913 914 timeout(gmac_mii_tick, sc, hz); 915 } 916
Indexes created Tue Sep 30 20:09:53 GMT 2025