if_gm.c revision 1.26
1 /* $NetBSD: if_gm.c,v 1.26 2005/12/24 20:07:15 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_gm.c,v 1.26 2005/12/24 20:07:15 perry Exp $"); 31 32 #include "opt_inet.h" 33 #include "opt_ns.h" 34 #include "rnd.h" 35 #include "bpfilter.h" 36 37 #include <sys/param.h> 38 #include <sys/device.h> 39 #include <sys/ioctl.h> 40 #include <sys/kernel.h> 41 #include <sys/mbuf.h> 42 #include <sys/socket.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 46 #if NRND > 0 47 #include <sys/rnd.h> 48 #endif 49 50 #include <uvm/uvm_extern.h> 51 52 #include <net/if.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 56 #if NBPFILTER > 0 57 #include <net/bpf.h> 58 #endif 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/if_inarp.h> 63 #endif 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/ofw/openfirm.h> 73 #include <macppc/dev/if_gmreg.h> 74 #include <machine/pio.h> 75 76 #define NTXBUF 4 77 #define NRXBUF 32 78 79 struct gmac_softc { 80 struct device sc_dev; 81 struct ethercom sc_ethercom; 82 vaddr_t sc_reg; 83 struct gmac_dma *sc_txlist; 84 struct gmac_dma *sc_rxlist; 85 int sc_txnext; 86 int sc_rxlast; 87 caddr_t sc_txbuf[NTXBUF]; 88 caddr_t sc_rxbuf[NRXBUF]; 89 struct mii_data sc_mii; 90 struct callout sc_tick_ch; 91 char sc_laddr[6]; 92 93 #if NRND > 0 94 rndsource_element_t sc_rnd_source; /* random source */ 95 #endif 96 }; 97 98 #define sc_if sc_ethercom.ec_if 99 100 int gmac_match __P((struct device *, struct cfdata *, void *)); 101 void gmac_attach __P((struct device *, struct device *, void *)); 102 103 static inline u_int gmac_read_reg __P((struct gmac_softc *, int)); 104 static inline void gmac_write_reg __P((struct gmac_softc *, int, u_int)); 105 106 static inline void gmac_start_txdma __P((struct gmac_softc *)); 107 static inline void gmac_start_rxdma __P((struct gmac_softc *)); 108 static inline void gmac_stop_txdma __P((struct gmac_softc *)); 109 static inline void gmac_stop_rxdma __P((struct gmac_softc *)); 110 111 int gmac_intr __P((void *)); 112 void gmac_tint __P((struct gmac_softc *)); 113 void gmac_rint __P((struct gmac_softc *)); 114 struct mbuf * gmac_get __P((struct gmac_softc *, caddr_t, int)); 115 void gmac_start __P((struct ifnet *)); 116 int gmac_put __P((struct gmac_softc *, caddr_t, struct mbuf *)); 117 118 void gmac_stop __P((struct gmac_softc *)); 119 void gmac_reset __P((struct gmac_softc *)); 120 void gmac_init __P((struct gmac_softc *)); 121 void gmac_init_mac __P((struct gmac_softc *)); 122 void gmac_setladrf __P((struct gmac_softc *)); 123 124 int gmac_ioctl __P((struct ifnet *, u_long, caddr_t)); 125 void gmac_watchdog __P((struct ifnet *)); 126 127 int gmac_mediachange __P((struct ifnet *)); 128 void gmac_mediastatus __P((struct ifnet *, struct ifmediareq *)); 129 int gmac_mii_readreg __P((struct device *, int, int)); 130 void gmac_mii_writereg __P((struct device *, int, int, int)); 131 void gmac_mii_statchg __P((struct device *)); 132 void gmac_mii_tick __P((void *)); 133 134 CFATTACH_DECL(gm, sizeof(struct gmac_softc), 135 gmac_match, gmac_attach, NULL, NULL); 136 137 int 138 gmac_match(parent, match, aux) 139 struct device *parent; 140 struct cfdata *match; 141 void *aux; 142 { 143 struct pci_attach_args *pa = aux; 144 145 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 146 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 147 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 148 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3)) 149 return 1; 150 151 return 0; 152 } 153 154 void 155 gmac_attach(parent, self, aux) 156 struct device *parent, *self; 157 void *aux; 158 { 159 struct gmac_softc *sc = (void *)self; 160 struct pci_attach_args *pa = aux; 161 struct ifnet *ifp = &sc->sc_if; 162 struct mii_data *mii = &sc->sc_mii; 163 pci_intr_handle_t ih; 164 const char *intrstr = NULL; 165 int node, i; 166 char *p; 167 struct gmac_dma *dp; 168 u_int32_t reg[10]; 169 u_char laddr[6]; 170 171 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 172 if (node == 0) { 173 printf(": cannot find gmac node\n"); 174 return; 175 } 176 177 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 178 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 179 180 memcpy(sc->sc_laddr, laddr, sizeof laddr); 181 sc->sc_reg = reg[2]; 182 183 if (pci_intr_map(pa, &ih)) { 184 printf(": unable to map interrupt\n"); 185 return; 186 } 187 intrstr = pci_intr_string(pa->pa_pc, ih); 188 189 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 190 printf(": unable to establish interrupt"); 191 if (intrstr) 192 printf(" at %s", intrstr); 193 printf("\n"); 194 return; 195 } 196 197 /* Setup packet buffers and DMA descriptors. */ 198 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 199 if (p == NULL) { 200 printf(": cannot malloc buffers\n"); 201 return; 202 } 203 p = (void *)roundup((vaddr_t)p, 0x800); 204 memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 205 206 sc->sc_rxlist = (void *)p; 207 p += 0x800; 208 sc->sc_txlist = (void *)p; 209 p += 0x800; 210 211 dp = sc->sc_rxlist; 212 for (i = 0; i < NRXBUF; i++) { 213 sc->sc_rxbuf[i] = p; 214 dp->address = htole32(vtophys((vaddr_t)p)); 215 dp->cmd = htole32(GMAC_OWN); 216 dp++; 217 p += 2048; 218 } 219 220 dp = sc->sc_txlist; 221 for (i = 0; i < NTXBUF; i++) { 222 sc->sc_txbuf[i] = p; 223 dp->address = htole32(vtophys((vaddr_t)p)); 224 dp++; 225 p += 2048; 226 } 227 228 printf(": Ethernet address %s\n", ether_sprintf(laddr)); 229 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 230 231 callout_init(&sc->sc_tick_ch); 232 233 gmac_reset(sc); 234 gmac_init_mac(sc); 235 236 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 237 ifp->if_softc = sc; 238 ifp->if_ioctl = gmac_ioctl; 239 ifp->if_start = gmac_start; 240 ifp->if_watchdog = gmac_watchdog; 241 ifp->if_flags = 242 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 243 IFQ_SET_READY(&ifp->if_snd); 244 245 mii->mii_ifp = ifp; 246 mii->mii_readreg = gmac_mii_readreg; 247 mii->mii_writereg = gmac_mii_writereg; 248 mii->mii_statchg = gmac_mii_statchg; 249 250 ifmedia_init(&mii->mii_media, 0, gmac_mediachange, gmac_mediastatus); 251 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 252 253 /* Choose a default media. */ 254 if (LIST_FIRST(&mii->mii_phys) == NULL) { 255 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 256 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 257 } else 258 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 259 260 if_attach(ifp); 261 ether_ifattach(ifp, laddr); 262 #if NRND > 0 263 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 264 RND_TYPE_NET, 0); 265 #endif 266 } 267 268 u_int 269 gmac_read_reg(sc, reg) 270 struct gmac_softc *sc; 271 int reg; 272 { 273 return in32rb(sc->sc_reg + reg); 274 } 275 276 void 277 gmac_write_reg(sc, reg, val) 278 struct gmac_softc *sc; 279 int reg; 280 u_int val; 281 { 282 out32rb(sc->sc_reg + reg, val); 283 } 284 285 void 286 gmac_start_txdma(sc) 287 struct gmac_softc *sc; 288 { 289 u_int x; 290 291 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 292 x |= 1; 293 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 294 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 295 x |= 1; 296 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 297 } 298 299 void 300 gmac_start_rxdma(sc) 301 struct gmac_softc *sc; 302 { 303 u_int x; 304 305 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 306 x |= 1; 307 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 308 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 309 x |= 1; 310 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 311 } 312 313 void 314 gmac_stop_txdma(sc) 315 struct gmac_softc *sc; 316 { 317 u_int x; 318 319 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 320 x &= ~1; 321 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 322 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 323 x &= ~1; 324 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 325 } 326 327 void 328 gmac_stop_rxdma(sc) 329 struct gmac_softc *sc; 330 { 331 u_int x; 332 333 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 334 x &= ~1; 335 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 336 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 337 x &= ~1; 338 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 339 } 340 341 int 342 gmac_intr(v) 343 void *v; 344 { 345 struct gmac_softc *sc = v; 346 u_int status; 347 348 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 349 if (status == 0) 350 return 0; 351 352 if (status & GMAC_INT_RXDONE) 353 gmac_rint(sc); 354 355 if (status & GMAC_INT_TXEMPTY) 356 gmac_tint(sc); 357 358 #if NRND > 0 359 rnd_add_uint32(&sc->sc_rnd_source, status); 360 #endif 361 return 1; 362 } 363 364 void 365 gmac_tint(sc) 366 struct gmac_softc *sc; 367 { 368 struct ifnet *ifp = &sc->sc_if; 369 370 ifp->if_flags &= ~IFF_OACTIVE; 371 ifp->if_timer = 0; 372 gmac_start(ifp); 373 } 374 375 void 376 gmac_rint(sc) 377 struct gmac_softc *sc; 378 { 379 struct ifnet *ifp = &sc->sc_if; 380 volatile struct gmac_dma *dp; 381 struct mbuf *m; 382 int i, j, len; 383 u_int cmd; 384 385 for (i = sc->sc_rxlast;; i++) { 386 if (i == NRXBUF) 387 i = 0; 388 389 dp = &sc->sc_rxlist[i]; 390 cmd = le32toh(dp->cmd); 391 if (cmd & GMAC_OWN) 392 break; 393 len = (cmd >> 16) & GMAC_LEN_MASK; 394 len -= 4; /* CRC */ 395 396 if (le32toh(dp->cmd_hi) & 0x40000000) { 397 ifp->if_ierrors++; 398 goto next; 399 } 400 401 m = gmac_get(sc, sc->sc_rxbuf[i], len); 402 if (m == NULL) { 403 ifp->if_ierrors++; 404 goto next; 405 } 406 407 #if NBPFILTER > 0 408 /* 409 * Check if there's a BPF listener on this interface. 410 * If so, hand off the raw packet to BPF. 411 */ 412 if (ifp->if_bpf) 413 bpf_mtap(ifp->if_bpf, m); 414 #endif 415 (*ifp->if_input)(ifp, m); 416 ifp->if_ipackets++; 417 418 next: 419 dp->cmd_hi = 0; 420 __asm volatile ("sync"); 421 dp->cmd = htole32(GMAC_OWN); 422 } 423 sc->sc_rxlast = i; 424 425 /* XXX Make sure free buffers have GMAC_OWN. */ 426 i++; 427 for (j = 1; j < NRXBUF; j++) { 428 if (i == NRXBUF) 429 i = 0; 430 dp = &sc->sc_rxlist[i++]; 431 dp->cmd = htole32(GMAC_OWN); 432 } 433 } 434 435 struct mbuf * 436 gmac_get(sc, pkt, totlen) 437 struct gmac_softc *sc; 438 caddr_t pkt; 439 int totlen; 440 { 441 struct mbuf *m; 442 struct mbuf *top, **mp; 443 int len; 444 445 MGETHDR(m, M_DONTWAIT, MT_DATA); 446 if (m == 0) 447 return 0; 448 m->m_pkthdr.rcvif = &sc->sc_if; 449 m->m_pkthdr.len = totlen; 450 len = MHLEN; 451 top = 0; 452 mp = ⊤ 453 454 while (totlen > 0) { 455 if (top) { 456 MGET(m, M_DONTWAIT, MT_DATA); 457 if (m == 0) { 458 m_freem(top); 459 return 0; 460 } 461 len = MLEN; 462 } 463 if (totlen >= MINCLSIZE) { 464 MCLGET(m, M_DONTWAIT); 465 if ((m->m_flags & M_EXT) == 0) { 466 m_free(m); 467 m_freem(top); 468 return 0; 469 } 470 len = MCLBYTES; 471 } 472 m->m_len = len = min(totlen, len); 473 memcpy(mtod(m, caddr_t), pkt, len); 474 pkt += len; 475 totlen -= len; 476 *mp = m; 477 mp = &m->m_next; 478 } 479 480 return top; 481 } 482 483 void 484 gmac_start(ifp) 485 struct ifnet *ifp; 486 { 487 struct gmac_softc *sc = ifp->if_softc; 488 struct mbuf *m; 489 caddr_t buff; 490 int i, tlen; 491 volatile struct gmac_dma *dp; 492 493 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 494 return; 495 496 for (;;) { 497 if (ifp->if_flags & IFF_OACTIVE) 498 break; 499 500 IFQ_DEQUEUE(&ifp->if_snd, m); 501 if (m == 0) 502 break; 503 504 /* 5 seconds to watch for failing to transmit */ 505 ifp->if_timer = 5; 506 ifp->if_opackets++; /* # of pkts */ 507 508 i = sc->sc_txnext; 509 buff = sc->sc_txbuf[i]; 510 tlen = gmac_put(sc, buff, m); 511 512 dp = &sc->sc_txlist[i]; 513 dp->cmd_hi = 0; 514 dp->address_hi = 0; 515 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 516 517 i++; 518 if (i == NTXBUF) 519 i = 0; 520 __asm volatile ("sync"); 521 522 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 523 sc->sc_txnext = i; 524 525 #if NBPFILTER > 0 526 /* 527 * If BPF is listening on this interface, let it see the 528 * packet before we commit it to the wire. 529 */ 530 if (ifp->if_bpf) 531 bpf_mtap(ifp->if_bpf, m); 532 #endif 533 m_freem(m); 534 535 i++; 536 if (i == NTXBUF) 537 i = 0; 538 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 539 ifp->if_flags |= IFF_OACTIVE; 540 break; 541 } 542 } 543 } 544 545 int 546 gmac_put(sc, buff, m) 547 struct gmac_softc *sc; 548 caddr_t buff; 549 struct mbuf *m; 550 { 551 int len, tlen = 0; 552 553 for (; m; m = m->m_next) { 554 len = m->m_len; 555 if (len == 0) 556 continue; 557 memcpy(buff, mtod(m, caddr_t), len); 558 buff += len; 559 tlen += len; 560 } 561 if (tlen > 2048) 562 panic("%s: gmac_put packet overflow", sc->sc_dev.dv_xname); 563 564 return tlen; 565 } 566 567 void 568 gmac_reset(sc) 569 struct gmac_softc *sc; 570 { 571 int i, s; 572 573 s = splnet(); 574 575 gmac_stop_txdma(sc); 576 gmac_stop_rxdma(sc); 577 578 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 579 for (i = 10; i > 0; i--) { 580 delay(300000); /* XXX long delay */ 581 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 582 break; 583 } 584 if (i == 0) 585 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 586 587 sc->sc_txnext = 0; 588 sc->sc_rxlast = 0; 589 for (i = 0; i < NRXBUF; i++) 590 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 591 __asm volatile ("sync"); 592 593 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 594 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 595 vtophys((vaddr_t)sc->sc_txlist)); 596 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 597 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 598 vtophys((vaddr_t)sc->sc_rxlist)); 599 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 600 601 splx(s); 602 } 603 604 void 605 gmac_stop(sc) 606 struct gmac_softc *sc; 607 { 608 struct ifnet *ifp = &sc->sc_if; 609 int s; 610 611 s = splnet(); 612 613 callout_stop(&sc->sc_tick_ch); 614 mii_down(&sc->sc_mii); 615 616 gmac_stop_txdma(sc); 617 gmac_stop_rxdma(sc); 618 619 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 620 621 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 622 ifp->if_timer = 0; 623 624 splx(s); 625 } 626 627 void 628 gmac_init_mac(sc) 629 struct gmac_softc *sc; 630 { 631 int i, tb; 632 char *laddr = sc->sc_laddr; 633 634 if ((mfpvr() >> 16) == MPC601) 635 tb = mfrtcl(); 636 else 637 tb = mftbl(); 638 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 639 640 /* init-mii */ 641 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 642 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 643 644 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 645 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 646 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 647 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 648 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 649 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 650 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 651 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 652 gmac_write_reg(sc, GMAC_PASIZE, 7); 653 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 654 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10); 655 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 656 657 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 658 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 659 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 660 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 661 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 662 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 663 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 664 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 665 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 666 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 667 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 668 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 669 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 670 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 671 672 for (i = 0; i < 0x6c; i += 4) 673 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 674 675 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 676 677 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 678 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 679 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 680 } else { 681 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 682 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 683 } 684 685 if (0) /* g-bit? */ 686 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 687 else 688 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 689 } 690 691 void 692 gmac_setladrf(sc) 693 struct gmac_softc *sc; 694 { 695 struct ifnet *ifp = &sc->sc_if; 696 struct ether_multi *enm; 697 struct ether_multistep step; 698 struct ethercom *ec = &sc->sc_ethercom; 699 u_int32_t crc; 700 u_int32_t hash[16]; 701 u_int v; 702 int i; 703 704 /* Clear hash table */ 705 for (i = 0; i < 16; i++) 706 hash[i] = 0; 707 708 /* Get current RX configuration */ 709 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 710 711 if ((ifp->if_flags & IFF_PROMISC) != 0) { 712 /* Turn on promiscuous mode; turn off the hash filter */ 713 v |= GMAC_RXMAC_PR; 714 v &= ~GMAC_RXMAC_HEN; 715 ifp->if_flags |= IFF_ALLMULTI; 716 goto chipit; 717 } 718 719 /* Turn off promiscuous mode; turn on the hash filter */ 720 v &= ~GMAC_RXMAC_PR; 721 v |= GMAC_RXMAC_HEN; 722 723 /* 724 * Set up multicast address filter by passing all multicast addresses 725 * through a crc generator, and then using the high order 8 bits as an 726 * index into the 256 bit logical address filter. The high order bit 727 * selects the word, while the rest of the bits select the bit within 728 * the word. 729 */ 730 731 ETHER_FIRST_MULTI(step, ec, enm); 732 while (enm != NULL) { 733 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 734 /* 735 * We must listen to a range of multicast addresses. 736 * For now, just accept all multicasts, rather than 737 * trying to set only those filter bits needed to match 738 * the range. (At this time, the only use of address 739 * ranges is for IP multicast routing, for which the 740 * range is big enough to require all bits set.) 741 */ 742 for (i = 0; i < 16; i++) 743 hash[i] = 0xffff; 744 ifp->if_flags |= IFF_ALLMULTI; 745 goto chipit; 746 } 747 748 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 749 750 /* Just want the 8 most significant bits. */ 751 crc >>= 24; 752 753 /* Set the corresponding bit in the filter. */ 754 hash[crc >> 4] |= 1 << (crc & 0xf); 755 756 ETHER_NEXT_MULTI(step, enm); 757 } 758 759 ifp->if_flags &= ~IFF_ALLMULTI; 760 761 chipit: 762 /* Now load the hash table into the chip */ 763 for (i = 0; i < 16; i++) 764 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 765 766 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 767 } 768 769 void 770 gmac_init(sc) 771 struct gmac_softc *sc; 772 { 773 struct ifnet *ifp = &sc->sc_if; 774 775 gmac_stop_txdma(sc); 776 gmac_stop_rxdma(sc); 777 778 gmac_init_mac(sc); 779 gmac_setladrf(sc); 780 781 gmac_start_txdma(sc); 782 gmac_start_rxdma(sc); 783 784 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 785 786 ifp->if_flags |= IFF_RUNNING; 787 ifp->if_flags &= ~IFF_OACTIVE; 788 ifp->if_timer = 0; 789 790 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 791 792 gmac_start(ifp); 793 } 794 795 int 796 gmac_ioctl(ifp, cmd, data) 797 struct ifnet *ifp; 798 u_long cmd; 799 caddr_t data; 800 { 801 struct gmac_softc *sc = ifp->if_softc; 802 struct ifaddr *ifa = (struct ifaddr *)data; 803 struct ifreq *ifr = (struct ifreq *)data; 804 int s, error = 0; 805 806 s = splnet(); 807 808 switch (cmd) { 809 810 case SIOCSIFADDR: 811 ifp->if_flags |= IFF_UP; 812 813 switch (ifa->ifa_addr->sa_family) { 814 #ifdef INET 815 case AF_INET: 816 gmac_init(sc); 817 arp_ifinit(ifp, ifa); 818 break; 819 #endif 820 #ifdef NS 821 case AF_NS: 822 { 823 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 824 825 if (ns_nullhost(*ina)) 826 ina->x_host = 827 *(union ns_host *)LLADDR(ifp->if_sadl); 828 else { 829 memcpy(LLADDR(ifp->if_sadl), 830 ina->x_host.c_host, 831 sizeof(sc->sc_enaddr)); 832 } 833 /* Set new address. */ 834 gmac_init(sc); 835 break; 836 } 837 #endif 838 default: 839 gmac_init(sc); 840 break; 841 } 842 break; 843 844 case SIOCSIFFLAGS: 845 if ((ifp->if_flags & IFF_UP) == 0 && 846 (ifp->if_flags & IFF_RUNNING) != 0) { 847 /* 848 * If interface is marked down and it is running, then 849 * stop it. 850 */ 851 gmac_stop(sc); 852 ifp->if_flags &= ~IFF_RUNNING; 853 } else if ((ifp->if_flags & IFF_UP) != 0 && 854 (ifp->if_flags & IFF_RUNNING) == 0) { 855 /* 856 * If interface is marked up and it is stopped, then 857 * start it. 858 */ 859 gmac_init(sc); 860 } else { 861 /* 862 * Reset the interface to pick up changes in any other 863 * flags that affect hardware registers. 864 */ 865 gmac_reset(sc); 866 gmac_init(sc); 867 } 868 #ifdef GMAC_DEBUG 869 if (ifp->if_flags & IFF_DEBUG) 870 sc->sc_flags |= GMAC_DEBUGFLAG; 871 #endif 872 break; 873 874 case SIOCADDMULTI: 875 case SIOCDELMULTI: 876 error = (cmd == SIOCADDMULTI) ? 877 ether_addmulti(ifr, &sc->sc_ethercom) : 878 ether_delmulti(ifr, &sc->sc_ethercom); 879 880 if (error == ENETRESET) { 881 /* 882 * Multicast list has changed; set the hardware filter 883 * accordingly. 884 */ 885 if (ifp->if_flags & IFF_RUNNING) { 886 gmac_init(sc); 887 /* gmac_setladrf(sc); */ 888 } 889 error = 0; 890 } 891 break; 892 893 case SIOCGIFMEDIA: 894 case SIOCSIFMEDIA: 895 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 896 break; 897 898 default: 899 error = EINVAL; 900 } 901 902 splx(s); 903 return error; 904 } 905 906 void 907 gmac_watchdog(ifp) 908 struct ifnet *ifp; 909 { 910 struct gmac_softc *sc = ifp->if_softc; 911 912 printf("%s: device timeout\n", ifp->if_xname); 913 ifp->if_oerrors++; 914 915 gmac_reset(sc); 916 gmac_init(sc); 917 } 918 919 int 920 gmac_mediachange(ifp) 921 struct ifnet *ifp; 922 { 923 struct gmac_softc *sc = ifp->if_softc; 924 925 return mii_mediachg(&sc->sc_mii); 926 } 927 928 void 929 gmac_mediastatus(ifp, ifmr) 930 struct ifnet *ifp; 931 struct ifmediareq *ifmr; 932 { 933 struct gmac_softc *sc = ifp->if_softc; 934 935 mii_pollstat(&sc->sc_mii); 936 937 ifmr->ifm_status = sc->sc_mii.mii_media_status; 938 ifmr->ifm_active = sc->sc_mii.mii_media_active; 939 } 940 941 int 942 gmac_mii_readreg(dev, phy, reg) 943 struct device *dev; 944 int phy, reg; 945 { 946 struct gmac_softc *sc = (void *)dev; 947 int i; 948 949 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 950 0x60020000 | (phy << 23) | (reg << 18)); 951 952 for (i = 1000; i >= 0; i -= 10) { 953 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 954 break; 955 delay(10); 956 } 957 if (i < 0) { 958 printf("%s: gmac_mii_readreg: timeout\n", sc->sc_dev.dv_xname); 959 return 0; 960 } 961 962 return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 963 } 964 965 void 966 gmac_mii_writereg(dev, phy, reg, val) 967 struct device *dev; 968 int phy, reg, val; 969 { 970 struct gmac_softc *sc = (void *)dev; 971 int i; 972 973 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 974 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 975 976 for (i = 1000; i >= 0; i -= 10) { 977 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 978 break; 979 delay(10); 980 } 981 if (i < 0) 982 printf("%s: gmac_mii_writereg: timeout\n", sc->sc_dev.dv_xname); 983 } 984 985 void 986 gmac_mii_statchg(dev) 987 struct device *dev; 988 { 989 struct gmac_softc *sc = (void *)dev; 990 991 gmac_stop_txdma(sc); 992 gmac_stop_rxdma(sc); 993 994 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 995 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 996 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 997 } else { 998 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 999 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 1000 } 1001 1002 if (0) /* g-bit? */ 1003 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 1004 else 1005 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 1006 1007 gmac_start_txdma(sc); 1008 gmac_start_rxdma(sc); 1009 } 1010 1011 void 1012 gmac_mii_tick(v) 1013 void *v; 1014 { 1015 struct gmac_softc *sc = v; 1016 int s; 1017 1018 s = splnet(); 1019 mii_tick(&sc->sc_mii); 1020 splx(s); 1021 1022 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 1023 } 1024
Indexes created Tue Sep 30 20:09:53 GMT 2025